[WebAssembly] SIMD integer min and max instructions
Summary: Introduces a clang builtins and LLVM intrinsics representing integer min/max instructions. These instructions have not been merged to the SIMD spec proposal yet, so they are currently opt-in only via builtins and not produced by general pattern matching. If these instructions are accepted into the spec proposal the builtins and intrinsics will be replaced with normal pattern matching. Defined in https://github.com/WebAssembly/simd/pull/27. Reviewers: aheejin Reviewed By: aheejin Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D69696
This commit is contained in:
Thomas Lively
parent
10c1d0a452
commit
a07019a275
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@ -98,6 +98,21 @@ TARGET_BUILTIN(__builtin_wasm_sub_saturate_u_i8x16, "V16cV16cV16c", "nc", "simd1
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TARGET_BUILTIN(__builtin_wasm_sub_saturate_s_i16x8, "V8sV8sV8s", "nc", "simd128")
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TARGET_BUILTIN(__builtin_wasm_sub_saturate_u_i16x8, "V8sV8sV8s", "nc", "simd128")
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// TODO: Remove builtins and rely on codegen patterns once these are officially
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// merged to the spec proposal
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TARGET_BUILTIN(__builtin_wasm_min_s_i8x16, "V16cV16cV16c", "nc", "simd128")
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TARGET_BUILTIN(__builtin_wasm_min_u_i8x16, "V16cV16cV16c", "nc", "simd128")
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TARGET_BUILTIN(__builtin_wasm_max_s_i8x16, "V16cV16cV16c", "nc", "simd128")
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TARGET_BUILTIN(__builtin_wasm_max_u_i8x16, "V16cV16cV16c", "nc", "simd128")
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TARGET_BUILTIN(__builtin_wasm_min_s_i16x8, "V8sV8sV8s", "nc", "simd128")
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TARGET_BUILTIN(__builtin_wasm_min_u_i16x8, "V8sV8sV8s", "nc", "simd128")
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TARGET_BUILTIN(__builtin_wasm_max_s_i16x8, "V8sV8sV8s", "nc", "simd128")
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TARGET_BUILTIN(__builtin_wasm_max_u_i16x8, "V8sV8sV8s", "nc", "simd128")
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TARGET_BUILTIN(__builtin_wasm_min_s_i32x4, "V4iV4iV4i", "nc", "simd128")
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TARGET_BUILTIN(__builtin_wasm_min_u_i32x4, "V4iV4iV4i", "nc", "simd128")
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TARGET_BUILTIN(__builtin_wasm_max_s_i32x4, "V4iV4iV4i", "nc", "simd128")
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TARGET_BUILTIN(__builtin_wasm_max_u_i32x4, "V4iV4iV4i", "nc", "simd128")
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TARGET_BUILTIN(__builtin_wasm_bitselect, "V4iV4iV4iV4i", "nc", "simd128")
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TARGET_BUILTIN(__builtin_wasm_any_true_i8x16, "iV16c", "nc", "simd128")
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@ -14318,6 +14318,48 @@ Value *CodeGenFunction::EmitWebAssemblyBuiltinExpr(unsigned BuiltinID,
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ConvertType(E->getType()));
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return Builder.CreateCall(Callee, {V1, V2, C});
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}
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case WebAssembly::BI__builtin_wasm_min_s_i8x16:
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case WebAssembly::BI__builtin_wasm_min_u_i8x16:
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case WebAssembly::BI__builtin_wasm_max_s_i8x16:
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case WebAssembly::BI__builtin_wasm_max_u_i8x16:
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case WebAssembly::BI__builtin_wasm_min_s_i16x8:
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case WebAssembly::BI__builtin_wasm_min_u_i16x8:
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case WebAssembly::BI__builtin_wasm_max_s_i16x8:
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case WebAssembly::BI__builtin_wasm_max_u_i16x8:
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case WebAssembly::BI__builtin_wasm_min_s_i32x4:
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case WebAssembly::BI__builtin_wasm_min_u_i32x4:
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case WebAssembly::BI__builtin_wasm_max_s_i32x4:
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case WebAssembly::BI__builtin_wasm_max_u_i32x4: {
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unsigned IntNo;
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switch (BuiltinID) {
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case WebAssembly::BI__builtin_wasm_min_s_i8x16:
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case WebAssembly::BI__builtin_wasm_min_s_i16x8:
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case WebAssembly::BI__builtin_wasm_min_s_i32x4:
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IntNo = Intrinsic::wasm_min_signed;
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break;
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case WebAssembly::BI__builtin_wasm_min_u_i8x16:
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case WebAssembly::BI__builtin_wasm_min_u_i16x8:
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case WebAssembly::BI__builtin_wasm_min_u_i32x4:
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IntNo = Intrinsic::wasm_min_unsigned;
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break;
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case WebAssembly::BI__builtin_wasm_max_s_i8x16:
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case WebAssembly::BI__builtin_wasm_max_s_i16x8:
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case WebAssembly::BI__builtin_wasm_max_s_i32x4:
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IntNo = Intrinsic::wasm_max_signed;
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break;
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case WebAssembly::BI__builtin_wasm_max_u_i8x16:
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case WebAssembly::BI__builtin_wasm_max_u_i16x8:
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case WebAssembly::BI__builtin_wasm_max_u_i32x4:
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IntNo = Intrinsic::wasm_max_unsigned;
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break;
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default:
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llvm_unreachable("unexpected builtin ID");
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}
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Value *LHS = EmitScalarExpr(E->getArg(0));
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Value *RHS = EmitScalarExpr(E->getArg(1));
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Function *Callee = CGM.getIntrinsic(IntNo, ConvertType(E->getType()));
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return Builder.CreateCall(Callee, {LHS, RHS});
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}
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case WebAssembly::BI__builtin_wasm_any_true_i8x16:
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case WebAssembly::BI__builtin_wasm_any_true_i16x8:
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case WebAssembly::BI__builtin_wasm_any_true_i32x4:
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@ -352,6 +352,90 @@ i16x8 sub_saturate_u_i16x8(i16x8 x, i16x8 y) {
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// WEBASSEMBLY-NEXT: ret
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}
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i8x16 min_s_i8x16(i8x16 x, i8x16 y) {
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return __builtin_wasm_min_s_i8x16(x, y);
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// WEBASSEMBLY: call <16 x i8> @llvm.wasm.min.signed.v16i8(
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// WEBASSEMBLY-SAME: <16 x i8> %x, <16 x i8> %y)
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// WEBASSEMBLY-NEXT: ret
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}
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i8x16 min_u_i8x16(i8x16 x, i8x16 y) {
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return __builtin_wasm_min_u_i8x16(x, y);
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// WEBASSEMBLY: call <16 x i8> @llvm.wasm.min.unsigned.v16i8(
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// WEBASSEMBLY-SAME: <16 x i8> %x, <16 x i8> %y)
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// WEBASSEMBLY-NEXT: ret
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}
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i8x16 max_s_i8x16(i8x16 x, i8x16 y) {
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return __builtin_wasm_max_s_i8x16(x, y);
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// WEBASSEMBLY: call <16 x i8> @llvm.wasm.max.signed.v16i8(
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// WEBASSEMBLY-SAME: <16 x i8> %x, <16 x i8> %y)
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// WEBASSEMBLY-NEXT: ret
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}
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i8x16 max_u_i8x16(i8x16 x, i8x16 y) {
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return __builtin_wasm_max_u_i8x16(x, y);
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// WEBASSEMBLY: call <16 x i8> @llvm.wasm.max.unsigned.v16i8(
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// WEBASSEMBLY-SAME: <16 x i8> %x, <16 x i8> %y)
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// WEBASSEMBLY-NEXT: ret
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}
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i16x8 min_s_i16x8(i16x8 x, i16x8 y) {
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return __builtin_wasm_min_s_i16x8(x, y);
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// WEBASSEMBLY: call <8 x i16> @llvm.wasm.min.signed.v8i16(
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// WEBASSEMBLY-SAME: <8 x i16> %x, <8 x i16> %y)
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// WEBASSEMBLY-NEXT: ret
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}
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i16x8 min_u_i16x8(i16x8 x, i16x8 y) {
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return __builtin_wasm_min_u_i16x8(x, y);
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// WEBASSEMBLY: call <8 x i16> @llvm.wasm.min.unsigned.v8i16(
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// WEBASSEMBLY-SAME: <8 x i16> %x, <8 x i16> %y)
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// WEBASSEMBLY-NEXT: ret
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}
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i16x8 max_s_i16x8(i16x8 x, i16x8 y) {
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return __builtin_wasm_max_s_i16x8(x, y);
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// WEBASSEMBLY: call <8 x i16> @llvm.wasm.max.signed.v8i16(
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// WEBASSEMBLY-SAME: <8 x i16> %x, <8 x i16> %y)
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// WEBASSEMBLY-NEXT: ret
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}
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i16x8 max_u_i16x8(i16x8 x, i16x8 y) {
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return __builtin_wasm_max_u_i16x8(x, y);
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// WEBASSEMBLY: call <8 x i16> @llvm.wasm.max.unsigned.v8i16(
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// WEBASSEMBLY-SAME: <8 x i16> %x, <8 x i16> %y)
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// WEBASSEMBLY-NEXT: ret
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}
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i32x4 min_s_i32x4(i32x4 x, i32x4 y) {
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return __builtin_wasm_min_s_i32x4(x, y);
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// WEBASSEMBLY: call <4 x i32> @llvm.wasm.min.signed.v4i32(
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// WEBASSEMBLY-SAME: <4 x i32> %x, <4 x i32> %y)
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// WEBASSEMBLY-NEXT: ret
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}
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i32x4 min_u_i32x4(i32x4 x, i32x4 y) {
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return __builtin_wasm_min_u_i32x4(x, y);
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// WEBASSEMBLY: call <4 x i32> @llvm.wasm.min.unsigned.v4i32(
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// WEBASSEMBLY-SAME: <4 x i32> %x, <4 x i32> %y)
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// WEBASSEMBLY-NEXT: ret
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}
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i32x4 max_s_i32x4(i32x4 x, i32x4 y) {
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return __builtin_wasm_max_s_i32x4(x, y);
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// WEBASSEMBLY: call <4 x i32> @llvm.wasm.max.signed.v4i32(
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// WEBASSEMBLY-SAME: <4 x i32> %x, <4 x i32> %y)
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// WEBASSEMBLY-NEXT: ret
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}
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i32x4 max_u_i32x4(i32x4 x, i32x4 y) {
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return __builtin_wasm_max_u_i32x4(x, y);
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// WEBASSEMBLY: call <4 x i32> @llvm.wasm.max.unsigned.v4i32(
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// WEBASSEMBLY-SAME: <4 x i32> %x, <4 x i32> %y)
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// WEBASSEMBLY-NEXT: ret
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}
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i32x4 bitselect(i32x4 x, i32x4 y, i32x4 c) {
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return __builtin_wasm_bitselect(x, y, c);
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// WEBASSEMBLY: call <4 x i32> @llvm.wasm.bitselect.v4i32(
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@ -112,6 +112,26 @@ def int_wasm_sub_saturate_unsigned :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>],
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[IntrNoMem, IntrSpeculatable]>;
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// TODO: Remove intrinsics and rely on codegen patterns once these are
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// officially merged to the spec proposal
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def int_wasm_min_signed :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_min_unsigned :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_max_signed :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_max_unsigned :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_bitselect :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
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@ -727,8 +727,17 @@ defm SUB_SAT_U :
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SIMDBinaryIntSmall<int_wasm_sub_saturate_unsigned, "sub_saturate_u", 92>;
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// Integer multiplication: mul
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let isCommutable = 1 in
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defm MUL : SIMDBinaryIntNoI64x2<mul, "mul", 93>;
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// Integer min_s / min_u / max_s / max_u
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let isCommutable = 1 in {
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defm MIN_S : SIMDBinaryIntNoI64x2<int_wasm_min_signed, "min_s", 94>;
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defm MIN_U : SIMDBinaryIntNoI64x2<int_wasm_min_unsigned, "min_u", 95>;
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defm MAX_S : SIMDBinaryIntNoI64x2<int_wasm_max_signed, "max_s", 96>;
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defm MAX_U : SIMDBinaryIntNoI64x2<int_wasm_max_unsigned, "max_u", 97>;
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} // isCommutable = 1
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//===----------------------------------------------------------------------===//
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// Floating-point unary arithmetic
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//===----------------------------------------------------------------------===//
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@ -65,6 +65,46 @@ define <16 x i8> @sub_sat_u_v16i8(<16 x i8> %x, <16 x i8> %y) {
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ret <16 x i8> %a
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}
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; CHECK-LABEL: min_s_v16i8:
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; SIMD128-NEXT: .functype min_s_v16i8 (v128, v128) -> (v128){{$}}
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; SIMD128-NEXT: i8x16.min_s $push[[R:[0-9]+]]=, $0, $1{{$}}
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; SIMD128-NEXT: return $pop[[R]]{{$}}
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declare <16 x i8> @llvm.wasm.min.signed.v16i8(<16 x i8>, <16 x i8>)
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define <16 x i8> @min_s_v16i8(<16 x i8> %x, <16 x i8> %y) {
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%a = call <16 x i8> @llvm.wasm.min.signed.v16i8(<16 x i8> %x, <16 x i8> %y)
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ret <16 x i8> %a
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}
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; CHECK-LABEL: min_u_v16i8:
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; SIMD128-NEXT: .functype min_u_v16i8 (v128, v128) -> (v128){{$}}
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; SIMD128-NEXT: i8x16.min_u $push[[R:[0-9]+]]=, $0, $1{{$}}
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; SIMD128-NEXT: return $pop[[R]]{{$}}
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declare <16 x i8> @llvm.wasm.min.unsigned.v16i8(<16 x i8>, <16 x i8>)
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define <16 x i8> @min_u_v16i8(<16 x i8> %x, <16 x i8> %y) {
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%a = call <16 x i8> @llvm.wasm.min.unsigned.v16i8(<16 x i8> %x, <16 x i8> %y)
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ret <16 x i8> %a
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}
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; CHECK-LABEL: max_s_v16i8:
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; SIMD128-NEXT: .functype max_s_v16i8 (v128, v128) -> (v128){{$}}
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; SIMD128-NEXT: i8x16.max_s $push[[R:[0-9]+]]=, $0, $1{{$}}
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; SIMD128-NEXT: return $pop[[R]]{{$}}
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declare <16 x i8> @llvm.wasm.max.signed.v16i8(<16 x i8>, <16 x i8>)
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define <16 x i8> @max_s_v16i8(<16 x i8> %x, <16 x i8> %y) {
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%a = call <16 x i8> @llvm.wasm.max.signed.v16i8(<16 x i8> %x, <16 x i8> %y)
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ret <16 x i8> %a
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}
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; CHECK-LABEL: max_u_v16i8:
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; SIMD128-NEXT: .functype max_u_v16i8 (v128, v128) -> (v128){{$}}
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; SIMD128-NEXT: i8x16.max_u $push[[R:[0-9]+]]=, $0, $1{{$}}
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; SIMD128-NEXT: return $pop[[R]]{{$}}
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declare <16 x i8> @llvm.wasm.max.unsigned.v16i8(<16 x i8>, <16 x i8>)
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define <16 x i8> @max_u_v16i8(<16 x i8> %x, <16 x i8> %y) {
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%a = call <16 x i8> @llvm.wasm.max.unsigned.v16i8(<16 x i8> %x, <16 x i8> %y)
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ret <16 x i8> %a
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}
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; CHECK-LABEL: any_v16i8:
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; SIMD128-NEXT: .functype any_v16i8 (v128) -> (i32){{$}}
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; SIMD128-NEXT: i8x16.any_true $push[[R:[0-9]+]]=, $0{{$}}
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@ -168,6 +208,46 @@ define <8 x i16> @sub_sat_u_v8i16(<8 x i16> %x, <8 x i16> %y) {
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ret <8 x i16> %a
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}
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; CHECK-LABEL: min_s_v8i16:
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; SIMD128-NEXT: .functype min_s_v8i16 (v128, v128) -> (v128){{$}}
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; SIMD128-NEXT: i16x8.min_s $push[[R:[0-9]+]]=, $0, $1{{$}}
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; SIMD128-NEXT: return $pop[[R]]{{$}}
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declare <8 x i16> @llvm.wasm.min.signed.v8i16(<8 x i16>, <8 x i16>)
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define <8 x i16> @min_s_v8i16(<8 x i16> %x, <8 x i16> %y) {
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%a = call <8 x i16> @llvm.wasm.min.signed.v8i16(<8 x i16> %x, <8 x i16> %y)
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ret <8 x i16> %a
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}
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; CHECK-LABEL: min_u_v8i16:
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; SIMD128-NEXT: .functype min_u_v8i16 (v128, v128) -> (v128){{$}}
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; SIMD128-NEXT: i16x8.min_u $push[[R:[0-9]+]]=, $0, $1{{$}}
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; SIMD128-NEXT: return $pop[[R]]{{$}}
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declare <8 x i16> @llvm.wasm.min.unsigned.v8i16(<8 x i16>, <8 x i16>)
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define <8 x i16> @min_u_v8i16(<8 x i16> %x, <8 x i16> %y) {
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%a = call <8 x i16> @llvm.wasm.min.unsigned.v8i16(<8 x i16> %x, <8 x i16> %y)
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ret <8 x i16> %a
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}
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; CHECK-LABEL: max_s_v8i16:
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; SIMD128-NEXT: .functype max_s_v8i16 (v128, v128) -> (v128){{$}}
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; SIMD128-NEXT: i16x8.max_s $push[[R:[0-9]+]]=, $0, $1{{$}}
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; SIMD128-NEXT: return $pop[[R]]{{$}}
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declare <8 x i16> @llvm.wasm.max.signed.v8i16(<8 x i16>, <8 x i16>)
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define <8 x i16> @max_s_v8i16(<8 x i16> %x, <8 x i16> %y) {
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%a = call <8 x i16> @llvm.wasm.max.signed.v8i16(<8 x i16> %x, <8 x i16> %y)
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ret <8 x i16> %a
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}
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; CHECK-LABEL: max_u_v8i16:
|
||||
; SIMD128-NEXT: .functype max_u_v8i16 (v128, v128) -> (v128){{$}}
|
||||
; SIMD128-NEXT: i16x8.max_u $push[[R:[0-9]+]]=, $0, $1{{$}}
|
||||
; SIMD128-NEXT: return $pop[[R]]{{$}}
|
||||
declare <8 x i16> @llvm.wasm.max.unsigned.v8i16(<8 x i16>, <8 x i16>)
|
||||
define <8 x i16> @max_u_v8i16(<8 x i16> %x, <8 x i16> %y) {
|
||||
%a = call <8 x i16> @llvm.wasm.max.unsigned.v8i16(<8 x i16> %x, <8 x i16> %y)
|
||||
ret <8 x i16> %a
|
||||
}
|
||||
|
||||
; CHECK-LABEL: any_v8i16:
|
||||
; SIMD128-NEXT: .functype any_v8i16 (v128) -> (i32){{$}}
|
||||
; SIMD128-NEXT: i16x8.any_true $push[[R:[0-9]+]]=, $0{{$}}
|
||||
|
|
@ -267,6 +347,46 @@ define <8 x i16> @widen_high_unsigned_v8i16(<16 x i8> %v) {
|
|||
; ==============================================================================
|
||||
; 4 x i32
|
||||
; ==============================================================================
|
||||
; CHECK-LABEL: min_s_v4i32:
|
||||
; SIMD128-NEXT: .functype min_s_v4i32 (v128, v128) -> (v128){{$}}
|
||||
; SIMD128-NEXT: i32x4.min_s $push[[R:[0-9]+]]=, $0, $1{{$}}
|
||||
; SIMD128-NEXT: return $pop[[R]]{{$}}
|
||||
declare <4 x i32> @llvm.wasm.min.signed.v4i32(<4 x i32>, <4 x i32>)
|
||||
define <4 x i32> @min_s_v4i32(<4 x i32> %x, <4 x i32> %y) {
|
||||
%a = call <4 x i32> @llvm.wasm.min.signed.v4i32(<4 x i32> %x, <4 x i32> %y)
|
||||
ret <4 x i32> %a
|
||||
}
|
||||
|
||||
; CHECK-LABEL: min_u_v4i32:
|
||||
; SIMD128-NEXT: .functype min_u_v4i32 (v128, v128) -> (v128){{$}}
|
||||
; SIMD128-NEXT: i32x4.min_u $push[[R:[0-9]+]]=, $0, $1{{$}}
|
||||
; SIMD128-NEXT: return $pop[[R]]{{$}}
|
||||
declare <4 x i32> @llvm.wasm.min.unsigned.v4i32(<4 x i32>, <4 x i32>)
|
||||
define <4 x i32> @min_u_v4i32(<4 x i32> %x, <4 x i32> %y) {
|
||||
%a = call <4 x i32> @llvm.wasm.min.unsigned.v4i32(<4 x i32> %x, <4 x i32> %y)
|
||||
ret <4 x i32> %a
|
||||
}
|
||||
|
||||
; CHECK-LABEL: max_s_v4i32:
|
||||
; SIMD128-NEXT: .functype max_s_v4i32 (v128, v128) -> (v128){{$}}
|
||||
; SIMD128-NEXT: i32x4.max_s $push[[R:[0-9]+]]=, $0, $1{{$}}
|
||||
; SIMD128-NEXT: return $pop[[R]]{{$}}
|
||||
declare <4 x i32> @llvm.wasm.max.signed.v4i32(<4 x i32>, <4 x i32>)
|
||||
define <4 x i32> @max_s_v4i32(<4 x i32> %x, <4 x i32> %y) {
|
||||
%a = call <4 x i32> @llvm.wasm.max.signed.v4i32(<4 x i32> %x, <4 x i32> %y)
|
||||
ret <4 x i32> %a
|
||||
}
|
||||
|
||||
; CHECK-LABEL: max_u_v4i32:
|
||||
; SIMD128-NEXT: .functype max_u_v4i32 (v128, v128) -> (v128){{$}}
|
||||
; SIMD128-NEXT: i32x4.max_u $push[[R:[0-9]+]]=, $0, $1{{$}}
|
||||
; SIMD128-NEXT: return $pop[[R]]{{$}}
|
||||
declare <4 x i32> @llvm.wasm.max.unsigned.v4i32(<4 x i32>, <4 x i32>)
|
||||
define <4 x i32> @max_u_v4i32(<4 x i32> %x, <4 x i32> %y) {
|
||||
%a = call <4 x i32> @llvm.wasm.max.unsigned.v4i32(<4 x i32> %x, <4 x i32> %y)
|
||||
ret <4 x i32> %a
|
||||
}
|
||||
|
||||
; CHECK-LABEL: any_v4i32:
|
||||
; SIMD128-NEXT: .functype any_v4i32 (v128) -> (i32){{$}}
|
||||
; SIMD128-NEXT: i32x4.any_true $push[[R:[0-9]+]]=, $0{{$}}
|
||||
|
|
|
|||
|
|
@ -283,6 +283,18 @@ main:
|
|||
# CHECK: i8x16.mul # encoding: [0xfd,0x5d]
|
||||
i8x16.mul
|
||||
|
||||
# CHECK: i8x16.min_s # encoding: [0xfd,0x5e]
|
||||
i8x16.min_s
|
||||
|
||||
# CHECK: i8x16.min_u # encoding: [0xfd,0x5f]
|
||||
i8x16.min_u
|
||||
|
||||
# CHECK: i8x16.max_s # encoding: [0xfd,0x60]
|
||||
i8x16.max_s
|
||||
|
||||
# CHECK: i8x16.max_u # encoding: [0xfd,0x61]
|
||||
i8x16.max_u
|
||||
|
||||
# CHECK: i16x8.neg # encoding: [0xfd,0x62]
|
||||
i16x8.neg
|
||||
|
||||
|
|
@ -322,6 +334,18 @@ main:
|
|||
# CHECK: i16x8.mul # encoding: [0xfd,0x6e]
|
||||
i16x8.mul
|
||||
|
||||
# CHECK: i16x8.min_s # encoding: [0xfd,0x6f]
|
||||
i16x8.min_s
|
||||
|
||||
# CHECK: i16x8.min_u # encoding: [0xfd,0x70]
|
||||
i16x8.min_u
|
||||
|
||||
# CHECK: i16x8.max_s # encoding: [0xfd,0x71]
|
||||
i16x8.max_s
|
||||
|
||||
# CHECK: i16x8.max_u # encoding: [0xfd,0x72]
|
||||
i16x8.max_u
|
||||
|
||||
# CHECK: i32x4.neg # encoding: [0xfd,0x73]
|
||||
i32x4.neg
|
||||
|
||||
|
|
@ -349,6 +373,18 @@ main:
|
|||
# CHECK: i32x4.mul # encoding: [0xfd,0x7f]
|
||||
i32x4.mul
|
||||
|
||||
# CHECK: i32x4.min_s # encoding: [0xfd,0x80,0x01]
|
||||
i32x4.min_s
|
||||
|
||||
# CHECK: i32x4.min_u # encoding: [0xfd,0x81,0x01]
|
||||
i32x4.min_u
|
||||
|
||||
# CHECK: i32x4.max_s # encoding: [0xfd,0x82,0x01]
|
||||
i32x4.max_s
|
||||
|
||||
# CHECK: i32x4.max_u # encoding: [0xfd,0x83,0x01]
|
||||
i32x4.max_u
|
||||
|
||||
# CHECK: i64x2.neg # encoding: [0xfd,0x84,0x01]
|
||||
i64x2.neg
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue