[X86][SSE] Add shuffle combining support for ISD::ANY_EXTEND_VECTOR_INREG
Reuses what we already have in place for ISD::ZERO_EXTEND_VECTOR_INREG just with a different sentinel llvm-svn: 361734
This commit is contained in:
Simon Pilgrim
parent
7b883b7ed0
commit
a044410f37
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@ -1202,7 +1202,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
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Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
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LLVM_FALLTHROUGH;
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CASE_PMOVZX(PMOVZXBW, m)
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DecodeZeroExtendMask(8, 16, getRegOperandNumElts(MI, 16, 0), ShuffleMask);
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DecodeZeroExtendMask(8, 16, getRegOperandNumElts(MI, 16, 0), false,
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ShuffleMask);
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DestName = getRegName(MI->getOperand(0).getReg());
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break;
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@ -1210,7 +1211,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
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Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
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LLVM_FALLTHROUGH;
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CASE_PMOVZX(PMOVZXBD, m)
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DecodeZeroExtendMask(8, 32, getRegOperandNumElts(MI, 32, 0), ShuffleMask);
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DecodeZeroExtendMask(8, 32, getRegOperandNumElts(MI, 32, 0), false,
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ShuffleMask);
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DestName = getRegName(MI->getOperand(0).getReg());
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break;
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@ -1218,7 +1220,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
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Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
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LLVM_FALLTHROUGH;
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CASE_PMOVZX(PMOVZXBQ, m)
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DecodeZeroExtendMask(8, 64, getRegOperandNumElts(MI, 64, 0), ShuffleMask);
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DecodeZeroExtendMask(8, 64, getRegOperandNumElts(MI, 64, 0), false,
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ShuffleMask);
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DestName = getRegName(MI->getOperand(0).getReg());
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break;
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@ -1226,7 +1229,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
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Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
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LLVM_FALLTHROUGH;
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CASE_PMOVZX(PMOVZXWD, m)
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DecodeZeroExtendMask(16, 32, getRegOperandNumElts(MI, 32, 0), ShuffleMask);
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DecodeZeroExtendMask(16, 32, getRegOperandNumElts(MI, 32, 0), false,
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ShuffleMask);
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DestName = getRegName(MI->getOperand(0).getReg());
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break;
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@ -1234,7 +1238,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
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Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
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LLVM_FALLTHROUGH;
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CASE_PMOVZX(PMOVZXWQ, m)
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DecodeZeroExtendMask(16, 64, getRegOperandNumElts(MI, 64, 0), ShuffleMask);
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DecodeZeroExtendMask(16, 64, getRegOperandNumElts(MI, 64, 0), false,
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ShuffleMask);
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DestName = getRegName(MI->getOperand(0).getReg());
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break;
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@ -1242,7 +1247,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
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Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
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LLVM_FALLTHROUGH;
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CASE_PMOVZX(PMOVZXDQ, m)
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DecodeZeroExtendMask(32, 64, getRegOperandNumElts(MI, 64, 0), ShuffleMask);
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DecodeZeroExtendMask(32, 64, getRegOperandNumElts(MI, 64, 0), false,
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ShuffleMask);
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DestName = getRegName(MI->getOperand(0).getReg());
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break;
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}
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@ -383,7 +383,8 @@ void DecodeVPERMMask(unsigned NumElts, unsigned Imm,
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}
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void DecodeZeroExtendMask(unsigned SrcScalarBits, unsigned DstScalarBits,
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unsigned NumDstElts, SmallVectorImpl<int> &Mask) {
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unsigned NumDstElts, bool IsAnyExtend,
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SmallVectorImpl<int> &Mask) {
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unsigned Scale = DstScalarBits / SrcScalarBits;
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assert(SrcScalarBits < DstScalarBits &&
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"Expected zero extension mask to increase scalar size");
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@ -391,7 +392,7 @@ void DecodeZeroExtendMask(unsigned SrcScalarBits, unsigned DstScalarBits,
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for (unsigned i = 0; i != NumDstElts; i++) {
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Mask.push_back(i);
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for (unsigned j = 1; j != Scale; j++)
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Mask.push_back(SM_SentinelZero);
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Mask.push_back(IsAnyExtend ? SM_SentinelUndef : SM_SentinelZero);
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}
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}
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@ -136,7 +136,7 @@ void DecodeVPPERMMask(ArrayRef<uint64_t> RawMask, const APInt &UndefElts,
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/// Decode a zero extension instruction as a shuffle mask.
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void DecodeZeroExtendMask(unsigned SrcScalarBits, unsigned DstScalarBits,
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unsigned NumDstElts,
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unsigned NumDstElts, bool IsAnyExtend,
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SmallVectorImpl<int> &ShuffleMask);
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/// Decode a move lower and zero upper instruction as a shuffle mask.
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@ -6849,17 +6849,20 @@ static bool getFauxShuffleMask(SDValue N, SmallVectorImpl<int> &Mask,
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return true;
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}
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case ISD::ZERO_EXTEND:
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case ISD::ZERO_EXTEND_VECTOR_INREG: {
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case ISD::ZERO_EXTEND_VECTOR_INREG:
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case ISD::ANY_EXTEND_VECTOR_INREG: {
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SDValue Src = N.getOperand(0);
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EVT SrcVT = Src.getValueType();
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// Zero-extended source must be a simple vector.
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// Extended source must be a simple vector.
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if (!SrcVT.isSimple() || (SrcVT.getSizeInBits() % 128) != 0 ||
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(SrcVT.getScalarSizeInBits() % 8) != 0)
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return false;
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unsigned NumSrcBitsPerElt = SrcVT.getScalarSizeInBits();
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DecodeZeroExtendMask(NumSrcBitsPerElt, NumBitsPerElt, NumElts, Mask);
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bool IsAnyExtend = (ISD::ANY_EXTEND_VECTOR_INREG == Opcode);
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DecodeZeroExtendMask(NumSrcBitsPerElt, NumBitsPerElt, NumElts, IsAnyExtend,
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Mask);
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if (NumSizeInBits != SrcVT.getSizeInBits()) {
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assert((NumSizeInBits % SrcVT.getSizeInBits()) == 0 &&
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@ -43259,7 +43262,7 @@ static SDValue combineExtInVec(SDNode *N, SelectionDAG &DAG,
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// Attempt to combine as a shuffle.
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// TODO: SSE41 support
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if (Subtarget.hasAVX() && N->getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG) {
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if (Subtarget.hasAVX()) {
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SDValue Op(N, 0);
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if (TLI.isTypeLegal(VT) && TLI.isTypeLegal(In.getValueType()))
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if (SDValue Res = combineX86ShufflesRecursively(Op, DAG, Subtarget))
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@ -479,11 +479,10 @@ define void @mul_2xi16(i8* nocapture readonly %a, i8* nocapture readonly %b, i64
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; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-AVX-NEXT: movl c, %esi
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; X86-AVX-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X86-AVX-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
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; X86-AVX-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; X86-AVX-NEXT: vpmovzxwd {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
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; X86-AVX-NEXT: vpmulld %xmm0, %xmm1, %xmm0
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; X86-AVX-NEXT: vpmovzxwq {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero
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; X86-AVX-NEXT: vpmovzxwq {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero
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; X86-AVX-NEXT: vpmuludq %xmm0, %xmm1, %xmm0
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; X86-AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; X86-AVX-NEXT: vmovq %xmm0, (%esi,%ecx,4)
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; X86-AVX-NEXT: popl %esi
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; X86-AVX-NEXT: retl
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@ -503,11 +502,10 @@ define void @mul_2xi16(i8* nocapture readonly %a, i8* nocapture readonly %b, i64
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; X64-AVX-LABEL: mul_2xi16:
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; X64-AVX: # %bb.0: # %entry
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; X64-AVX-NEXT: movq {{.*}}(%rip), %rax
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; X64-AVX-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X64-AVX-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
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; X64-AVX-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; X64-AVX-NEXT: vpmovzxwd {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
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; X64-AVX-NEXT: vpmulld %xmm0, %xmm1, %xmm0
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; X64-AVX-NEXT: vpmovzxwq {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero
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; X64-AVX-NEXT: vpmovzxwq {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero
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; X64-AVX-NEXT: vpmuludq %xmm0, %xmm1, %xmm0
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; X64-AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; X64-AVX-NEXT: vmovq %xmm0, (%rax,%rdx,4)
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; X64-AVX-NEXT: retq
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entry:
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@ -1167,10 +1165,9 @@ define void @mul_2xi16_sext_zext(i8* nocapture readonly %a, i8* nocapture readon
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; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-AVX-NEXT: movl c, %esi
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; X86-AVX-NEXT: vpmovsxwq (%edx,%ecx), %xmm0
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; X86-AVX-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; X86-AVX-NEXT: vpmovzxwd {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
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; X86-AVX-NEXT: vpmovzxwq {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero
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; X86-AVX-NEXT: vpmuludq %xmm0, %xmm1, %xmm0
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; X86-AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; X86-AVX-NEXT: vpmulld %xmm0, %xmm1, %xmm0
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; X86-AVX-NEXT: vmovq %xmm0, (%esi,%ecx,4)
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; X86-AVX-NEXT: popl %esi
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; X86-AVX-NEXT: retl
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@ -1195,10 +1192,9 @@ define void @mul_2xi16_sext_zext(i8* nocapture readonly %a, i8* nocapture readon
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; X64-AVX: # %bb.0: # %entry
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; X64-AVX-NEXT: movq {{.*}}(%rip), %rax
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; X64-AVX-NEXT: vpmovsxwq (%rdi,%rdx), %xmm0
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; X64-AVX-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; X64-AVX-NEXT: vpmovzxwd {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
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; X64-AVX-NEXT: vpmovzxwq {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero
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; X64-AVX-NEXT: vpmuludq %xmm0, %xmm1, %xmm0
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; X64-AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; X64-AVX-NEXT: vpmulld %xmm0, %xmm1, %xmm0
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; X64-AVX-NEXT: vmovq %xmm0, (%rax,%rdx,4)
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; X64-AVX-NEXT: retq
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entry:
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@ -1813,9 +1809,9 @@ define void @mul_2xi16_varconst1(i8* nocapture readonly %a, i64 %index) {
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; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-AVX-NEXT: movl c, %edx
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; X86-AVX-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X86-AVX-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
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; X86-AVX-NEXT: vpmulld {{\.LCPI.*}}, %xmm0, %xmm0
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; X86-AVX-NEXT: vpmovzxwq {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero
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; X86-AVX-NEXT: vpmuludq {{\.LCPI.*}}, %xmm0, %xmm0
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; X86-AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; X86-AVX-NEXT: vmovq %xmm0, (%edx,%eax,4)
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; X86-AVX-NEXT: retl
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;
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@ -1834,9 +1830,9 @@ define void @mul_2xi16_varconst1(i8* nocapture readonly %a, i64 %index) {
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; X64-AVX-LABEL: mul_2xi16_varconst1:
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; X64-AVX: # %bb.0: # %entry
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; X64-AVX-NEXT: movq {{.*}}(%rip), %rax
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; X64-AVX-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X64-AVX-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
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; X64-AVX-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
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; X64-AVX-NEXT: vpmovzxwq {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero
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; X64-AVX-NEXT: vpmuludq {{.*}}(%rip), %xmm0, %xmm0
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; X64-AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; X64-AVX-NEXT: vmovq %xmm0, (%rax,%rsi,4)
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; X64-AVX-NEXT: retq
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entry:
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@ -1941,9 +1937,9 @@ define void @mul_2xi16_varconst3(i8* nocapture readonly %a, i64 %index) {
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; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-AVX-NEXT: movl c, %edx
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; X86-AVX-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X86-AVX-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
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; X86-AVX-NEXT: vpmulld {{\.LCPI.*}}, %xmm0, %xmm0
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; X86-AVX-NEXT: vpmovzxwq {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero
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; X86-AVX-NEXT: vpmuludq {{\.LCPI.*}}, %xmm0, %xmm0
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; X86-AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; X86-AVX-NEXT: vmovq %xmm0, (%edx,%eax,4)
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; X86-AVX-NEXT: retl
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;
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@ -1962,9 +1958,9 @@ define void @mul_2xi16_varconst3(i8* nocapture readonly %a, i64 %index) {
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; X64-AVX-LABEL: mul_2xi16_varconst3:
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; X64-AVX: # %bb.0: # %entry
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; X64-AVX-NEXT: movq {{.*}}(%rip), %rax
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; X64-AVX-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X64-AVX-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
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; X64-AVX-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
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; X64-AVX-NEXT: vpmovzxwq {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero
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; X64-AVX-NEXT: vpmuludq {{.*}}(%rip), %xmm0, %xmm0
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; X64-AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; X64-AVX-NEXT: vmovq %xmm0, (%rax,%rsi,4)
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; X64-AVX-NEXT: retq
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entry:
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