Add FP conditional move instructions, which annoyingly have special properties
that require the asmwriter to be extended (printing implicit uses before the explicit operands) llvm-svn: 12574
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@ -34,9 +34,11 @@ def X86InstrInfo : InstrInfo {
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// Define how we want to layout our TargetSpecific information field... This
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// Define how we want to layout our TargetSpecific information field... This
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// should be kept up-to-date with the fields in the X86InstrInfo.h file.
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// should be kept up-to-date with the fields in the X86InstrInfo.h file.
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let TSFlagsFields = ["FormBits" , "hasOpSizePrefix" , "Prefix", "MemTypeBits",
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let TSFlagsFields = ["FormBits" , "hasOpSizePrefix" , "Prefix", "MemTypeBits",
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"ImmTypeBits", "FPFormBits", "printImplicitUses", "Opcode"];
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"ImmTypeBits", "FPFormBits", "printImplicitUsesAfter",
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"printImplicitUsesBefore", "Opcode"];
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let TSFlagsShifts = [0, 5, 6, 10, 13,
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let TSFlagsShifts = [0, 5, 6, 10, 13,
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15, 18, 19];
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15, 18, 19,
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20];
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}
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}
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def X86 : Target {
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def X86 : Target {
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@ -155,13 +155,21 @@ namespace X86II {
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// argument. For example: fadd, fsub, fmul, etc...
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// argument. For example: fadd, fsub, fmul, etc...
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TwoArgFP = 4 << FPTypeShift,
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TwoArgFP = 4 << FPTypeShift,
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// CondMovFP - "2 operand" floating point conditional move instructions.
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CondMovFP = 5 << FPTypeShift,
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// SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
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// SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
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SpecialFP = 5 << FPTypeShift,
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SpecialFP = 6 << FPTypeShift,
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// PrintImplUses - Print out implicit uses in the assembly output.
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// PrintImplUsesAfter - Print out implicit uses in the assembly output after
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PrintImplUses = 1 << 18,
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// the normal operands.
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PrintImplUsesAfter = 1 << 18,
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OpcodeShift = 19,
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// PrintImplUsesBefore - Print out implicit uses in the assembly output before
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// the normal operands.
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PrintImplUsesBefore = 1 << 19,
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OpcodeShift = 20,
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OpcodeMask = 0xFF << OpcodeShift,
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OpcodeMask = 0xFF << OpcodeShift,
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// Bits 25 -> 31 are unused
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// Bits 25 -> 31 are unused
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};
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};
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@ -66,7 +66,8 @@ def ZeroArgFP : FPFormat<1>;
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def OneArgFP : FPFormat<2>;
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def OneArgFP : FPFormat<2>;
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def OneArgFPRW : FPFormat<3>;
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def OneArgFPRW : FPFormat<3>;
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def TwoArgFP : FPFormat<4>;
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def TwoArgFP : FPFormat<4>;
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def SpecialFP : FPFormat<5>;
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def CondMovFP : FPFormat<5>;
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def SpecialFP : FPFormat<6>;
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class X86Inst<string nam, bits<8> opcod, Format f, MemType m, ImmType i> : Instruction {
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class X86Inst<string nam, bits<8> opcod, Format f, MemType m, ImmType i> : Instruction {
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@ -83,7 +84,8 @@ class X86Inst<string nam, bits<8> opcod, Format f, MemType m, ImmType i> : Instr
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// Attributes specific to X86 instructions...
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// Attributes specific to X86 instructions...
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bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
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bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
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bit printImplicitUses = 0; // Should we print implicit uses of this inst?
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bit printImplicitUsesBefore = 0; // Should we print implicit uses before this inst?
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bit printImplicitUsesAfter = 0; // Should we print implicit uses after this inst?
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bits<4> Prefix = 0; // Which prefix byte does this inst have?
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bits<4> Prefix = 0; // Which prefix byte does this inst have?
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FPFormat FPForm; // What flavor of FP instruction is this?
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FPFormat FPForm; // What flavor of FP instruction is this?
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@ -138,7 +140,7 @@ class Im16i8<string n, bits<8> o, Format f> : X86Inst<n, o, f, Mem16, Imm8>;
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class Im32i8<string n, bits<8> o, Format f> : X86Inst<n, o, f, Mem32, Imm8>;
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class Im32i8<string n, bits<8> o, Format f> : X86Inst<n, o, f, Mem32, Imm8>;
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// Helper for shift instructions
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// Helper for shift instructions
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class UsesCL { list<Register> Uses = [CL]; bit printImplicitUses = 1; }
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class UsesCL { list<Register> Uses = [CL]; bit printImplicitUsesAfter = 1; }
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction list...
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// Instruction list...
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@ -694,6 +696,17 @@ def FpUCOM : FPI<"FUCOM", 0, Pseudo, TwoArgFP>; // FPSW = fucom f1, f2
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def FpGETRESULT : FPI<"FGETRESULT",0, Pseudo, SpecialFP>; // FPR = ST(0)
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def FpGETRESULT : FPI<"FGETRESULT",0, Pseudo, SpecialFP>; // FPR = ST(0)
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def FpSETRESULT : FPI<"FSETRESULT",0, Pseudo, SpecialFP>; // ST(0) = FPR
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def FpSETRESULT : FPI<"FSETRESULT",0, Pseudo, SpecialFP>; // ST(0) = FPR
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// Floating point cmovs...
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let isTwoAddress = 1, Uses = [ST0], Defs = [ST0], printImplicitUsesBefore = 1 in {
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def FCMOVB : FPI <"fcmovb" , 0xC0, AddRegFrm, CondMovFP>, DA; // fcmovb ST(i) -> ST(0)
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def FCMOVBE : FPI <"fcmovbe", 0xD0, AddRegFrm, CondMovFP>, DA; // fcmovbe ST(i) -> ST(0)
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def FCMOVE : FPI <"fcmove" , 0xC8, AddRegFrm, CondMovFP>, DA; // fcmove ST(i) -> ST(0)
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def FCMOVAE : FPI <"fcmovae", 0xC0, AddRegFrm, CondMovFP>, DB; // fcmovae ST(i) -> ST(0)
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def FCMOVA : FPI <"fcmova" , 0xD0, AddRegFrm, CondMovFP>, DB; // fcmova ST(i) -> ST(0)
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def FCMOVNE : FPI <"fcmovne", 0xC8, AddRegFrm, CondMovFP>, DB; // fcmovne ST(i) -> ST(0)
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}
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// Floating point loads & stores...
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// Floating point loads & stores...
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def FLDrr : FPI <"fld" , 0xC0, AddRegFrm, NotFP>, D9; // push(ST(i))
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def FLDrr : FPI <"fld" , 0xC0, AddRegFrm, NotFP>, D9; // push(ST(i))
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def FLD32m : FPI32m <"fld" , 0xD9, MRM0m , ZeroArgFP>; // load float
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def FLD32m : FPI32m <"fld" , 0xD9, MRM0m , ZeroArgFP>; // load float
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@ -735,7 +748,7 @@ class FPST0rInst<string n, bits<8> o> : I<n, o, AddRegFrm>, D8 {
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list<Register> Defs = [ST0];
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list<Register> Defs = [ST0];
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}
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}
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class FPrST0Inst<string n, bits<8> o> : I<n, o, AddRegFrm>, DC {
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class FPrST0Inst<string n, bits<8> o> : I<n, o, AddRegFrm>, DC {
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bit printImplicitUses = 1;
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bit printImplicitUsesAfter = 1;
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list<Register> Uses = [ST0];
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list<Register> Uses = [ST0];
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}
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}
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class FPrST0PInst<string n, bits<8> o> : I<n, o, AddRegFrm>, DE {
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class FPrST0PInst<string n, bits<8> o> : I<n, o, AddRegFrm>, DE {
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