Plugin new subtarget backend into the build.
llvm-svn: 23870
This commit is contained in:
Jim Laskey
parent
cfda85ad91
commit
9ed9032e22
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@ -1162,6 +1162,10 @@ $(ObjDir)/%GenDAGISel.inc.tmp : %.td $(ObjDir)/.dir
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$(Echo) "Building $(<F) instruction selector implementation with tblgen"
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$(Verb) $(TableGen) -gen-dag-isel -o $@ $<
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$(TARGET:%=$(ObjDir)/%GenSubtarget.inc.tmp): \
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$(ObjDir)/%GenSubtarget.inc.tmp : %.td $(ObjDir)/.dir
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$(Echo) "Building $(<F) subtarget information with tblgen"
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$(Verb) $(TableGen) -gen-subtarget -o $@ $<
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clean-local::
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-$(Verb) $(RM) -f $(INCFiles)
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@ -14,6 +14,6 @@ TARGET = PPC
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BUILT_SOURCES = PPCGenInstrNames.inc PPCGenRegisterNames.inc \
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PPCGenAsmWriter.inc PPCGenCodeEmitter.inc \
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PPCGenRegisterInfo.h.inc PPCGenRegisterInfo.inc \
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PPCGenInstrInfo.inc PPCGenDAGISel.inc
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PPCGenInstrInfo.inc PPCGenDAGISel.inc PPCGenSubtarget.inc
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include $(LEVEL)/Makefile.common
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@ -26,37 +26,44 @@ include "PPCInstrInfo.td"
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//===----------------------------------------------------------------------===//
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// PowerPC Subtarget features.
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// PowerPC Subtarget features (sorted by name).
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//
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def F64Bit : SubtargetFeature<"64bit",
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"Should 64 bit instructions be used">;
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def F64BitRegs : SubtargetFeature<"64bitregs",
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"Should 64 bit registers be used">;
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def FAltivec : SubtargetFeature<"altivec",
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"Should Altivec instructions be used">;
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def FGPUL : SubtargetFeature<"gpul",
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"Should GPUL instructions be used">;
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def FFSQRT : SubtargetFeature<"fsqrt",
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"Should the fsqrt instruction be used">;
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def Feature64Bit : SubtargetFeature<"64bit",
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"Should 64 bit instructions be used">;
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def Feature64BitRegs : SubtargetFeature<"64bitregs",
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"Should 64 bit registers be used">;
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def FeatureAltivec : SubtargetFeature<"altivec",
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"Should Altivec instructions be used">;
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def FeatureFSqrt : SubtargetFeature<"fsqrt",
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"Should the fsqrt instruction be used">;
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def FeatureGPUL : SubtargetFeature<"gpul",
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"Should GPUL instructions be used">;
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//===----------------------------------------------------------------------===//
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// PowerPC chips sets supported
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// PowerPC chips sets supported (sorted by name)
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//
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def : Processor<"601", G3Itineraries, []>;
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def : Processor<"602", G3Itineraries, []>;
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def : Processor<"603", G3Itineraries, []>;
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def : Processor<"603e", G3Itineraries, []>;
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def : Processor<"603ev", G3Itineraries, []>;
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def : Processor<"604", G3Itineraries, []>;
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def : Processor<"604e", G3Itineraries, []>;
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def : Processor<"620", G3Itineraries, []>;
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def : Processor<"7400", G4Itineraries, [FeatureAltivec]>;
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def : Processor<"7450", G4PlusItineraries, [FeatureAltivec]>;
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def : Processor<"750", G3Itineraries, []>;
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def : Processor<"7400", G4Itineraries, [FAltivec]>;
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def : Processor<"g4", G4Itineraries, [FAltivec]>;
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def : Processor<"7450", G4PlusItineraries, [FAltivec]>;
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def : Processor<"g4+", G4PlusItineraries, [FAltivec]>;
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def : Processor<"970", G5Itineraries,
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[FAltivec, FGPUL, FFSQRT, F64Bit, F64BitRegs]>;
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[FeatureAltivec, FeatureGPUL, FeatureFSqrt,
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Feature64Bit, Feature64BitRegs]>;
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def : Processor<"g4", G4Itineraries, [FeatureAltivec]>;
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def : Processor<"g4+", G4PlusItineraries, [FeatureAltivec]>;
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def : Processor<"g5", G5Itineraries,
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[FAltivec, FGPUL, FFSQRT, F64Bit, F64BitRegs]>;
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[FeatureAltivec, FeatureGPUL, FeatureFSqrt,
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Feature64Bit, Feature64BitRegs]>;
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def : Processor<"generic", G3Itineraries, []>;
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def PPC : Target {
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@ -16,6 +16,7 @@
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#include "llvm/Module.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Target/SubtargetFeature.h"
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#include "PPCGenSubtarget.inc"
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using namespace llvm;
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PPCTargetEnum llvm::PPCTarget = TargetDefault;
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@ -29,59 +30,14 @@ namespace llvm {
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" Enable Darwin codegen"),
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clEnumValEnd),
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cl::location(PPCTarget), cl::init(TargetDefault));
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}
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enum PowerPCFeature {
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PowerPCFeature64Bit = 1 << 0,
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PowerPCFeatureAltivec = 1 << 1,
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PowerPCFeatureFSqrt = 1 << 2,
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PowerPCFeatureGPUL = 1 << 3,
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PowerPCFeature64BRegs = 1 << 4
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};
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/// Sorted (by key) array of values for CPU subtype.
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static const SubtargetFeatureKV PowerPCSubTypeKV[] = {
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{ "601" , "Select the PowerPC 601 processor", 0 },
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{ "602" , "Select the PowerPC 602 processor", 0 },
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{ "603" , "Select the PowerPC 603 processor", 0 },
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{ "603e" , "Select the PowerPC 603e processor", 0 },
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{ "603ev" , "Select the PowerPC 603ev processor", 0 },
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{ "604" , "Select the PowerPC 604 processor", 0 },
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{ "604e" , "Select the PowerPC 604e processor", 0 },
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{ "620" , "Select the PowerPC 620 processor", 0 },
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{ "7400" , "Select the PowerPC 7400 (G4) processor",
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PowerPCFeatureAltivec },
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{ "7450" , "Select the PowerPC 7450 (G4+) processor",
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PowerPCFeatureAltivec },
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{ "750" , "Select the PowerPC 750 (G3) processor", 0 },
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{ "970" , "Select the PowerPC 970 (G5 - GPUL) processor",
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PowerPCFeature64Bit | PowerPCFeatureAltivec |
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PowerPCFeatureFSqrt | PowerPCFeatureGPUL },
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{ "g3" , "Select the PowerPC G3 (750) processor", 0 },
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{ "g4" , "Select the PowerPC G4 (7400) processor",
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PowerPCFeatureAltivec },
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{ "g4+" , "Select the PowerPC G4+ (7450) processor",
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PowerPCFeatureAltivec },
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{ "g5" , "Select the PowerPC g5 (970 - GPUL) processor",
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PowerPCFeature64Bit | PowerPCFeatureAltivec |
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PowerPCFeatureFSqrt | PowerPCFeatureGPUL },
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{ "generic", "Select instructions for a generic PowerPC processor", 0 }
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};
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/// Length of PowerPCSubTypeKV.
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static const unsigned PowerPCSubTypeKVSize = sizeof(PowerPCSubTypeKV)
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/ sizeof(SubtargetFeatureKV);
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/// Sorted (by key) array of values for CPU features.
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static SubtargetFeatureKV PowerPCFeatureKV[] = {
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{ "64bit" , "Should 64 bit instructions be used" , PowerPCFeature64Bit },
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{ "64bitregs", "Should 64 bit registers be used" , PowerPCFeature64BRegs },
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{ "altivec", "Should Altivec instructions be used" , PowerPCFeatureAltivec },
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{ "fsqrt" , "Should the fsqrt instruction be used", PowerPCFeatureFSqrt },
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{ "gpul" , "Should GPUL instructions be used" , PowerPCFeatureGPUL }
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};
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/// Length of PowerPCFeatureKV.
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static const unsigned PowerPCFeatureKVSize = sizeof(PowerPCFeatureKV)
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}
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/// Length of FeatureKV.
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static const unsigned FeatureKVSize = sizeof(FeatureKV)
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/ sizeof(SubtargetFeatureKV);
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/// Length of SubTypeKV.
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static const unsigned SubTypeKVSize = sizeof(SubTypeKV)
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/ sizeof(SubtargetFeatureKV);
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#if defined(__APPLE__)
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@ -131,12 +87,11 @@ PPCSubtarget::PPCSubtarget(const Module &M, const std::string &FS)
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#endif
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uint32_t Bits =
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SubtargetFeatures::Parse(FS, CPU,
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PowerPCSubTypeKV, PowerPCSubTypeKVSize,
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PowerPCFeatureKV, PowerPCFeatureKVSize);
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IsGigaProcessor = (Bits & PowerPCFeatureGPUL ) != 0;
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Is64Bit = (Bits & PowerPCFeature64Bit) != 0;
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HasFSQRT = (Bits & PowerPCFeatureFSqrt) != 0;
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Has64BitRegs = (Bits & PowerPCFeature64BRegs) != 0;
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SubTypeKV, SubTypeKVSize, FeatureKV, FeatureKVSize);
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IsGigaProcessor = (Bits & FeatureGPUL ) != 0;
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Is64Bit = (Bits & Feature64Bit) != 0;
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HasFSQRT = (Bits & FeatureFSqrt) != 0;
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Has64BitRegs = (Bits & Feature64BitRegs) != 0;
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// Set the boolean corresponding to the current target triple, or the default
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// if one cannot be determined, to true.
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@ -280,7 +280,7 @@ class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
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ProcessorItineraries ProcItin = pi;
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// Features - list of
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list<SubtargetFeature> Features;
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list<SubtargetFeature> Features = f;
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}
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//===----------------------------------------------------------------------===//
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@ -28,8 +28,8 @@ class FuncUnit;
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// need to complete the stage. Units represent the choice of functional units
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// that can be used to complete the stage. Eg. IntUnit1, IntUnit2.
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//
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class InstrStage<int latency, list<FuncUnit> units> {
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int Latency = latency; // length of stage in machine cycles
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class InstrStage<int cycles, list<FuncUnit> units> {
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int Cycles = cycles; // length of stage in machine cycles
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list<FuncUnit> Units = units; // choice of functional units
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}
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@ -25,6 +25,7 @@
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#include "AsmWriterEmitter.h"
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#include "InstrSelectorEmitter.h"
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#include "DAGISelEmitter.h"
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#include "SubtargetEmitter.h"
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#include <algorithm>
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#include <cstdio>
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#include <fstream>
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@ -36,6 +37,7 @@ enum ActionType {
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GenRegisterEnums, GenRegister, GenRegisterHeader,
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GenInstrEnums, GenInstrs, GenAsmWriter, GenInstrSelector,
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GenDAGISel,
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GenSubtarget,
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PrintEnums,
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Parse
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};
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@ -63,6 +65,8 @@ namespace {
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"Generate an instruction selector"),
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clEnumValN(GenDAGISel, "gen-dag-isel",
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"Generate a DAG instruction selector"),
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clEnumValN(GenSubtarget, "gen-subtarget",
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"Generate subtarget enumerations"),
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clEnumValN(PrintEnums, "print-enums",
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"Print enum values for a class"),
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clEnumValN(Parse, "parse",
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@ -472,6 +476,9 @@ int main(int argc, char **argv) {
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case GenDAGISel:
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DAGISelEmitter(Records).run(*Out);
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break;
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case GenSubtarget:
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SubtargetEmitter(Records).run(*Out);
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break;
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case PrintEnums:
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{
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std::vector<Record*> Recs = Records.getAllDerivedDefinitions(Class);
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