From 9df2fa261b66933cf0f3f8882e5ea0eee9fbc075 Mon Sep 17 00:00:00 2001 From: Quentin Colombet Date: Fri, 1 May 2015 20:57:11 +0000 Subject: [PATCH] [AArch64][FastISel] Fix the setting of kill flags for MUL -> UMULH sequences. rdar://problem/20748715 llvm-svn: 236346 --- llvm/lib/Target/AArch64/AArch64FastISel.cpp | 10 ++++++++-- llvm/test/CodeGen/AArch64/arm64-fast-isel.ll | 13 +++++++++++++ 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64FastISel.cpp b/llvm/lib/Target/AArch64/AArch64FastISel.cpp index 837a31f303fb..c70b17c8a32c 100644 --- a/llvm/lib/Target/AArch64/AArch64FastISel.cpp +++ b/llvm/lib/Target/AArch64/AArch64FastISel.cpp @@ -3598,7 +3598,10 @@ bool AArch64FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) { AArch64_AM::ASR, 31, /*WantResult=*/false); } else { assert(VT == MVT::i64 && "Unexpected value type."); - MulReg = emitMul_rr(VT, LHSReg, LHSIsKill, RHSReg, RHSIsKill); + // LHSReg and RHSReg cannot be killed by this Mul, since they are + // reused in the next instruction. + MulReg = emitMul_rr(VT, LHSReg, /*IsKill=*/false, RHSReg, + /*IsKill=*/false); unsigned SMULHReg = fastEmit_rr(VT, VT, ISD::MULHS, LHSReg, LHSIsKill, RHSReg, RHSIsKill); emitSubs_rs(VT, SMULHReg, /*IsKill=*/true, MulReg, /*IsKill=*/false, @@ -3627,7 +3630,10 @@ bool AArch64FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) { AArch64::sub_32); } else { assert(VT == MVT::i64 && "Unexpected value type."); - MulReg = emitMul_rr(VT, LHSReg, LHSIsKill, RHSReg, RHSIsKill); + // LHSReg and RHSReg cannot be killed by this Mul, since they are + // reused in the next instruction. + MulReg = emitMul_rr(VT, LHSReg, /*IsKill=*/false, RHSReg, + /*IsKill=*/false); unsigned UMULHReg = fastEmit_rr(VT, VT, ISD::MULHU, LHSReg, LHSIsKill, RHSReg, RHSIsKill); emitSubs_rr(VT, AArch64::XZR, /*IsKill=*/true, UMULHReg, diff --git a/llvm/test/CodeGen/AArch64/arm64-fast-isel.ll b/llvm/test/CodeGen/AArch64/arm64-fast-isel.ll index a1d51a54cd46..6663c9ac577e 100644 --- a/llvm/test/CodeGen/AArch64/arm64-fast-isel.ll +++ b/llvm/test/CodeGen/AArch64/arm64-fast-isel.ll @@ -101,3 +101,16 @@ entry: store i32 %cond91, i32* %addr, align 4 ret void } + +define i64 @mul_umul(i64 %arg) { +; CHECK-LABEL: mul_umul: +; CHECK: mul x{{[0-9]+}}, [[ARG1:x[0-9]+]], [[ARG2:x[0-9]+]] +; CHECK-NEXT: umulh x{{[0-9]+}}, [[ARG1]], [[ARG2]] +entry: + %sub.ptr.div = sdiv exact i64 %arg, 8 + %tmp = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %sub.ptr.div, i64 8) + %tmp1 = extractvalue { i64, i1 } %tmp, 0 + ret i64 %tmp1 +} + +declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64)