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[AArch64] Add isel pattern for v8i8->v2f32 NVCASTs. 

rdar://39454635

llvm-svn: 330276
This commit is contained in:
Amara Emerson 2018-04-18 17:10:19 +00:00
parent 1a928f3fc7
commit 9de072f8ae
2 changed files with 17 additions and 0 deletions
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1
llvm/lib/Target/AArch64/AArch64InstrInfo.td
View File

@ -5651,6 +5651,7 @@ def : Pat<(v8i8 (AArch64NvCast (v8i8 FPR64:$src))), (v8i8 FPR64:$src)>;
def : Pat<(v4i16 (AArch64NvCast (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
def : Pat<(v4f16 (AArch64NvCast (v8i8 FPR64:$src))), (v4f16 FPR64:$src)>;
def : Pat<(v2i32 (AArch64NvCast (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
def : Pat<(v2f32 (AArch64NvCast (v8i8 FPR64:$src))), (v2f32 FPR64:$src)>;
def : Pat<(v1i64 (AArch64NvCast (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
def : Pat<(v8i8 (AArch64NvCast (f64 FPR64:$src))), (v8i8 FPR64:$src)>;

16
llvm/test/CodeGen/AArch64/arm64-nvcast.ll
View File

@ -31,3 +31,19 @@ entry:
store float %v2, float* %p1, align 4
ret void
}
%"st1" = type { %"subst1", %"subst1", %"subst1" }
%"subst1" = type { %float4 }
%float4 = type { float, float, float, float }
@_gv = external unnamed_addr global %"st1", align 8
define internal void @nvcast_f32_v8i8() {
; CHECK-LABEL: _nvcast_f32_v8i8
; CHECK: movi.8b v[[REG:[0-9]+]], #254
; CHECK: str d[[REG]]
entry:
store <2 x float> <float 0xC7DFDFDFC0000000, float 0xC7DFDFDFC0000000>, <2 x float>* bitcast (%"st1"* @_gv to <2 x float>*), align 8
ret void
}