replica
/
hanchenye-llvm-project
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Add suport for unpredicatble cases of the cmp, tst, teq and cmnz ARM instructions in the disassembler. 

llvm-svn: 154999
This commit is contained in:
Silviu Baranga 2012-04-18 12:48:43 +00:00
parent 296a7bb49f
commit 9da1918c84
2 changed files with 40 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
llvm/lib/Target/ARM/ARMInstrInfo.td
View File

@ -1187,6 +1187,8 @@ multiclass AI1_cmp_irs<bits<4> opcod, string opc,
let Inst{19-16} = Rn;
let Inst{15-12} = 0b0000;
let Inst{11-0} = imm;
let Unpredictable{15-12} = 0b1111;
}
def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
opc, "\t$Rn, $Rm",
@ -1200,6 +1202,8 @@ multiclass AI1_cmp_irs<bits<4> opcod, string opc,
let Inst{15-12} = 0b0000;
let Inst{11-4} = 0b00000000;
let Inst{3-0} = Rm;
let Unpredictable{15-12} = 0b1111;
}
def rsi : AI1<opcod, (outs),
(ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
@ -1214,11 +1218,13 @@ multiclass AI1_cmp_irs<bits<4> opcod, string opc,
let Inst{11-5} = shift{11-5};
let Inst{4} = 0;
let Inst{3-0} = shift{3-0};
let Unpredictable{15-12} = 0b1111;
}
def rsr : AI1<opcod, (outs),
(ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
(ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
opc, "\t$Rn, $shift",
[(opnode GPR:$Rn, so_reg_reg:$shift)]> {
[(opnode GPRnopc:$Rn, so_reg_reg:$shift)]> {
bits<4> Rn;
bits<12> shift;
let Inst{25} = 0;
@ -1230,6 +1236,8 @@ multiclass AI1_cmp_irs<bits<4> opcod, string opc,
let Inst{6-5} = shift{6-5};
let Inst{4} = 1;
let Inst{3-0} = shift{3-0};
let Unpredictable{15-12} = 0b1111;
}
}

30
llvm/test/MC/Disassembler/ARM/unpredictable-AI1cmp-arm.txt Normal file
View File

@ -0,0 +1,30 @@
# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s
# CHECK: potentially undefined
# CHECK: 0x01 0x10 0x50 0x03
0x01 0x10 0x50 0x03
# CHECK: potentially undefined
# CHECK: 0x82 0x10 0x50 0x01
0x82 0x10 0x50 0x01
# CHECK: potentially undefined
# CHECK: 0x02 0x10 0x50 0x01
0x02 0x10 0x50 0x01
# CHECK: potentially undefined
# CHECK: 0x1f 0x01 0x52 0x01
0x1f 0x01 0x52 0x01
# CHECK: potentially undefined
# CHECK: 0x10 0x11 0x52 0x01
0x10 0x11 0x52 0x01
# CHECK: potentially undefined
# CHECK: 0x10 0x0f 0x51 0x01
0x10 0x0f 0x51 0x01
# CHECK: potentially undefined
# CHECK: 0x10 0x01 0x5f 0x01
0x10 0x01 0x5f 0x01