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McARM: Add more hard coded logic to SplitMnemonicAndCC to also split out the 

carry setting flag from the mnemonic.

Note that this currently involves me disabling a number of working cases in
arm_instructions.s, this is a hopefully short term evil which will be rapidly
fixed (and greatly surpassed), assuming my current approach flies.

llvm-svn: 123238
This commit is contained in:
Daniel Dunbar 2011-01-11 15:59:50 +00:00
parent 7a7dc6f504
commit 9d944b3fcc
2 changed files with 50 additions and 20 deletions
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43
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -866,9 +866,19 @@ bool ARMAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands){
}
}
/// \brief Given a mnemonic, split out possible predication code and carry
/// setting letters to form a canonical mnemonic and flags.
//
// FIXME: Would be nice to autogen this.
static unsigned SplitMnemonicAndCC(StringRef &Mnemonic) {
static StringRef SplitMnemonicAndCC(StringRef Mnemonic,
unsigned &PredicationCode,
bool &CarrySetting) {
PredicationCode = ARMCC::AL;
CarrySetting = false;
// Ignore some mnemonics we know aren't predicated forms.
//
// FIXME: Would be nice to autogen this.
if (Mnemonic == "teq" || Mnemonic == "vceq" ||
Mnemonic == "movs" ||
Mnemonic == "svc" ||
@ -881,13 +891,9 @@ static unsigned SplitMnemonicAndCC(StringRef &Mnemonic) {
(Mnemonic == "smlal" || Mnemonic == "umaal" || Mnemonic == "umlal" ||
Mnemonic == "vabal" || Mnemonic == "vmlal" || Mnemonic == "vpadal" ||
Mnemonic == "vqdmlal"))
return ARMCC::AL;
return Mnemonic;
// Otherwise, determine the predicate.
//
// FIXME: We need a way to check whether a prefix supports predication,
// otherwise we will end up with an ambiguity for instructions that happen to
// end with a predicate name.
// First, split out any predication code.
unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
.Case("eq", ARMCC::EQ)
.Case("ne", ARMCC::NE)
@ -907,10 +913,23 @@ static unsigned SplitMnemonicAndCC(StringRef &Mnemonic) {
.Default(~0U);
if (CC != ~0U) {
Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
return CC;
PredicationCode = CC;
}
return ARMCC::AL;
// Next, determine if we have a carry setting bit. We explicitly ignore all
// the instructions we know end in 's'.
if (Mnemonic.endswith("s") &&
!(Mnemonic == "asrs" || Mnemonic == "cps" || Mnemonic == "mls" ||
Mnemonic == "movs" || Mnemonic == "mrs" || Mnemonic == "smmls" ||
Mnemonic == "vabs" || Mnemonic == "vcls" || Mnemonic == "vmls" ||
Mnemonic == "vmrs" || Mnemonic == "vnmls" || Mnemonic == "vqabs" ||
Mnemonic == "vrecps" || Mnemonic == "vrsqrts")) {
Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
CarrySetting = true;
}
return Mnemonic;
}
}
/// Parse an arm instruction mnemonic followed by its operands.
@ -920,8 +939,10 @@ bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
size_t Start = 0, Next = Name.find('.');
StringRef Head = Name.slice(Start, Next);
// Determine the predicate, if any.
unsigned CC = SplitMnemonicAndCC(Head);
// Split out the predication code and carry setting flag from the mnemonic.
unsigned PredicationCode;
bool CarrySetting;
Head = SplitMnemonicAndCC(Head, PredicationCode, CarrySetting);
Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));

27
llvm/test/MC/ARM/arm_instructions.s
View File

@ -59,25 +59,29 @@
@ CHECK: and r1, r2, r3 @ encoding: [0x03,0x10,0x02,0xe0]
and r1,r2,r3
@ CHECK: ands r1, r2, r3 @ encoding: [0x03,0x10,0x12,0xe0]
@ FIXME: This is wrong, we are dropping the 's' for now.
@ CHECK-FIXME: ands r1, r2, r3 @ encoding: [0x03,0x10,0x12,0xe0]
ands r1,r2,r3
@ CHECK: eor r1, r2, r3 @ encoding: [0x03,0x10,0x22,0xe0]
eor r1,r2,r3
@ CHECK: eors r1, r2, r3 @ encoding: [0x03,0x10,0x32,0xe0]
@ FIXME: This is wrong, we are dropping the 's' for now.
@ CHECK-FIXME: eors r1, r2, r3 @ encoding: [0x03,0x10,0x32,0xe0]
eors r1,r2,r3
@ CHECK: sub r1, r2, r3 @ encoding: [0x03,0x10,0x42,0xe0]
sub r1,r2,r3
@ CHECK: subs r1, r2, r3 @ encoding: [0x03,0x10,0x52,0xe0]
@ FIXME: This is wrong, we are dropping the 's' for now.
@ CHECK-FIXME: subs r1, r2, r3 @ encoding: [0x03,0x10,0x52,0xe0]
subs r1,r2,r3
@ CHECK: add r1, r2, r3 @ encoding: [0x03,0x10,0x82,0xe0]
add r1,r2,r3
@ CHECK: adds r1, r2, r3 @ encoding: [0x03,0x10,0x92,0xe0]
@ FIXME: This is wrong, we are dropping the 's' for now.
@ CHECK-FIXME: adds r1, r2, r3 @ encoding: [0x03,0x10,0x92,0xe0]
adds r1,r2,r3
@ CHECK: adc r1, r2, r3 @ encoding: [0x03,0x10,0xa2,0xe0]
@ -89,13 +93,15 @@
@ CHECK: orr r1, r2, r3 @ encoding: [0x03,0x10,0x82,0xe1]
orr r1,r2,r3
@ CHECK: orrs r1, r2, r3 @ encoding: [0x03,0x10,0x92,0xe1]
@ FIXME: This is wrong, we are dropping the 's' for now.
@ CHECK-FIXME: orrs r1, r2, r3 @ encoding: [0x03,0x10,0x92,0xe1]
orrs r1,r2,r3
@ CHECK: bic r1, r2, r3 @ encoding: [0x03,0x10,0xc2,0xe1]
bic r1,r2,r3
@ CHECK: bics r1, r2, r3 @ encoding: [0x03,0x10,0xd2,0xe1]
@ FIXME: This is wrong, we are dropping the 's' for now.
@ CHECK-FIXME: bics r1, r2, r3 @ encoding: [0x03,0x10,0xd2,0xe1]
bics r1,r2,r3
@ CHECK: mov r1, r2 @ encoding: [0x02,0x10,0xa0,0xe1]
@ -104,7 +110,8 @@
@ CHECK: mvn r1, r2 @ encoding: [0x02,0x10,0xe0,0xe1]
mvn r1,r2
@ CHECK: mvns r1, r2 @ encoding: [0x02,0x10,0xf0,0xe1]
@ FIXME: This is wrong, we are dropping the 's' for now.
@ CHECK-FIXME: mvns r1, r2 @ encoding: [0x02,0x10,0xf0,0xe1]
mvns r1,r2
@ CHECK: rsb r1, r2, r3 @ encoding: [0x03,0x10,0x62,0xe0]
@ -113,5 +120,7 @@
@ CHECK: rsc r1, r2, r3 @ encoding: [0x03,0x10,0xe2,0xe0]
rsc r1,r2,r3
@ CHECK: mlas r1, r2, r3, r4 @ encoding: [0x92,0x43,0x31,0xe0]
mlas r1,r2,r3,r4
@ FIXME: This is broken, CCOut operands don't work correctly when their presence
@ may depend on flags.
@ CHECK-FIXME:: mlas r1, r2, r3, r4 @ encoding: [0x92,0x43,0x31,0xe0]
@ mlas r1,r2,r3,r4