[AArch64] Add missing PCRel relocations for AArch64 in RuntimeDyldELF
llvm-svn: 201149
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@ -454,6 +454,48 @@ void RuntimeDyldELF::resolveAArch64Relocation(const SectionEntry &Section,
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assert((*TargetPtr >> 21 & 0x3) == 0 && "invalid shift for relocation");
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break;
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}
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case ELF::R_AARCH64_ADR_PREL_PG_HI21: {
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// Operation: Page(S+A) - Page(P)
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uint64_t Result = ((Value + Addend) & ~0xfffULL) - (FinalAddress & ~0xfffULL);
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// Check that -2^32 <= X < 2^32
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assert(static_cast<int64_t>(Result) >= (-1LL << 32) &&
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static_cast<int64_t>(Result) < (1LL << 32) &&
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"overflow check failed for relocation");
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// AArch64 code is emitted with .rela relocations. The data already in any
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// bits affected by the relocation on entry is garbage.
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*TargetPtr &= 0x9f00001fU;
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// Immediate goes in bits 30:29 + 5:23 of ADRP instruction, taken
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// from bits 32:12 of X.
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*TargetPtr |= ((Result & 0x3000U) << (29 - 12));
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*TargetPtr |= ((Result & 0x1ffffc000ULL) >> (14 - 5));
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break;
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}
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case ELF::R_AARCH64_LDST32_ABS_LO12_NC: {
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// Operation: S + A
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uint64_t Result = Value + Addend;
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// AArch64 code is emitted with .rela relocations. The data already in any
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// bits affected by the relocation on entry is garbage.
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*TargetPtr &= 0xffc003ffU;
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// Immediate goes in bits 21:10 of LD/ST instruction, taken
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// from bits 11:2 of X
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*TargetPtr |= ((Result & 0xffc) << (10 - 2));
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break;
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}
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case ELF::R_AARCH64_LDST64_ABS_LO12_NC: {
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// Operation: S + A
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uint64_t Result = Value + Addend;
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// AArch64 code is emitted with .rela relocations. The data already in any
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// bits affected by the relocation on entry is garbage.
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*TargetPtr &= 0xffc003ffU;
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// Immediate goes in bits 21:10 of LD/ST instruction, taken
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// from bits 11:3 of X
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*TargetPtr |= ((Result & 0xff8) << (10 - 3));
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break;
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}
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}
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}
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