R600: Add pattern for the BFI_INT instruction
llvm-svn: 179830
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@ -261,6 +261,26 @@ class DwordAddrPat<ValueType vt, RegisterClass rc> : Pat <
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(vt rc:$addr)
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>;
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// BFI_INT patterns
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multiclass BFIPatterns <Instruction BFI_INT> {
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// Definition from ISA doc:
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// (y & x) | (z & ~x)
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def : Pat <
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(or (and i32:$y, i32:$x), (and i32:$z, (not i32:$x))),
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(BFI_INT $x, $y, $z)
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>;
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// SHA-256 Ch function
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// z ^ (x & (y ^ z))
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def : Pat <
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(xor i32:$z, (and i32:$x, (xor i32:$y, i32:$z))),
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(BFI_INT $x, $y, $z)
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>;
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}
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include "R600Instructions.td"
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include "SIInstrInfo.td"
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@ -1570,6 +1570,9 @@ let Predicates = [isEGorCayman] in {
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VecALU
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>;
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def BFI_INT_eg : R600_3OP <0x06, "BFI_INT", []>;
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defm : BFIPatterns <BFI_INT_eg>;
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def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT",
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[(set R600_Reg32:$dst, (AMDGPUbitalign R600_Reg32:$src0, R600_Reg32:$src1,
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R600_Reg32:$src2))],
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@ -948,6 +948,7 @@ def V_CUBEMA_F32 : VOP3_32 <0x00000147, "V_CUBEMA_F32", []>;
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def V_BFE_U32 : VOP3_32 <0x00000148, "V_BFE_U32", []>;
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def V_BFE_I32 : VOP3_32 <0x00000149, "V_BFE_I32", []>;
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def V_BFI_B32 : VOP3_32 <0x0000014a, "V_BFI_B32", []>;
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defm : BFIPatterns <V_BFI_B32>;
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def V_FMA_F32 : VOP3_32 <0x0000014b, "V_FMA_F32", []>;
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def V_FMA_F64 : VOP3_64 <0x0000014c, "V_FMA_F64", []>;
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//def V_LERP_U8 : VOP3_U8 <0x0000014d, "V_LERP_U8", []>;
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@ -0,0 +1,34 @@
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; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600-CHECK %s
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; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI-CHECK %s
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; BFI_INT Definition pattern from ISA docs
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; (y & x) | (z & ~x)
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;
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; R600-CHECK: @bfi_def
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; R600-CHECK: BFI_INT
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; SI-CHECK: @bfi_def
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; SI-CHECK: V_BFI_B32
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define void @bfi_def(i32 addrspace(1)* %out, i32 %x, i32 %y, i32 %z) {
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entry:
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%0 = xor i32 %x, -1
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%1 = and i32 %z, %0
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%2 = and i32 %y, %x
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%3 = or i32 %1, %2
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store i32 %3, i32 addrspace(1)* %out
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ret void
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}
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; SHA-256 Ch function
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; z ^ (x & (y ^ z))
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; R600-CHECK: @bfi_sha256_ch
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; R600-CHECK: BFI_INT
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; SI-CHECK: @bfi_sha256_ch
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; SI-CHECK: V_BFI_B32
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define void @bfi_sha256_ch(i32 addrspace(1)* %out, i32 %x, i32 %y, i32 %z) {
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entry:
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%0 = xor i32 %y, %z
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%1 = and i32 %x, %0
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%2 = xor i32 %z, %1
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store i32 %2, i32 addrspace(1)* %out
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ret void
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}
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