Push methods into base class in preparation for sharing.
llvm-svn: 75020
This commit is contained in:
parent
f731a2df6b
commit
9ca33e8a9f
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@ -13,6 +13,7 @@
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#include "ARM.h"
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#include "ARM.h"
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#include "ARMAddressingModes.h"
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#include "ARMAddressingModes.h"
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#include "ARMBaseInstrInfo.h"
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#include "ARMBaseRegisterInfo.h"
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#include "ARMBaseRegisterInfo.h"
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#include "ARMInstrInfo.h"
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#include "ARMInstrInfo.h"
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#include "ARMMachineFunctionInfo.h"
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#include "ARMMachineFunctionInfo.h"
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@ -147,7 +148,7 @@ unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum,
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}
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}
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}
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}
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ARMBaseRegisterInfo::ARMBaseRegisterInfo(const TargetInstrInfo &tii,
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ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
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const ARMSubtarget &sti)
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const ARMSubtarget &sti)
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: ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
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: ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
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TII(tii), STI(sti),
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TII(tii), STI(sti),
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@ -861,4 +862,541 @@ unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
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return 0;
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return 0;
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}
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}
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static inline
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const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
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return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
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}
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static inline
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const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
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return MIB.addReg(0);
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}
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/// emitLoadConstPool - Emits a load from constpool to materialize the
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/// specified immediate.
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void ARMBaseRegisterInfo::
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emitLoadConstPool(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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const TargetInstrInfo *TII, DebugLoc dl,
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unsigned DestReg, int Val,
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ARMCC::CondCodes Pred,
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unsigned PredReg) const {
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MachineFunction &MF = *MBB.getParent();
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MachineConstantPool *ConstantPool = MF.getConstantPool();
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Constant *C = ConstantInt::get(Type::Int32Ty, Val);
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unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
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BuildMI(MBB, MBBI, dl, TII->get(ARM::LDRcp), DestReg)
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.addConstantPoolIndex(Idx)
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.addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
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}
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bool ARMBaseRegisterInfo::
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requiresRegisterScavenging(const MachineFunction &MF) const {
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return true;
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}
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// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
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// not required, we reserve argument space for call sites in the function
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// immediately on entry to the current function. This eliminates the need for
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// add/sub sp brackets around call sites. Returns true if the call frame is
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// included as part of the stack frame.
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bool ARMBaseRegisterInfo::
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hasReservedCallFrame(MachineFunction &MF) const {
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const MachineFrameInfo *FFI = MF.getFrameInfo();
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unsigned CFSize = FFI->getMaxCallFrameSize();
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// It's not always a good idea to include the call frame as part of the
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// stack frame. ARM (especially Thumb) has small immediate offset to
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// address the stack frame. So a large call frame can cause poor codegen
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// and may even makes it impossible to scavenge a register.
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if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
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return false;
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return !MF.getFrameInfo()->hasVarSizedObjects();
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}
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/// emitARMRegPlusImmediate - Emits a series of instructions to materialize
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/// a destreg = basereg + immediate in ARM code.
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static
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void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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unsigned DestReg, unsigned BaseReg, int NumBytes,
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ARMCC::CondCodes Pred, unsigned PredReg,
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const TargetInstrInfo &TII,
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DebugLoc dl) {
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bool isSub = NumBytes < 0;
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if (isSub) NumBytes = -NumBytes;
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while (NumBytes) {
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unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
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unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
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assert(ThisVal && "Didn't extract field correctly");
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// We will handle these bits from offset, clear them.
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NumBytes &= ~ThisVal;
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// Get the properly encoded SOImmVal field.
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int SOImmVal = ARM_AM::getSOImmVal(ThisVal);
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assert(SOImmVal != -1 && "Bit extraction didn't work?");
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// Build the new ADD / SUB.
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BuildMI(MBB, MBBI, dl, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg)
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.addReg(BaseReg, RegState::Kill).addImm(SOImmVal)
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.addImm((unsigned)Pred).addReg(PredReg).addReg(0);
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BaseReg = DestReg;
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}
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}
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static void
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emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
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const TargetInstrInfo &TII, DebugLoc dl,
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int NumBytes,
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ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
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emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes,
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Pred, PredReg, TII, dl);
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}
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void ARMBaseRegisterInfo::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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if (!hasReservedCallFrame(MF)) {
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// If we have alloca, convert as follows:
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// ADJCALLSTACKDOWN -> sub, sp, sp, amount
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// ADJCALLSTACKUP -> add, sp, sp, amount
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MachineInstr *Old = I;
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DebugLoc dl = Old->getDebugLoc();
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unsigned Amount = Old->getOperand(0).getImm();
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if (Amount != 0) {
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// We need to keep the stack aligned properly. To do this, we round the
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// amount of space needed for the outgoing arguments up to the next
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// alignment boundary.
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unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
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Amount = (Amount+Align-1)/Align*Align;
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// Replace the pseudo instruction with a new instruction...
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unsigned Opc = Old->getOpcode();
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ARMCC::CondCodes Pred = (ARMCC::CondCodes)Old->getOperand(1).getImm();
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if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
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// Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
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unsigned PredReg = Old->getOperand(2).getReg();
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emitSPUpdate(MBB, I, TII, dl, -Amount, Pred, PredReg);
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} else {
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// Note: PredReg is operand 3 for ADJCALLSTACKUP.
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unsigned PredReg = Old->getOperand(3).getReg();
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assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
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emitSPUpdate(MBB, I, TII, dl, Amount, Pred, PredReg);
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}
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}
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}
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MBB.erase(I);
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}
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/// findScratchRegister - Find a 'free' ARM register. If register scavenger
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/// is not being used, R12 is available. Otherwise, try for a call-clobbered
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/// register first and then a spilled callee-saved register if that fails.
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static
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unsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC,
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ARMFunctionInfo *AFI) {
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unsigned Reg = RS ? RS->FindUnusedReg(RC, true) : (unsigned) ARM::R12;
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assert (!AFI->isThumbFunction());
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if (Reg == 0)
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// Try a already spilled CS register.
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Reg = RS->FindUnusedReg(RC, AFI->getSpilledCSRegisters());
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return Reg;
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}
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void ARMBaseRegisterInfo::
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eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, RegScavenger *RS) const{
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unsigned i = 0;
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MachineInstr &MI = *II;
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MachineBasicBlock &MBB = *MI.getParent();
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MachineFunction &MF = *MBB.getParent();
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ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
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DebugLoc dl = MI.getDebugLoc();
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while (!MI.getOperand(i).isFI()) {
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++i;
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assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
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}
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unsigned FrameReg = ARM::SP;
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int FrameIndex = MI.getOperand(i).getIndex();
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int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
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MF.getFrameInfo()->getStackSize() + SPAdj;
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if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
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Offset -= AFI->getGPRCalleeSavedArea1Offset();
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else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
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Offset -= AFI->getGPRCalleeSavedArea2Offset();
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else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex))
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Offset -= AFI->getDPRCalleeSavedAreaOffset();
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else if (hasFP(MF)) {
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assert(SPAdj == 0 && "Unexpected");
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// There is alloca()'s in this function, must reference off the frame
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// pointer instead.
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FrameReg = getFrameRegister(MF);
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Offset -= AFI->getFramePtrSpillOffset();
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}
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unsigned Opcode = MI.getOpcode();
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const TargetInstrDesc &Desc = MI.getDesc();
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unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
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bool isSub = false;
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// Memory operands in inline assembly always use AddrMode2.
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if (Opcode == ARM::INLINEASM)
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AddrMode = ARMII::AddrMode2;
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if (Opcode == ARM::ADDri) {
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Offset += MI.getOperand(i+1).getImm();
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if (Offset == 0) {
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// Turn it into a move.
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MI.setDesc(TII.get(ARM::MOVr));
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MI.getOperand(i).ChangeToRegister(FrameReg, false);
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MI.RemoveOperand(i+1);
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return;
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} else if (Offset < 0) {
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Offset = -Offset;
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isSub = true;
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MI.setDesc(TII.get(ARM::SUBri));
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}
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// Common case: small offset, fits into instruction.
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int ImmedOffset = ARM_AM::getSOImmVal(Offset);
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if (ImmedOffset != -1) {
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// Replace the FrameIndex with sp / fp
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MI.getOperand(i).ChangeToRegister(FrameReg, false);
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MI.getOperand(i+1).ChangeToImmediate(ImmedOffset);
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return;
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}
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// Otherwise, we fallback to common code below to form the imm offset with
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// a sequence of ADDri instructions. First though, pull as much of the imm
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// into this ADDri as possible.
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unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
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unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
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// We will handle these bits from offset, clear them.
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Offset &= ~ThisImmVal;
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// Get the properly encoded SOImmVal field.
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int ThisSOImmVal = ARM_AM::getSOImmVal(ThisImmVal);
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assert(ThisSOImmVal != -1 && "Bit extraction didn't work?");
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MI.getOperand(i+1).ChangeToImmediate(ThisSOImmVal);
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} else {
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unsigned ImmIdx = 0;
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int InstrOffs = 0;
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unsigned NumBits = 0;
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unsigned Scale = 1;
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switch (AddrMode) {
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case ARMII::AddrMode2: {
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ImmIdx = i+2;
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InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
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if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
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InstrOffs *= -1;
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NumBits = 12;
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break;
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}
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case ARMII::AddrMode3: {
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ImmIdx = i+2;
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InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
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if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
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InstrOffs *= -1;
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NumBits = 8;
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break;
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}
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case ARMII::AddrMode5: {
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ImmIdx = i+1;
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InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
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if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
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InstrOffs *= -1;
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NumBits = 8;
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Scale = 4;
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break;
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}
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default:
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LLVM_UNREACHABLE("Unsupported addressing mode!");
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break;
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}
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Offset += InstrOffs * Scale;
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assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
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if (Offset < 0) {
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Offset = -Offset;
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isSub = true;
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}
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// Common case: small offset, fits into instruction.
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MachineOperand &ImmOp = MI.getOperand(ImmIdx);
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int ImmedOffset = Offset / Scale;
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unsigned Mask = (1 << NumBits) - 1;
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if ((unsigned)Offset <= Mask * Scale) {
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// Replace the FrameIndex with sp
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MI.getOperand(i).ChangeToRegister(FrameReg, false);
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if (isSub)
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ImmedOffset |= 1 << NumBits;
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ImmOp.ChangeToImmediate(ImmedOffset);
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return;
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}
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// Otherwise, it didn't fit. Pull in what we can to simplify the immed.
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ImmedOffset = ImmedOffset & Mask;
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if (isSub)
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ImmedOffset |= 1 << NumBits;
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ImmOp.ChangeToImmediate(ImmedOffset);
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Offset &= ~(Mask*Scale);
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}
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// If we get here, the immediate doesn't fit into the instruction. We folded
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// as much as possible above, handle the rest, providing a register that is
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// SP+LargeImm.
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assert(Offset && "This code isn't needed if offset already handled!");
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// Insert a set of r12 with the full address: r12 = sp + offset
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// If the offset we have is too large to fit into the instruction, we need
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// to form it with a series of ADDri's. Do this by taking 8-bit chunks
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// out of 'Offset'.
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unsigned ScratchReg = findScratchRegister(RS, &ARM::GPRRegClass, AFI);
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if (ScratchReg == 0)
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// No register is "free". Scavenge a register.
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ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II, SPAdj);
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int PIdx = MI.findFirstPredOperandIdx();
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ARMCC::CondCodes Pred = (PIdx == -1)
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? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
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unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
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emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg,
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isSub ? -Offset : Offset, Pred, PredReg, TII, dl);
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MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
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}
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/// Move iterator pass the next bunch of callee save load / store ops for
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/// the particular spill area (1: integer area 1, 2: integer area 2,
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/// 3: fp area, 0: don't care).
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static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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int Opc, unsigned Area,
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const ARMSubtarget &STI) {
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while (MBBI != MBB.end() &&
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MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFI()) {
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if (Area != 0) {
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bool Done = false;
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unsigned Category = 0;
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switch (MBBI->getOperand(0).getReg()) {
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case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7:
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case ARM::LR:
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Category = 1;
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break;
|
||||||
|
case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
|
||||||
|
Category = STI.isTargetDarwin() ? 2 : 1;
|
||||||
|
break;
|
||||||
|
case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11:
|
||||||
|
case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
|
||||||
|
Category = 3;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
Done = true;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
if (Done || Category != Area)
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
++MBBI;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void ARMBaseRegisterInfo::
|
||||||
|
emitPrologue(MachineFunction &MF) const {
|
||||||
|
MachineBasicBlock &MBB = MF.front();
|
||||||
|
MachineBasicBlock::iterator MBBI = MBB.begin();
|
||||||
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
||||||
|
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
||||||
|
unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
|
||||||
|
unsigned NumBytes = MFI->getStackSize();
|
||||||
|
const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
|
||||||
|
DebugLoc dl = (MBBI != MBB.end() ?
|
||||||
|
MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
|
||||||
|
|
||||||
|
// Determine the sizes of each callee-save spill areas and record which frame
|
||||||
|
// belongs to which callee-save spill areas.
|
||||||
|
unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
|
||||||
|
int FramePtrSpillFI = 0;
|
||||||
|
|
||||||
|
if (VARegSaveSize)
|
||||||
|
emitSPUpdate(MBB, MBBI, TII, dl, -VARegSaveSize);
|
||||||
|
|
||||||
|
if (!AFI->hasStackFrame()) {
|
||||||
|
if (NumBytes != 0)
|
||||||
|
emitSPUpdate(MBB, MBBI, TII, dl, -NumBytes);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
|
||||||
|
unsigned Reg = CSI[i].getReg();
|
||||||
|
int FI = CSI[i].getFrameIdx();
|
||||||
|
switch (Reg) {
|
||||||
|
case ARM::R4:
|
||||||
|
case ARM::R5:
|
||||||
|
case ARM::R6:
|
||||||
|
case ARM::R7:
|
||||||
|
case ARM::LR:
|
||||||
|
if (Reg == FramePtr)
|
||||||
|
FramePtrSpillFI = FI;
|
||||||
|
AFI->addGPRCalleeSavedArea1Frame(FI);
|
||||||
|
GPRCS1Size += 4;
|
||||||
|
break;
|
||||||
|
case ARM::R8:
|
||||||
|
case ARM::R9:
|
||||||
|
case ARM::R10:
|
||||||
|
case ARM::R11:
|
||||||
|
if (Reg == FramePtr)
|
||||||
|
FramePtrSpillFI = FI;
|
||||||
|
if (STI.isTargetDarwin()) {
|
||||||
|
AFI->addGPRCalleeSavedArea2Frame(FI);
|
||||||
|
GPRCS2Size += 4;
|
||||||
|
} else {
|
||||||
|
AFI->addGPRCalleeSavedArea1Frame(FI);
|
||||||
|
GPRCS1Size += 4;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
AFI->addDPRCalleeSavedAreaFrame(FI);
|
||||||
|
DPRCSSize += 8;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
// Build the new SUBri to adjust SP for integer callee-save spill area 1.
|
||||||
|
emitSPUpdate(MBB, MBBI, TII, dl, -GPRCS1Size);
|
||||||
|
movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI);
|
||||||
|
|
||||||
|
// Darwin ABI requires FP to point to the stack slot that contains the
|
||||||
|
// previous FP.
|
||||||
|
if (STI.isTargetDarwin() || hasFP(MF)) {
|
||||||
|
MachineInstrBuilder MIB =
|
||||||
|
BuildMI(MBB, MBBI, dl, TII.get(ARM::ADDri), FramePtr)
|
||||||
|
.addFrameIndex(FramePtrSpillFI).addImm(0);
|
||||||
|
AddDefaultCC(AddDefaultPred(MIB));
|
||||||
|
}
|
||||||
|
|
||||||
|
// Build the new SUBri to adjust SP for integer callee-save spill area 2.
|
||||||
|
emitSPUpdate(MBB, MBBI, TII, dl, -GPRCS2Size);
|
||||||
|
|
||||||
|
// Build the new SUBri to adjust SP for FP callee-save spill area.
|
||||||
|
movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI);
|
||||||
|
emitSPUpdate(MBB, MBBI, TII, dl, -DPRCSSize);
|
||||||
|
|
||||||
|
// Determine starting offsets of spill areas.
|
||||||
|
unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
|
||||||
|
unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
|
||||||
|
unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
|
||||||
|
AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
|
||||||
|
AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
|
||||||
|
AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
|
||||||
|
AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
|
||||||
|
|
||||||
|
NumBytes = DPRCSOffset;
|
||||||
|
if (NumBytes) {
|
||||||
|
// Insert it after all the callee-save spills.
|
||||||
|
movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI);
|
||||||
|
emitSPUpdate(MBB, MBBI, TII, dl, -NumBytes);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (STI.isTargetELF() && hasFP(MF)) {
|
||||||
|
MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
|
||||||
|
AFI->getFramePtrSpillOffset());
|
||||||
|
}
|
||||||
|
|
||||||
|
AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
|
||||||
|
AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
|
||||||
|
AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
|
||||||
|
}
|
||||||
|
|
||||||
|
static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
|
||||||
|
for (unsigned i = 0; CSRegs[i]; ++i)
|
||||||
|
if (Reg == CSRegs[i])
|
||||||
|
return true;
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
|
||||||
|
return ((MI->getOpcode() == ARM::FLDD ||
|
||||||
|
MI->getOpcode() == ARM::LDR) &&
|
||||||
|
MI->getOperand(1).isFI() &&
|
||||||
|
isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
|
||||||
|
}
|
||||||
|
|
||||||
|
void ARMBaseRegisterInfo::
|
||||||
|
emitEpilogue(MachineFunction &MF,
|
||||||
|
MachineBasicBlock &MBB) const {
|
||||||
|
MachineBasicBlock::iterator MBBI = prior(MBB.end());
|
||||||
|
assert(MBBI->getOpcode() == ARM::BX_RET &&
|
||||||
|
"Can only insert epilog into returning blocks");
|
||||||
|
DebugLoc dl = MBBI->getDebugLoc();
|
||||||
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
||||||
|
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
||||||
|
unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
|
||||||
|
int NumBytes = (int)MFI->getStackSize();
|
||||||
|
|
||||||
|
if (!AFI->hasStackFrame()) {
|
||||||
|
if (NumBytes != 0)
|
||||||
|
emitSPUpdate(MBB, MBBI, TII, dl, NumBytes);
|
||||||
|
} else {
|
||||||
|
// Unwind MBBI to point to first LDR / FLDD.
|
||||||
|
const unsigned *CSRegs = getCalleeSavedRegs();
|
||||||
|
if (MBBI != MBB.begin()) {
|
||||||
|
do
|
||||||
|
--MBBI;
|
||||||
|
while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
|
||||||
|
if (!isCSRestore(MBBI, CSRegs))
|
||||||
|
++MBBI;
|
||||||
|
}
|
||||||
|
|
||||||
|
// Move SP to start of FP callee save spill area.
|
||||||
|
NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
|
||||||
|
AFI->getGPRCalleeSavedArea2Size() +
|
||||||
|
AFI->getDPRCalleeSavedAreaSize());
|
||||||
|
|
||||||
|
// Darwin ABI requires FP to point to the stack slot that contains the
|
||||||
|
// previous FP.
|
||||||
|
if ((STI.isTargetDarwin() && NumBytes) || hasFP(MF)) {
|
||||||
|
NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
|
||||||
|
// Reset SP based on frame pointer only if the stack frame extends beyond
|
||||||
|
// frame pointer stack slot or target is ELF and the function has FP.
|
||||||
|
if (AFI->getGPRCalleeSavedArea2Size() ||
|
||||||
|
AFI->getDPRCalleeSavedAreaSize() ||
|
||||||
|
AFI->getDPRCalleeSavedAreaOffset()||
|
||||||
|
hasFP(MF)) {
|
||||||
|
if (NumBytes)
|
||||||
|
BuildMI(MBB, MBBI, dl, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr)
|
||||||
|
.addImm(NumBytes)
|
||||||
|
.addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
|
||||||
|
else
|
||||||
|
BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr)
|
||||||
|
.addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
|
||||||
|
}
|
||||||
|
} else if (NumBytes) {
|
||||||
|
emitSPUpdate(MBB, MBBI, TII, dl, NumBytes);
|
||||||
|
}
|
||||||
|
|
||||||
|
// Move SP to start of integer callee save spill area 2.
|
||||||
|
movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI);
|
||||||
|
emitSPUpdate(MBB, MBBI, TII, dl, AFI->getDPRCalleeSavedAreaSize());
|
||||||
|
|
||||||
|
// Move SP to start of integer callee save spill area 1.
|
||||||
|
movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI);
|
||||||
|
emitSPUpdate(MBB, MBBI, TII, dl, AFI->getGPRCalleeSavedArea2Size());
|
||||||
|
|
||||||
|
// Move SP to SP upon entry to the function.
|
||||||
|
movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI);
|
||||||
|
emitSPUpdate(MBB, MBBI, TII, dl, AFI->getGPRCalleeSavedArea1Size());
|
||||||
|
}
|
||||||
|
|
||||||
|
if (VARegSaveSize)
|
||||||
|
emitSPUpdate(MBB, MBBI, TII, dl, VARegSaveSize);
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
#include "ARMGenRegisterInfo.inc"
|
#include "ARMGenRegisterInfo.inc"
|
||||||
|
|
|
@ -20,7 +20,7 @@
|
||||||
|
|
||||||
namespace llvm {
|
namespace llvm {
|
||||||
class ARMSubtarget;
|
class ARMSubtarget;
|
||||||
class TargetInstrInfo;
|
class ARMBaseInstrInfo;
|
||||||
class Type;
|
class Type;
|
||||||
|
|
||||||
/// Register allocation hints.
|
/// Register allocation hints.
|
||||||
|
@ -46,14 +46,16 @@ static inline bool isARMLowRegister(unsigned Reg) {
|
||||||
|
|
||||||
struct ARMBaseRegisterInfo : public ARMGenRegisterInfo {
|
struct ARMBaseRegisterInfo : public ARMGenRegisterInfo {
|
||||||
protected:
|
protected:
|
||||||
const TargetInstrInfo &TII;
|
const ARMBaseInstrInfo &TII;
|
||||||
const ARMSubtarget &STI;
|
const ARMSubtarget &STI;
|
||||||
|
|
||||||
/// FramePtr - ARM physical register used as frame ptr.
|
/// FramePtr - ARM physical register used as frame ptr.
|
||||||
unsigned FramePtr;
|
unsigned FramePtr;
|
||||||
public:
|
|
||||||
ARMBaseRegisterInfo(const TargetInstrInfo &tii, const ARMSubtarget &STI);
|
|
||||||
|
|
||||||
|
// Can be only subclassed.
|
||||||
|
explicit ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI);
|
||||||
|
|
||||||
|
public:
|
||||||
/// getRegisterNumbering - Given the enum value for some register, e.g.
|
/// getRegisterNumbering - Given the enum value for some register, e.g.
|
||||||
/// ARM::LR, return the number that it corresponds to (e.g. 14).
|
/// ARM::LR, return the number that it corresponds to (e.g. 14).
|
||||||
static unsigned getRegisterNumbering(unsigned RegEnum);
|
static unsigned getRegisterNumbering(unsigned RegEnum);
|
||||||
|
@ -70,8 +72,6 @@ public:
|
||||||
|
|
||||||
BitVector getReservedRegs(const MachineFunction &MF) const;
|
BitVector getReservedRegs(const MachineFunction &MF) const;
|
||||||
|
|
||||||
bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
|
|
||||||
|
|
||||||
const TargetRegisterClass *getPointerRegClass() const;
|
const TargetRegisterClass *getPointerRegClass() const;
|
||||||
|
|
||||||
std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
|
std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
|
||||||
|
@ -102,6 +102,33 @@ public:
|
||||||
|
|
||||||
bool isLowRegister(unsigned Reg) const;
|
bool isLowRegister(unsigned Reg) const;
|
||||||
|
|
||||||
|
|
||||||
|
/// emitLoadConstPool - Emits a load from constpool to materialize the
|
||||||
|
/// specified immediate.
|
||||||
|
virtual void emitLoadConstPool(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator &MBBI,
|
||||||
|
const TargetInstrInfo *TII, DebugLoc dl,
|
||||||
|
unsigned DestReg, int Val,
|
||||||
|
ARMCC::CondCodes Pred = ARMCC::AL,
|
||||||
|
unsigned PredReg = 0) const;
|
||||||
|
|
||||||
|
/// Code Generation virtual methods...
|
||||||
|
virtual bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
|
||||||
|
|
||||||
|
virtual bool requiresRegisterScavenging(const MachineFunction &MF) const;
|
||||||
|
|
||||||
|
virtual bool hasReservedCallFrame(MachineFunction &MF) const;
|
||||||
|
|
||||||
|
virtual void eliminateCallFramePseudoInstr(MachineFunction &MF,
|
||||||
|
MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator I) const;
|
||||||
|
|
||||||
|
virtual void eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||||
|
int SPAdj, RegScavenger *RS = NULL) const;
|
||||||
|
|
||||||
|
virtual void emitPrologue(MachineFunction &MF) const;
|
||||||
|
virtual void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
|
||||||
|
|
||||||
private:
|
private:
|
||||||
unsigned getRegisterPairEven(unsigned Reg, const MachineFunction &MF) const;
|
unsigned getRegisterPairEven(unsigned Reg, const MachineFunction &MF) const;
|
||||||
|
|
||||||
|
|
|
@ -34,539 +34,7 @@
|
||||||
#include "llvm/ADT/SmallVector.h"
|
#include "llvm/ADT/SmallVector.h"
|
||||||
using namespace llvm;
|
using namespace llvm;
|
||||||
|
|
||||||
ARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii,
|
ARMRegisterInfo::ARMRegisterInfo(const ARMBaseInstrInfo &tii,
|
||||||
const ARMSubtarget &sti)
|
const ARMSubtarget &sti)
|
||||||
: ARMBaseRegisterInfo(tii, sti) {
|
: ARMBaseRegisterInfo(tii, sti) {
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline
|
|
||||||
const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
|
|
||||||
return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline
|
|
||||||
const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
|
|
||||||
return MIB.addReg(0);
|
|
||||||
}
|
|
||||||
|
|
||||||
/// emitLoadConstPool - Emits a load from constpool to materialize the
|
|
||||||
/// specified immediate.
|
|
||||||
void ARMRegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
|
|
||||||
MachineBasicBlock::iterator &MBBI,
|
|
||||||
const TargetInstrInfo *TII, DebugLoc dl,
|
|
||||||
unsigned DestReg, int Val,
|
|
||||||
ARMCC::CondCodes Pred,
|
|
||||||
unsigned PredReg) const {
|
|
||||||
MachineFunction &MF = *MBB.getParent();
|
|
||||||
MachineConstantPool *ConstantPool = MF.getConstantPool();
|
|
||||||
Constant *C = ConstantInt::get(Type::Int32Ty, Val);
|
|
||||||
unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
|
|
||||||
|
|
||||||
BuildMI(MBB, MBBI, dl, TII->get(ARM::LDRcp), DestReg)
|
|
||||||
.addConstantPoolIndex(Idx)
|
|
||||||
.addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
|
|
||||||
}
|
|
||||||
|
|
||||||
bool
|
|
||||||
ARMRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
|
|
||||||
return true;
|
|
||||||
}
|
|
||||||
|
|
||||||
// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
|
|
||||||
// not required, we reserve argument space for call sites in the function
|
|
||||||
// immediately on entry to the current function. This eliminates the need for
|
|
||||||
// add/sub sp brackets around call sites. Returns true if the call frame is
|
|
||||||
// included as part of the stack frame.
|
|
||||||
bool ARMRegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
|
|
||||||
const MachineFrameInfo *FFI = MF.getFrameInfo();
|
|
||||||
unsigned CFSize = FFI->getMaxCallFrameSize();
|
|
||||||
// It's not always a good idea to include the call frame as part of the
|
|
||||||
// stack frame. ARM (especially Thumb) has small immediate offset to
|
|
||||||
// address the stack frame. So a large call frame can cause poor codegen
|
|
||||||
// and may even makes it impossible to scavenge a register.
|
|
||||||
if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
|
|
||||||
return false;
|
|
||||||
|
|
||||||
return !MF.getFrameInfo()->hasVarSizedObjects();
|
|
||||||
}
|
|
||||||
|
|
||||||
/// emitARMRegPlusImmediate - Emits a series of instructions to materialize
|
|
||||||
/// a destreg = basereg + immediate in ARM code.
|
|
||||||
static
|
|
||||||
void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
|
|
||||||
MachineBasicBlock::iterator &MBBI,
|
|
||||||
unsigned DestReg, unsigned BaseReg, int NumBytes,
|
|
||||||
ARMCC::CondCodes Pred, unsigned PredReg,
|
|
||||||
const TargetInstrInfo &TII,
|
|
||||||
DebugLoc dl) {
|
|
||||||
bool isSub = NumBytes < 0;
|
|
||||||
if (isSub) NumBytes = -NumBytes;
|
|
||||||
|
|
||||||
while (NumBytes) {
|
|
||||||
unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
|
|
||||||
unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
|
|
||||||
assert(ThisVal && "Didn't extract field correctly");
|
|
||||||
|
|
||||||
// We will handle these bits from offset, clear them.
|
|
||||||
NumBytes &= ~ThisVal;
|
|
||||||
|
|
||||||
// Get the properly encoded SOImmVal field.
|
|
||||||
int SOImmVal = ARM_AM::getSOImmVal(ThisVal);
|
|
||||||
assert(SOImmVal != -1 && "Bit extraction didn't work?");
|
|
||||||
|
|
||||||
// Build the new ADD / SUB.
|
|
||||||
BuildMI(MBB, MBBI, dl, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg)
|
|
||||||
.addReg(BaseReg, RegState::Kill).addImm(SOImmVal)
|
|
||||||
.addImm((unsigned)Pred).addReg(PredReg).addReg(0);
|
|
||||||
BaseReg = DestReg;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
static void
|
|
||||||
emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
|
|
||||||
const TargetInstrInfo &TII, DebugLoc dl,
|
|
||||||
int NumBytes,
|
|
||||||
ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
|
|
||||||
emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes,
|
|
||||||
Pred, PredReg, TII, dl);
|
|
||||||
}
|
|
||||||
|
|
||||||
void ARMRegisterInfo::
|
|
||||||
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
|
|
||||||
MachineBasicBlock::iterator I) const {
|
|
||||||
if (!hasReservedCallFrame(MF)) {
|
|
||||||
// If we have alloca, convert as follows:
|
|
||||||
// ADJCALLSTACKDOWN -> sub, sp, sp, amount
|
|
||||||
// ADJCALLSTACKUP -> add, sp, sp, amount
|
|
||||||
MachineInstr *Old = I;
|
|
||||||
DebugLoc dl = Old->getDebugLoc();
|
|
||||||
unsigned Amount = Old->getOperand(0).getImm();
|
|
||||||
if (Amount != 0) {
|
|
||||||
// We need to keep the stack aligned properly. To do this, we round the
|
|
||||||
// amount of space needed for the outgoing arguments up to the next
|
|
||||||
// alignment boundary.
|
|
||||||
unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
|
|
||||||
Amount = (Amount+Align-1)/Align*Align;
|
|
||||||
|
|
||||||
// Replace the pseudo instruction with a new instruction...
|
|
||||||
unsigned Opc = Old->getOpcode();
|
|
||||||
ARMCC::CondCodes Pred = (ARMCC::CondCodes)Old->getOperand(1).getImm();
|
|
||||||
if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
|
|
||||||
// Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
|
|
||||||
unsigned PredReg = Old->getOperand(2).getReg();
|
|
||||||
emitSPUpdate(MBB, I, TII, dl, -Amount, Pred, PredReg);
|
|
||||||
} else {
|
|
||||||
// Note: PredReg is operand 3 for ADJCALLSTACKUP.
|
|
||||||
unsigned PredReg = Old->getOperand(3).getReg();
|
|
||||||
assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
|
|
||||||
emitSPUpdate(MBB, I, TII, dl, Amount, Pred, PredReg);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
MBB.erase(I);
|
|
||||||
}
|
|
||||||
|
|
||||||
/// findScratchRegister - Find a 'free' ARM register. If register scavenger
|
|
||||||
/// is not being used, R12 is available. Otherwise, try for a call-clobbered
|
|
||||||
/// register first and then a spilled callee-saved register if that fails.
|
|
||||||
static
|
|
||||||
unsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC,
|
|
||||||
ARMFunctionInfo *AFI) {
|
|
||||||
unsigned Reg = RS ? RS->FindUnusedReg(RC, true) : (unsigned) ARM::R12;
|
|
||||||
assert (!AFI->isThumbFunction());
|
|
||||||
if (Reg == 0)
|
|
||||||
// Try a already spilled CS register.
|
|
||||||
Reg = RS->FindUnusedReg(RC, AFI->getSpilledCSRegisters());
|
|
||||||
|
|
||||||
return Reg;
|
|
||||||
}
|
|
||||||
|
|
||||||
void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|
||||||
int SPAdj, RegScavenger *RS) const{
|
|
||||||
unsigned i = 0;
|
|
||||||
MachineInstr &MI = *II;
|
|
||||||
MachineBasicBlock &MBB = *MI.getParent();
|
|
||||||
MachineFunction &MF = *MBB.getParent();
|
|
||||||
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
|
||||||
DebugLoc dl = MI.getDebugLoc();
|
|
||||||
|
|
||||||
while (!MI.getOperand(i).isFI()) {
|
|
||||||
++i;
|
|
||||||
assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
|
|
||||||
}
|
|
||||||
|
|
||||||
unsigned FrameReg = ARM::SP;
|
|
||||||
int FrameIndex = MI.getOperand(i).getIndex();
|
|
||||||
int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
|
|
||||||
MF.getFrameInfo()->getStackSize() + SPAdj;
|
|
||||||
|
|
||||||
if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
|
|
||||||
Offset -= AFI->getGPRCalleeSavedArea1Offset();
|
|
||||||
else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
|
|
||||||
Offset -= AFI->getGPRCalleeSavedArea2Offset();
|
|
||||||
else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex))
|
|
||||||
Offset -= AFI->getDPRCalleeSavedAreaOffset();
|
|
||||||
else if (hasFP(MF)) {
|
|
||||||
assert(SPAdj == 0 && "Unexpected");
|
|
||||||
// There is alloca()'s in this function, must reference off the frame
|
|
||||||
// pointer instead.
|
|
||||||
FrameReg = getFrameRegister(MF);
|
|
||||||
Offset -= AFI->getFramePtrSpillOffset();
|
|
||||||
}
|
|
||||||
|
|
||||||
unsigned Opcode = MI.getOpcode();
|
|
||||||
const TargetInstrDesc &Desc = MI.getDesc();
|
|
||||||
unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
|
|
||||||
bool isSub = false;
|
|
||||||
|
|
||||||
// Memory operands in inline assembly always use AddrMode2.
|
|
||||||
if (Opcode == ARM::INLINEASM)
|
|
||||||
AddrMode = ARMII::AddrMode2;
|
|
||||||
|
|
||||||
if (Opcode == ARM::ADDri) {
|
|
||||||
Offset += MI.getOperand(i+1).getImm();
|
|
||||||
if (Offset == 0) {
|
|
||||||
// Turn it into a move.
|
|
||||||
MI.setDesc(TII.get(ARM::MOVr));
|
|
||||||
MI.getOperand(i).ChangeToRegister(FrameReg, false);
|
|
||||||
MI.RemoveOperand(i+1);
|
|
||||||
return;
|
|
||||||
} else if (Offset < 0) {
|
|
||||||
Offset = -Offset;
|
|
||||||
isSub = true;
|
|
||||||
MI.setDesc(TII.get(ARM::SUBri));
|
|
||||||
}
|
|
||||||
|
|
||||||
// Common case: small offset, fits into instruction.
|
|
||||||
int ImmedOffset = ARM_AM::getSOImmVal(Offset);
|
|
||||||
if (ImmedOffset != -1) {
|
|
||||||
// Replace the FrameIndex with sp / fp
|
|
||||||
MI.getOperand(i).ChangeToRegister(FrameReg, false);
|
|
||||||
MI.getOperand(i+1).ChangeToImmediate(ImmedOffset);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
// Otherwise, we fallback to common code below to form the imm offset with
|
|
||||||
// a sequence of ADDri instructions. First though, pull as much of the imm
|
|
||||||
// into this ADDri as possible.
|
|
||||||
unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
|
|
||||||
unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
|
|
||||||
|
|
||||||
// We will handle these bits from offset, clear them.
|
|
||||||
Offset &= ~ThisImmVal;
|
|
||||||
|
|
||||||
// Get the properly encoded SOImmVal field.
|
|
||||||
int ThisSOImmVal = ARM_AM::getSOImmVal(ThisImmVal);
|
|
||||||
assert(ThisSOImmVal != -1 && "Bit extraction didn't work?");
|
|
||||||
MI.getOperand(i+1).ChangeToImmediate(ThisSOImmVal);
|
|
||||||
} else {
|
|
||||||
unsigned ImmIdx = 0;
|
|
||||||
int InstrOffs = 0;
|
|
||||||
unsigned NumBits = 0;
|
|
||||||
unsigned Scale = 1;
|
|
||||||
switch (AddrMode) {
|
|
||||||
case ARMII::AddrMode2: {
|
|
||||||
ImmIdx = i+2;
|
|
||||||
InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
|
|
||||||
if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
|
|
||||||
InstrOffs *= -1;
|
|
||||||
NumBits = 12;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
case ARMII::AddrMode3: {
|
|
||||||
ImmIdx = i+2;
|
|
||||||
InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
|
|
||||||
if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
|
|
||||||
InstrOffs *= -1;
|
|
||||||
NumBits = 8;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
case ARMII::AddrMode5: {
|
|
||||||
ImmIdx = i+1;
|
|
||||||
InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
|
|
||||||
if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
|
|
||||||
InstrOffs *= -1;
|
|
||||||
NumBits = 8;
|
|
||||||
Scale = 4;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
default:
|
|
||||||
LLVM_UNREACHABLE("Unsupported addressing mode!");
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
Offset += InstrOffs * Scale;
|
|
||||||
assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
|
|
||||||
if (Offset < 0) {
|
|
||||||
Offset = -Offset;
|
|
||||||
isSub = true;
|
|
||||||
}
|
|
||||||
|
|
||||||
// Common case: small offset, fits into instruction.
|
|
||||||
MachineOperand &ImmOp = MI.getOperand(ImmIdx);
|
|
||||||
int ImmedOffset = Offset / Scale;
|
|
||||||
unsigned Mask = (1 << NumBits) - 1;
|
|
||||||
if ((unsigned)Offset <= Mask * Scale) {
|
|
||||||
// Replace the FrameIndex with sp
|
|
||||||
MI.getOperand(i).ChangeToRegister(FrameReg, false);
|
|
||||||
if (isSub)
|
|
||||||
ImmedOffset |= 1 << NumBits;
|
|
||||||
ImmOp.ChangeToImmediate(ImmedOffset);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
// Otherwise, it didn't fit. Pull in what we can to simplify the immed.
|
|
||||||
ImmedOffset = ImmedOffset & Mask;
|
|
||||||
if (isSub)
|
|
||||||
ImmedOffset |= 1 << NumBits;
|
|
||||||
ImmOp.ChangeToImmediate(ImmedOffset);
|
|
||||||
Offset &= ~(Mask*Scale);
|
|
||||||
}
|
|
||||||
|
|
||||||
// If we get here, the immediate doesn't fit into the instruction. We folded
|
|
||||||
// as much as possible above, handle the rest, providing a register that is
|
|
||||||
// SP+LargeImm.
|
|
||||||
assert(Offset && "This code isn't needed if offset already handled!");
|
|
||||||
|
|
||||||
// Insert a set of r12 with the full address: r12 = sp + offset
|
|
||||||
// If the offset we have is too large to fit into the instruction, we need
|
|
||||||
// to form it with a series of ADDri's. Do this by taking 8-bit chunks
|
|
||||||
// out of 'Offset'.
|
|
||||||
unsigned ScratchReg = findScratchRegister(RS, &ARM::GPRRegClass, AFI);
|
|
||||||
if (ScratchReg == 0)
|
|
||||||
// No register is "free". Scavenge a register.
|
|
||||||
ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II, SPAdj);
|
|
||||||
int PIdx = MI.findFirstPredOperandIdx();
|
|
||||||
ARMCC::CondCodes Pred = (PIdx == -1)
|
|
||||||
? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
|
|
||||||
unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
|
|
||||||
emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg,
|
|
||||||
isSub ? -Offset : Offset, Pred, PredReg, TII, dl);
|
|
||||||
MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
|
|
||||||
}
|
|
||||||
|
|
||||||
/// Move iterator pass the next bunch of callee save load / store ops for
|
|
||||||
/// the particular spill area (1: integer area 1, 2: integer area 2,
|
|
||||||
/// 3: fp area, 0: don't care).
|
|
||||||
static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
|
|
||||||
MachineBasicBlock::iterator &MBBI,
|
|
||||||
int Opc, unsigned Area,
|
|
||||||
const ARMSubtarget &STI) {
|
|
||||||
while (MBBI != MBB.end() &&
|
|
||||||
MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFI()) {
|
|
||||||
if (Area != 0) {
|
|
||||||
bool Done = false;
|
|
||||||
unsigned Category = 0;
|
|
||||||
switch (MBBI->getOperand(0).getReg()) {
|
|
||||||
case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7:
|
|
||||||
case ARM::LR:
|
|
||||||
Category = 1;
|
|
||||||
break;
|
|
||||||
case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
|
|
||||||
Category = STI.isTargetDarwin() ? 2 : 1;
|
|
||||||
break;
|
|
||||||
case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11:
|
|
||||||
case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
|
|
||||||
Category = 3;
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
Done = true;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
if (Done || Category != Area)
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
++MBBI;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
|
|
||||||
MachineBasicBlock &MBB = MF.front();
|
|
||||||
MachineBasicBlock::iterator MBBI = MBB.begin();
|
|
||||||
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
||||||
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
|
||||||
unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
|
|
||||||
unsigned NumBytes = MFI->getStackSize();
|
|
||||||
const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
|
|
||||||
DebugLoc dl = (MBBI != MBB.end() ?
|
|
||||||
MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
|
|
||||||
|
|
||||||
// Determine the sizes of each callee-save spill areas and record which frame
|
|
||||||
// belongs to which callee-save spill areas.
|
|
||||||
unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
|
|
||||||
int FramePtrSpillFI = 0;
|
|
||||||
|
|
||||||
if (VARegSaveSize)
|
|
||||||
emitSPUpdate(MBB, MBBI, TII, dl, -VARegSaveSize);
|
|
||||||
|
|
||||||
if (!AFI->hasStackFrame()) {
|
|
||||||
if (NumBytes != 0)
|
|
||||||
emitSPUpdate(MBB, MBBI, TII, dl, -NumBytes);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
|
|
||||||
unsigned Reg = CSI[i].getReg();
|
|
||||||
int FI = CSI[i].getFrameIdx();
|
|
||||||
switch (Reg) {
|
|
||||||
case ARM::R4:
|
|
||||||
case ARM::R5:
|
|
||||||
case ARM::R6:
|
|
||||||
case ARM::R7:
|
|
||||||
case ARM::LR:
|
|
||||||
if (Reg == FramePtr)
|
|
||||||
FramePtrSpillFI = FI;
|
|
||||||
AFI->addGPRCalleeSavedArea1Frame(FI);
|
|
||||||
GPRCS1Size += 4;
|
|
||||||
break;
|
|
||||||
case ARM::R8:
|
|
||||||
case ARM::R9:
|
|
||||||
case ARM::R10:
|
|
||||||
case ARM::R11:
|
|
||||||
if (Reg == FramePtr)
|
|
||||||
FramePtrSpillFI = FI;
|
|
||||||
if (STI.isTargetDarwin()) {
|
|
||||||
AFI->addGPRCalleeSavedArea2Frame(FI);
|
|
||||||
GPRCS2Size += 4;
|
|
||||||
} else {
|
|
||||||
AFI->addGPRCalleeSavedArea1Frame(FI);
|
|
||||||
GPRCS1Size += 4;
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
AFI->addDPRCalleeSavedAreaFrame(FI);
|
|
||||||
DPRCSSize += 8;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
// Build the new SUBri to adjust SP for integer callee-save spill area 1.
|
|
||||||
emitSPUpdate(MBB, MBBI, TII, dl, -GPRCS1Size);
|
|
||||||
movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI);
|
|
||||||
|
|
||||||
// Darwin ABI requires FP to point to the stack slot that contains the
|
|
||||||
// previous FP.
|
|
||||||
if (STI.isTargetDarwin() || hasFP(MF)) {
|
|
||||||
MachineInstrBuilder MIB =
|
|
||||||
BuildMI(MBB, MBBI, dl, TII.get(ARM::ADDri), FramePtr)
|
|
||||||
.addFrameIndex(FramePtrSpillFI).addImm(0);
|
|
||||||
AddDefaultCC(AddDefaultPred(MIB));
|
|
||||||
}
|
|
||||||
|
|
||||||
// Build the new SUBri to adjust SP for integer callee-save spill area 2.
|
|
||||||
emitSPUpdate(MBB, MBBI, TII, dl, -GPRCS2Size);
|
|
||||||
|
|
||||||
// Build the new SUBri to adjust SP for FP callee-save spill area.
|
|
||||||
movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI);
|
|
||||||
emitSPUpdate(MBB, MBBI, TII, dl, -DPRCSSize);
|
|
||||||
|
|
||||||
// Determine starting offsets of spill areas.
|
|
||||||
unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
|
|
||||||
unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
|
|
||||||
unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
|
|
||||||
AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
|
|
||||||
AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
|
|
||||||
AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
|
|
||||||
AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
|
|
||||||
|
|
||||||
NumBytes = DPRCSOffset;
|
|
||||||
if (NumBytes) {
|
|
||||||
// Insert it after all the callee-save spills.
|
|
||||||
movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI);
|
|
||||||
emitSPUpdate(MBB, MBBI, TII, dl, -NumBytes);
|
|
||||||
}
|
|
||||||
|
|
||||||
if (STI.isTargetELF() && hasFP(MF)) {
|
|
||||||
MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
|
|
||||||
AFI->getFramePtrSpillOffset());
|
|
||||||
}
|
|
||||||
|
|
||||||
AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
|
|
||||||
AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
|
|
||||||
AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
|
|
||||||
}
|
|
||||||
|
|
||||||
static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
|
|
||||||
for (unsigned i = 0; CSRegs[i]; ++i)
|
|
||||||
if (Reg == CSRegs[i])
|
|
||||||
return true;
|
|
||||||
return false;
|
|
||||||
}
|
|
||||||
|
|
||||||
static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
|
|
||||||
return ((MI->getOpcode() == ARM::FLDD ||
|
|
||||||
MI->getOpcode() == ARM::LDR) &&
|
|
||||||
MI->getOperand(1).isFI() &&
|
|
||||||
isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
|
|
||||||
}
|
|
||||||
|
|
||||||
void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
|
|
||||||
MachineBasicBlock &MBB) const {
|
|
||||||
MachineBasicBlock::iterator MBBI = prior(MBB.end());
|
|
||||||
assert(MBBI->getOpcode() == ARM::BX_RET &&
|
|
||||||
"Can only insert epilog into returning blocks");
|
|
||||||
DebugLoc dl = MBBI->getDebugLoc();
|
|
||||||
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
||||||
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
|
||||||
unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
|
|
||||||
int NumBytes = (int)MFI->getStackSize();
|
|
||||||
|
|
||||||
if (!AFI->hasStackFrame()) {
|
|
||||||
if (NumBytes != 0)
|
|
||||||
emitSPUpdate(MBB, MBBI, TII, dl, NumBytes);
|
|
||||||
} else {
|
|
||||||
// Unwind MBBI to point to first LDR / FLDD.
|
|
||||||
const unsigned *CSRegs = getCalleeSavedRegs();
|
|
||||||
if (MBBI != MBB.begin()) {
|
|
||||||
do
|
|
||||||
--MBBI;
|
|
||||||
while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
|
|
||||||
if (!isCSRestore(MBBI, CSRegs))
|
|
||||||
++MBBI;
|
|
||||||
}
|
|
||||||
|
|
||||||
// Move SP to start of FP callee save spill area.
|
|
||||||
NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
|
|
||||||
AFI->getGPRCalleeSavedArea2Size() +
|
|
||||||
AFI->getDPRCalleeSavedAreaSize());
|
|
||||||
|
|
||||||
// Darwin ABI requires FP to point to the stack slot that contains the
|
|
||||||
// previous FP.
|
|
||||||
if ((STI.isTargetDarwin() && NumBytes) || hasFP(MF)) {
|
|
||||||
NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
|
|
||||||
// Reset SP based on frame pointer only if the stack frame extends beyond
|
|
||||||
// frame pointer stack slot or target is ELF and the function has FP.
|
|
||||||
if (AFI->getGPRCalleeSavedArea2Size() ||
|
|
||||||
AFI->getDPRCalleeSavedAreaSize() ||
|
|
||||||
AFI->getDPRCalleeSavedAreaOffset()||
|
|
||||||
hasFP(MF)) {
|
|
||||||
if (NumBytes)
|
|
||||||
BuildMI(MBB, MBBI, dl, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr)
|
|
||||||
.addImm(NumBytes)
|
|
||||||
.addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
|
|
||||||
else
|
|
||||||
BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr)
|
|
||||||
.addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
|
|
||||||
}
|
|
||||||
} else if (NumBytes) {
|
|
||||||
emitSPUpdate(MBB, MBBI, TII, dl, NumBytes);
|
|
||||||
}
|
|
||||||
|
|
||||||
// Move SP to start of integer callee save spill area 2.
|
|
||||||
movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI);
|
|
||||||
emitSPUpdate(MBB, MBBI, TII, dl, AFI->getDPRCalleeSavedAreaSize());
|
|
||||||
|
|
||||||
// Move SP to start of integer callee save spill area 1.
|
|
||||||
movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI);
|
|
||||||
emitSPUpdate(MBB, MBBI, TII, dl, AFI->getGPRCalleeSavedArea2Size());
|
|
||||||
|
|
||||||
// Move SP to SP upon entry to the function.
|
|
||||||
movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI);
|
|
||||||
emitSPUpdate(MBB, MBBI, TII, dl, AFI->getGPRCalleeSavedArea1Size());
|
|
||||||
}
|
|
||||||
|
|
||||||
if (VARegSaveSize)
|
|
||||||
emitSPUpdate(MBB, MBBI, TII, dl, VARegSaveSize);
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
|
@ -20,38 +20,12 @@
|
||||||
|
|
||||||
namespace llvm {
|
namespace llvm {
|
||||||
class ARMSubtarget;
|
class ARMSubtarget;
|
||||||
class TargetInstrInfo;
|
class ARMBaseInstrInfo;
|
||||||
class Type;
|
class Type;
|
||||||
|
|
||||||
struct ARMRegisterInfo : public ARMBaseRegisterInfo {
|
struct ARMRegisterInfo : public ARMBaseRegisterInfo {
|
||||||
public:
|
public:
|
||||||
ARMRegisterInfo(const TargetInstrInfo &tii, const ARMSubtarget &STI);
|
ARMRegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI);
|
||||||
|
|
||||||
/// emitLoadConstPool - Emits a load from constpool to materialize the
|
|
||||||
/// specified immediate.
|
|
||||||
void emitLoadConstPool(MachineBasicBlock &MBB,
|
|
||||||
MachineBasicBlock::iterator &MBBI,
|
|
||||||
const TargetInstrInfo *TII, DebugLoc dl,
|
|
||||||
unsigned DestReg, int Val,
|
|
||||||
ARMCC::CondCodes Pred = ARMCC::AL,
|
|
||||||
unsigned PredReg = 0) const;
|
|
||||||
|
|
||||||
/// Code Generation virtual methods...
|
|
||||||
bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
|
|
||||||
|
|
||||||
bool requiresRegisterScavenging(const MachineFunction &MF) const;
|
|
||||||
|
|
||||||
bool hasReservedCallFrame(MachineFunction &MF) const;
|
|
||||||
|
|
||||||
void eliminateCallFramePseudoInstr(MachineFunction &MF,
|
|
||||||
MachineBasicBlock &MBB,
|
|
||||||
MachineBasicBlock::iterator I) const;
|
|
||||||
|
|
||||||
void eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|
||||||
int SPAdj, RegScavenger *RS = NULL) const;
|
|
||||||
|
|
||||||
void emitPrologue(MachineFunction &MF) const;
|
|
||||||
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
} // end namespace llvm
|
} // end namespace llvm
|
||||||
|
|
|
@ -38,7 +38,7 @@ ThumbRegScavenging("enable-thumb-reg-scavenging",
|
||||||
cl::Hidden,
|
cl::Hidden,
|
||||||
cl::desc("Enable register scavenging on Thumb"));
|
cl::desc("Enable register scavenging on Thumb"));
|
||||||
|
|
||||||
Thumb1RegisterInfo::Thumb1RegisterInfo(const TargetInstrInfo &tii,
|
Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMBaseInstrInfo &tii,
|
||||||
const ARMSubtarget &sti)
|
const ARMSubtarget &sti)
|
||||||
: ARMBaseRegisterInfo(tii, sti) {
|
: ARMBaseRegisterInfo(tii, sti) {
|
||||||
}
|
}
|
||||||
|
@ -47,9 +47,10 @@ Thumb1RegisterInfo::Thumb1RegisterInfo(const TargetInstrInfo &tii,
|
||||||
/// specified immediate.
|
/// specified immediate.
|
||||||
void Thumb1RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
|
void Thumb1RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator &MBBI,
|
MachineBasicBlock::iterator &MBBI,
|
||||||
|
const TargetInstrInfo *TII, DebugLoc dl,
|
||||||
unsigned DestReg, int Val,
|
unsigned DestReg, int Val,
|
||||||
const TargetInstrInfo *TII,
|
ARMCC::CondCodes Pred,
|
||||||
DebugLoc dl) const {
|
unsigned PredReg) const {
|
||||||
MachineFunction &MF = *MBB.getParent();
|
MachineFunction &MF = *MBB.getParent();
|
||||||
MachineConstantPool *ConstantPool = MF.getConstantPool();
|
MachineConstantPool *ConstantPool = MF.getConstantPool();
|
||||||
Constant *C = ConstantInt::get(Type::Int32Ty, Val);
|
Constant *C = ConstantInt::get(Type::Int32Ty, Val);
|
||||||
|
@ -130,7 +131,7 @@ void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
|
||||||
BuildMI(MBB, MBBI, dl, TII.get(ARM::tNEG), LdReg)
|
BuildMI(MBB, MBBI, dl, TII.get(ARM::tNEG), LdReg)
|
||||||
.addReg(LdReg, RegState::Kill);
|
.addReg(LdReg, RegState::Kill);
|
||||||
} else
|
} else
|
||||||
MRI.emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, &TII, dl);
|
MRI.emitLoadConstPool(MBB, MBBI, &TII, dl, LdReg, NumBytes);
|
||||||
|
|
||||||
// Emit add / sub.
|
// Emit add / sub.
|
||||||
int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
|
int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
|
||||||
|
@ -504,7 +505,7 @@ void Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||||
emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
|
emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
|
||||||
Offset, false, TII, *this, dl);
|
Offset, false, TII, *this, dl);
|
||||||
else {
|
else {
|
||||||
emitLoadConstPool(MBB, II, TmpReg, Offset, &TII, dl);
|
emitLoadConstPool(MBB, II, &TII, dl, TmpReg, Offset);
|
||||||
UseRR = true;
|
UseRR = true;
|
||||||
}
|
}
|
||||||
} else
|
} else
|
||||||
|
@ -542,7 +543,7 @@ void Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||||
emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
|
emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
|
||||||
Offset, false, TII, *this, dl);
|
Offset, false, TII, *this, dl);
|
||||||
else {
|
else {
|
||||||
emitLoadConstPool(MBB, II, TmpReg, Offset, &TII, dl);
|
emitLoadConstPool(MBB, II, &TII, dl, TmpReg, Offset);
|
||||||
UseRR = true;
|
UseRR = true;
|
||||||
}
|
}
|
||||||
} else
|
} else
|
||||||
|
|
|
@ -20,27 +20,26 @@
|
||||||
|
|
||||||
namespace llvm {
|
namespace llvm {
|
||||||
class ARMSubtarget;
|
class ARMSubtarget;
|
||||||
class TargetInstrInfo;
|
class ARMBaseInstrInfo;
|
||||||
class Type;
|
class Type;
|
||||||
|
|
||||||
struct Thumb1RegisterInfo : public ARMBaseRegisterInfo {
|
struct Thumb1RegisterInfo : public ARMBaseRegisterInfo {
|
||||||
public:
|
public:
|
||||||
Thumb1RegisterInfo(const TargetInstrInfo &tii, const ARMSubtarget &STI);
|
Thumb1RegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI);
|
||||||
|
|
||||||
/// emitLoadConstPool - Emits a load from constpool to materialize the
|
/// emitLoadConstPool - Emits a load from constpool to materialize the
|
||||||
/// specified immediate.
|
/// specified immediate.
|
||||||
void emitLoadConstPool(MachineBasicBlock &MBB,
|
void emitLoadConstPool(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator &MBBI,
|
MachineBasicBlock::iterator &MBBI,
|
||||||
unsigned DestReg, int Val,
|
const TargetInstrInfo *TII, DebugLoc dl,
|
||||||
const TargetInstrInfo *TII,
|
unsigned DestReg, int Val,
|
||||||
DebugLoc dl) const;
|
ARMCC::CondCodes Pred = ARMCC::AL,
|
||||||
|
unsigned PredReg = 0) const;
|
||||||
|
|
||||||
/// Code Generation virtual methods...
|
/// Code Generation virtual methods...
|
||||||
const TargetRegisterClass *
|
const TargetRegisterClass *
|
||||||
getPhysicalRegisterRegClass(unsigned Reg, MVT VT = MVT::Other) const;
|
getPhysicalRegisterRegClass(unsigned Reg, MVT VT = MVT::Other) const;
|
||||||
|
|
||||||
bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
|
|
||||||
|
|
||||||
bool requiresRegisterScavenging(const MachineFunction &MF) const;
|
bool requiresRegisterScavenging(const MachineFunction &MF) const;
|
||||||
|
|
||||||
bool hasReservedCallFrame(MachineFunction &MF) const;
|
bool hasReservedCallFrame(MachineFunction &MF) const;
|
||||||
|
|
|
@ -38,7 +38,7 @@ Thumb2RegScavenging("enable-thumb2-reg-scavenging",
|
||||||
cl::Hidden,
|
cl::Hidden,
|
||||||
cl::desc("Enable register scavenging on Thumb-2"));
|
cl::desc("Enable register scavenging on Thumb-2"));
|
||||||
|
|
||||||
Thumb2RegisterInfo::Thumb2RegisterInfo(const TargetInstrInfo &tii,
|
Thumb2RegisterInfo::Thumb2RegisterInfo(const ARMBaseInstrInfo &tii,
|
||||||
const ARMSubtarget &sti)
|
const ARMSubtarget &sti)
|
||||||
: ARMBaseRegisterInfo(tii, sti) {
|
: ARMBaseRegisterInfo(tii, sti) {
|
||||||
}
|
}
|
||||||
|
@ -47,9 +47,10 @@ Thumb2RegisterInfo::Thumb2RegisterInfo(const TargetInstrInfo &tii,
|
||||||
/// specified immediate.
|
/// specified immediate.
|
||||||
void Thumb2RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
|
void Thumb2RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator &MBBI,
|
MachineBasicBlock::iterator &MBBI,
|
||||||
|
const TargetInstrInfo *TII, DebugLoc dl,
|
||||||
unsigned DestReg, int Val,
|
unsigned DestReg, int Val,
|
||||||
const TargetInstrInfo *TII,
|
ARMCC::CondCodes Pred,
|
||||||
DebugLoc dl) const {
|
unsigned PredReg) const {
|
||||||
MachineFunction &MF = *MBB.getParent();
|
MachineFunction &MF = *MBB.getParent();
|
||||||
MachineConstantPool *ConstantPool = MF.getConstantPool();
|
MachineConstantPool *ConstantPool = MF.getConstantPool();
|
||||||
Constant *C = ConstantInt::get(Type::Int32Ty, Val);
|
Constant *C = ConstantInt::get(Type::Int32Ty, Val);
|
||||||
|
@ -130,7 +131,7 @@ void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
|
||||||
BuildMI(MBB, MBBI, dl, TII.get(ARM::tNEG), LdReg)
|
BuildMI(MBB, MBBI, dl, TII.get(ARM::tNEG), LdReg)
|
||||||
.addReg(LdReg, RegState::Kill);
|
.addReg(LdReg, RegState::Kill);
|
||||||
} else
|
} else
|
||||||
MRI.emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, &TII, dl);
|
MRI.emitLoadConstPool(MBB, MBBI, &TII, dl, LdReg, NumBytes);
|
||||||
|
|
||||||
// Emit add / sub.
|
// Emit add / sub.
|
||||||
int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
|
int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
|
||||||
|
@ -504,7 +505,7 @@ void Thumb2RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||||
emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
|
emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
|
||||||
Offset, false, TII, *this, dl);
|
Offset, false, TII, *this, dl);
|
||||||
else {
|
else {
|
||||||
emitLoadConstPool(MBB, II, TmpReg, Offset, &TII, dl);
|
emitLoadConstPool(MBB, II, &TII, dl, TmpReg, Offset);
|
||||||
UseRR = true;
|
UseRR = true;
|
||||||
}
|
}
|
||||||
} else
|
} else
|
||||||
|
@ -542,7 +543,7 @@ void Thumb2RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||||
emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
|
emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
|
||||||
Offset, false, TII, *this, dl);
|
Offset, false, TII, *this, dl);
|
||||||
else {
|
else {
|
||||||
emitLoadConstPool(MBB, II, TmpReg, Offset, &TII, dl);
|
emitLoadConstPool(MBB, II, &TII, dl, TmpReg, Offset);
|
||||||
UseRR = true;
|
UseRR = true;
|
||||||
}
|
}
|
||||||
} else
|
} else
|
||||||
|
|
|
@ -20,27 +20,26 @@
|
||||||
|
|
||||||
namespace llvm {
|
namespace llvm {
|
||||||
class ARMSubtarget;
|
class ARMSubtarget;
|
||||||
class TargetInstrInfo;
|
class ARMBaseInstrInfo;
|
||||||
class Type;
|
class Type;
|
||||||
|
|
||||||
struct Thumb2RegisterInfo : public ARMBaseRegisterInfo {
|
struct Thumb2RegisterInfo : public ARMBaseRegisterInfo {
|
||||||
public:
|
public:
|
||||||
Thumb2RegisterInfo(const TargetInstrInfo &tii, const ARMSubtarget &STI);
|
Thumb2RegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI);
|
||||||
|
|
||||||
/// emitLoadConstPool - Emits a load from constpool to materialize the
|
/// emitLoadConstPool - Emits a load from constpool to materialize the
|
||||||
/// specified immediate.
|
/// specified immediate.
|
||||||
void emitLoadConstPool(MachineBasicBlock &MBB,
|
void emitLoadConstPool(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator &MBBI,
|
MachineBasicBlock::iterator &MBBI,
|
||||||
unsigned DestReg, int Val,
|
const TargetInstrInfo *TII, DebugLoc dl,
|
||||||
const TargetInstrInfo *TII,
|
unsigned DestReg, int Val,
|
||||||
DebugLoc dl) const;
|
ARMCC::CondCodes Pred = ARMCC::AL,
|
||||||
|
unsigned PredReg = 0) const;
|
||||||
|
|
||||||
/// Code Generation virtual methods...
|
/// Code Generation virtual methods...
|
||||||
const TargetRegisterClass *
|
const TargetRegisterClass *
|
||||||
getPhysicalRegisterRegClass(unsigned Reg, MVT VT = MVT::Other) const;
|
getPhysicalRegisterRegClass(unsigned Reg, MVT VT = MVT::Other) const;
|
||||||
|
|
||||||
bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
|
|
||||||
|
|
||||||
bool requiresRegisterScavenging(const MachineFunction &MF) const;
|
bool requiresRegisterScavenging(const MachineFunction &MF) const;
|
||||||
|
|
||||||
bool hasReservedCallFrame(MachineFunction &MF) const;
|
bool hasReservedCallFrame(MachineFunction &MF) const;
|
||||||
|
|
Loading…
Reference in New Issue