replica
/
hanchenye-llvm-project
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Hexagon: Fix a nasty order-of-initialization bug. 

Reenable the tests.

llvm-svn: 146750
This commit is contained in:
Benjamin Kramer 2011-12-16 19:08:59 +00:00
parent f6f003af6a
commit 9ca2e7293b
12 changed files with 12 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
View File

@ -56,7 +56,7 @@ HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT,
CodeGenOpt::Level OL) CodeGenOpt::Level OL)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
DataLayout("e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-a0:0") , DataLayout("e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-a0:0") ,
Subtarget(TT, CPU, FS), TLInfo(*this), InstrInfo(Subtarget), Subtarget(TT, CPU, FS), InstrInfo(Subtarget), TLInfo(*this),
TSInfo(*this), TSInfo(*this),
FrameLowering(Subtarget), FrameLowering(Subtarget),
InstrItins(&Subtarget.getInstrItineraryData()) { InstrItins(&Subtarget.getInstrItineraryData()) {

2
llvm/lib/Target/Hexagon/HexagonTargetMachine.h
View File

@ -29,8 +29,8 @@ class Module;
class HexagonTargetMachine : public LLVMTargetMachine { class HexagonTargetMachine : public LLVMTargetMachine {
const TargetData DataLayout; // Calculates type size & alignment. const TargetData DataLayout; // Calculates type size & alignment.
HexagonSubtarget Subtarget; HexagonSubtarget Subtarget;
HexagonTargetLowering TLInfo;
HexagonInstrInfo InstrInfo; HexagonInstrInfo InstrInfo;
HexagonTargetLowering TLInfo;
HexagonSelectionDAGInfo TSInfo; HexagonSelectionDAGInfo TSInfo;
HexagonFrameLowering FrameLowering; HexagonFrameLowering FrameLowering;
const InstrItineraryData* InstrItins; const InstrItineraryData* InstrItins;

3
llvm/test/CodeGen/Hexagon/args.ll
View File

@ -1,5 +1,4 @@
; RUN: true ; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
; DISABLED: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
; CHECK: r[[T0:[0-9]+]] = #7 ; CHECK: r[[T0:[0-9]+]] = #7
; CHECK: memw(r29 + #0) = r[[T0]] ; CHECK: memw(r29 + #0) = r[[T0]]
; CHECK: r0 = #1 ; CHECK: r0 = #1

3
llvm/test/CodeGen/Hexagon/combine.ll
View File

@ -1,5 +1,4 @@
; RUN: true ; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
; DISABLED: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
; CHECK: combine(r{{[0-9]+}}, r{{[0-9]+}}) ; CHECK: combine(r{{[0-9]+}}, r{{[0-9]+}})
@j = external global i32 @j = external global i32

3
llvm/test/CodeGen/Hexagon/double.ll
View File

@ -1,5 +1,4 @@
; RUN: true ; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
; DISABLED: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
; CHECK: __hexagon_adddf3 ; CHECK: __hexagon_adddf3
; CHECK: __hexagon_subdf3 ; CHECK: __hexagon_subdf3

3
llvm/test/CodeGen/Hexagon/float.ll
View File

@ -1,5 +1,4 @@
; RUN: true ; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
; DISABLED: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
; CHECK: __hexagon_addsf3 ; CHECK: __hexagon_addsf3
; CHECK: __hexagon_subsf3 ; CHECK: __hexagon_subsf3

3
llvm/test/CodeGen/Hexagon/frame.ll
View File

@ -1,5 +1,4 @@
; RUN: true ; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
; DISABLED: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
@num = external global i32 @num = external global i32
@acc = external global i32 @acc = external global i32

3
llvm/test/CodeGen/Hexagon/mpy.ll
View File

@ -1,5 +1,4 @@
; RUN: true ; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
; DISABLED: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
; CHECK: += mpyi ; CHECK: += mpyi
define void @foo(i32 %acc, i32 %num, i32 %num2) nounwind { define void @foo(i32 %acc, i32 %num, i32 %num2) nounwind {

3
llvm/test/CodeGen/Hexagon/static.ll
View File

@ -1,5 +1,4 @@
; RUN: true ; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
; DISABLED: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
@num = external global i32 @num = external global i32
@acc = external global i32 @acc = external global i32

3
llvm/test/CodeGen/Hexagon/struct_args.ll
View File

@ -1,5 +1,4 @@
; RUN: true ; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
; DISABLED: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
; CHECK: r1:0 = or(r{{[0-9]}}:{{[0-9]}}, r{{[0-9]}}:{{[0-9]}}) ; CHECK: r1:0 = or(r{{[0-9]}}:{{[0-9]}}, r{{[0-9]}}:{{[0-9]}})
%struct.small = type { i32, i32 } %struct.small = type { i32, i32 }

3
llvm/test/CodeGen/Hexagon/struct_args_large.ll
View File

@ -1,5 +1,4 @@
; RUN: true ; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
; DISABLED: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
; CHECK: r[[T0:[0-9]+]] = CONST32(#s2) ; CHECK: r[[T0:[0-9]+]] = CONST32(#s2)
; CHECK: r[[T1:[0-9]+]] = memw(r[[T0]] + #0) ; CHECK: r[[T1:[0-9]+]] = memw(r[[T0]] + #0)
; CHECK: memw(r29 + #0) = r[[T1]] ; CHECK: memw(r29 + #0) = r[[T1]]

3
llvm/test/CodeGen/Hexagon/vaddh.ll
View File

@ -1,5 +1,4 @@
; RUN: true ; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
; DISABLED: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
; CHECK: vaddh(r{{[0-9]+}}, r{{[0-9]+}}) ; CHECK: vaddh(r{{[0-9]+}}, r{{[0-9]+}})
@j = external global i32 @j = external global i32