replica
/
hanchenye-llvm-project
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

isel (i32 anyext i16) as insert_subreg when 16-bit ops are being promoted. 

llvm-svn: 101979
This commit is contained in:
Evan Cheng 2010-04-21 01:47:12 +00:00
parent 873310f635
commit 9c8cd8c061
5 changed files with 30 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -64,9 +64,6 @@ DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
static cl::opt<bool>
Disable16Bit("disable-16bit", cl::Hidden,
cl::desc("Disable use of 16-bit instructions"));
static cl::opt<bool>
Promote16Bit("promote-16bit", cl::Hidden,
cl::desc("Promote 16-bit instructions"));
// Forward declarations.
static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
@ -6016,7 +6013,7 @@ SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
}
// Otherwise just emit a CMP with 0, which is the TEST pattern.
if (Promote16Bit && Op.getValueType() == MVT::i16)
if (Subtarget->shouldPromote16Bit() && Op.getValueType() == MVT::i16)
Op = DAG.getNode(ISD::ANY_EXTEND, Op.getDebugLoc(), MVT::i32, Op);
return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
DAG.getConstant(0, Op.getValueType()));
@ -6031,7 +6028,7 @@ SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
return EmitTest(Op0, X86CC, DAG);
DebugLoc dl = Op0.getDebugLoc();
if (Promote16Bit && Op0.getValueType() == MVT::i16) {
if (Subtarget->shouldPromote16Bit() && Op0.getValueType() == MVT::i16) {
Op0 = DAG.getNode(ISD::ANY_EXTEND, Op0.getDebugLoc(), MVT::i32, Op0);
Op1 = DAG.getNode(ISD::ANY_EXTEND, Op1.getDebugLoc(), MVT::i32, Op1);
}
@ -6040,8 +6037,8 @@ SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
/// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
/// if it's possible.
static SDValue LowerToBT(SDValue And, ISD::CondCode CC,
DebugLoc dl, SelectionDAG &DAG) {
SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
DebugLoc dl, SelectionDAG &DAG) const {
SDValue Op0 = And.getOperand(0);
SDValue Op1 = And.getOperand(1);
if (Op0.getOpcode() == ISD::TRUNCATE)
@ -6078,7 +6075,7 @@ static SDValue LowerToBT(SDValue And, ISD::CondCode CC,
// the encoding for the i16 version is larger than the i32 version.
// Also promote i16 to i32 for performance / code size reason.
if (LHS.getValueType() == MVT::i8 ||
(Promote16Bit && LHS.getValueType() == MVT::i16))
(Subtarget->shouldPromote16Bit() && LHS.getValueType() == MVT::i16))
LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
// If the operand types disagree, extend the shift amount to match. Since
@ -9960,7 +9957,7 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
if (!isTypeLegal(VT))
return false;
if (!Promote16Bit || VT != MVT::i16)
if (!Subtarget->shouldPromote16Bit() || VT != MVT::i16)
return true;
switch (Opc) {
@ -9989,7 +9986,7 @@ bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
/// beneficial for dag combiner to promote the specified node. If true, it
/// should return the desired promotion type by reference.
bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
if (!Promote16Bit)
if (!Subtarget->shouldPromote16Bit())
return false;
EVT VT = Op.getValueType();

2
llvm/lib/Target/X86/X86ISelLowering.h
View File

@ -685,6 +685,8 @@ namespace llvm {
SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerToBT(SDValue And, ISD::CondCode CC,
DebugLoc dl, SelectionDAG &DAG) const;
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;

10
llvm/lib/Target/X86/X86InstrInfo.td
View File

@ -331,6 +331,8 @@ def OptForSpeed : Predicate<"!OptForSize">;
def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
def HasAES : Predicate<"Subtarget->hasAES()">;
def Promote16Bit : Predicate<"Subtarget->shouldPromote16Bit()">;
def NotPromote16Bit : Predicate<"!Subtarget->shouldPromote16Bit()">;
//===----------------------------------------------------------------------===//
// X86 Instruction Format Definitions.
@ -4476,7 +4478,13 @@ def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
// avoid partial-register updates.
def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>;
def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>,
Requires<[NotPromote16Bit]>;
def : Pat<(i32 (anyext GR16:$src)),
(INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>,
Requires<[Promote16Bit]>;
//===----------------------------------------------------------------------===//
// Some peepholes

6
llvm/lib/Target/X86/X86Subtarget.cpp
View File

@ -16,6 +16,7 @@
#include "X86InstrInfo.h"
#include "X86GenSubtarget.inc"
#include "llvm/GlobalValue.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/System/Host.h"
@ -24,6 +25,10 @@
#include "llvm/ADT/SmallVector.h"
using namespace llvm;
static cl::opt<bool>
DoPromote16Bit("promote-16bit", cl::Hidden,
cl::desc("Promote 16-bit instructions"));
#if defined(_MSC_VER)
#include <intrin.h>
#endif
@ -293,6 +298,7 @@ X86Subtarget::X86Subtarget(const std::string &TT, const std::string &FS,
, IsBTMemSlow(false)
, IsUAMemFast(false)
, HasVectorUAMem(false)
, Promote16Bit(DoPromote16Bit)
, DarwinVers(0)
, stackAlignment(8)
// FIXME: this is a known good value for Yonah. How about others?

8
llvm/lib/Target/X86/X86Subtarget.h
View File

@ -85,10 +85,13 @@ protected:
bool IsUAMemFast;
/// HasVectorUAMem - True if SIMD operations can have unaligned memory
/// operands. This may require setting a feature bit in the
/// processor.
/// operands. This may require setting a feature bit in the processor.
bool HasVectorUAMem;
/// Promote16Bit - True if codegen should promote 16-bit operations to 32-bit.
/// This is a temporary option.
bool Promote16Bit;
/// DarwinVers - Nonzero if this is a darwin platform: the numeric
/// version of the platform, e.g. 8 = 10.4 (Tiger), 9 = 10.5 (Leopard), etc.
unsigned char DarwinVers; // Is any darwin-x86 platform.
@ -157,6 +160,7 @@ public:
bool isBTMemSlow() const { return IsBTMemSlow; }
bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
bool hasVectorUAMem() const { return HasVectorUAMem; }
bool shouldPromote16Bit() const { return Promote16Bit; }
bool isTargetDarwin() const { return TargetType == isDarwin; }
bool isTargetELF() const { return TargetType == isELF; }