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[X86] Reduce number of OpPrefix bits in TSFlags to 2. NFCI 

TSFlag doesn't need to disambiguate NoPrfx from PS. So shift the encodings so PS is NoPrfx|0x4.

llvm-svn: 329049
This commit is contained in:
Craig Topper 2018-04-03 06:37:04 +00:00
parent 7d522b6eee
commit 9b6a65b9ef
4 changed files with 38 additions and 34 deletions
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12
llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
View File

@ -397,21 +397,21 @@ namespace X86II {
// no prefix.
//
OpPrefixShift = AdSizeShift + 2,
OpPrefixMask = 0x7 << OpPrefixShift,
OpPrefixMask = 0x3 << OpPrefixShift,
// PS, PD - Prefix code for packed single and double precision vector
// floating point operations performed in the SSE registers.
PS = 1 << OpPrefixShift, PD = 2 << OpPrefixShift,
// PD - Prefix code for packed double precision vector floating point
// operations performed in the SSE registers.
PD = 1 << OpPrefixShift,
// XS, XD - These prefix codes are for single and double precision scalar
// floating point operations performed in the SSE registers.
XS = 3 << OpPrefixShift, XD = 4 << OpPrefixShift,
XS = 2 << OpPrefixShift, XD = 3 << OpPrefixShift,
//===------------------------------------------------------------------===//
// OpMap - This field determines which opcode map this instruction
// belongs to. i.e. one-byte, two-byte, 0x0f 0x38, 0x0f 0x3a, etc.
//
OpMapShift = OpPrefixShift + 3,
OpMapShift = OpPrefixShift + 2,
OpMapMask = 0x7 << OpMapShift,
// OB - OneByte - Set if this instruction has a one byte opcode.

4
llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
View File

@ -700,10 +700,8 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
// 0b10: F3
// 0b11: F2
//
uint8_t VEX_PP;
uint8_t VEX_PP = 0;
switch (TSFlags & X86II::OpPrefixMask) {
default: llvm_unreachable("Invalid op prefix!");
case X86II::PS: VEX_PP = 0x0; break; // none
case X86II::PD: VEX_PP = 0x1; break; // 66
case X86II::XS: VEX_PP = 0x2; break; // F3
case X86II::XD: VEX_PP = 0x3; break; // F2

54
llvm/lib/Target/X86/X86InstrFormats.td
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@ -127,10 +127,15 @@ class Prefix<bits<3> val> {
bits<3> Value = val;
}
def NoPrfx : Prefix<0>;
def PS : Prefix<1>;
def PD : Prefix<2>;
def XS : Prefix<3>;
def XD : Prefix<4>;
def PD : Prefix<1>;
def XS : Prefix<2>;
def XD : Prefix<3>;
def PS : Prefix<4>; // Similar to NoPrfx, but disassembler uses this to know
// that other instructions with this opcode use PD/XS/XD
// and if any of those is not supported they shouldn't
// decode to this instruction. e.g. ANDSS/ANDSD don't
// exist, but the 0xf2/0xf3 encoding shouldn't
// disable to ANDPS.
// Class specifying the opcode map.
class Map<bits<3> val> {
@ -327,28 +332,29 @@ class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
let TSFlags{6-0} = FormBits;
let TSFlags{8-7} = OpSizeBits;
let TSFlags{10-9} = AdSizeBits;
let TSFlags{13-11} = OpPrefixBits;
let TSFlags{16-14} = OpMapBits;
let TSFlags{17} = hasREX_WPrefix;
let TSFlags{21-18} = ImmT.Value;
let TSFlags{24-22} = FPForm.Value;
let TSFlags{25} = hasLockPrefix;
let TSFlags{26} = hasREPPrefix;
let TSFlags{28-27} = ExeDomain.Value;
let TSFlags{30-29} = OpEncBits;
let TSFlags{38-31} = Opcode;
// No need for 3rd bit, we don't need to distinguish NoPrfx from PS.
let TSFlags{12-11} = OpPrefixBits{1-0};
let TSFlags{15-13} = OpMapBits;
let TSFlags{16} = hasREX_WPrefix;
let TSFlags{20-17} = ImmT.Value;
let TSFlags{23-21} = FPForm.Value;
let TSFlags{24} = hasLockPrefix;
let TSFlags{25} = hasREPPrefix;
let TSFlags{27-26} = ExeDomain.Value;
let TSFlags{29-28} = OpEncBits;
let TSFlags{37-30} = Opcode;
// Currently no need for second bit in TSFlags - W Ignore is equivalent to 0.
let TSFlags{39} = VEX_WPrefix{0};
let TSFlags{40} = hasVEX_4V;
let TSFlags{41} = hasVEX_L;
let TSFlags{42} = hasEVEX_K;
let TSFlags{43} = hasEVEX_Z;
let TSFlags{44} = hasEVEX_L2;
let TSFlags{45} = hasEVEX_B;
let TSFlags{38} = VEX_WPrefix{0};
let TSFlags{39} = hasVEX_4V;
let TSFlags{40} = hasVEX_L;
let TSFlags{41} = hasEVEX_K;
let TSFlags{42} = hasEVEX_Z;
let TSFlags{43} = hasEVEX_L2;
let TSFlags{44} = hasEVEX_B;
// If we run out of TSFlags bits, it's possible to encode this in 3 bits.
let TSFlags{52-46} = CD8_Scale;
let TSFlags{53} = hasEVEX_RC;
let TSFlags{54} = hasNoTrackPrefix;
let TSFlags{51-45} = CD8_Scale;
let TSFlags{52} = hasEVEX_RC;
let TSFlags{53} = hasNoTrackPrefix;
}
class PseudoI<dag oops, dag iops, list<dag> pattern,

2
llvm/utils/TableGen/X86RecognizableInstr.h
View File

@ -126,7 +126,7 @@ namespace X86Local {
};
enum {
PS = 1, PD = 2, XS = 3, XD = 4
PD = 1, XS = 2, XD = 3, PS = 4
};
enum {