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Fixed issue with microMIPS JAL instruction. 

Differential Revision: http://llvm-reviews.chandlerc.com/D3200

llvm-svn: 205185
This commit is contained in:
Zoran Jovanovic 2014-03-31 14:00:10 +00:00
parent ff127bff89
commit 9b05a31f76
5 changed files with 52 additions and 15 deletions
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7
llvm/lib/Target/Mips/MicroMipsInstrInfo.td
View File

@ -78,15 +78,10 @@ class MoveMM16<string opstr, RegisterOperand RO, bit isComm = 0,
let isReMaterializable = 1;
}
// MicroMIPS Call
def MicroMipsJmpLink : SDNode<"MipsISD::JmpLinkMM",SDT_MipsJmpLink,
[SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
SDNPVariadic]>;
// 16-bit Jump and Link (Call)
class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
[(MicroMipsJmpLink RO:$rs)], IIBranch, FrmR> {
[(MipsJmpLink RO:$rs)], IIBranch, FrmR> {
let isCall = 1;
let hasDelaySlot = 1;
let Defs = [RA];

5
llvm/lib/Target/Mips/MipsISelLowering.cpp
View File

@ -115,7 +115,6 @@ SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty,
const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
switch (Opcode) {
case MipsISD::JmpLink: return "MipsISD::JmpLink";
case MipsISD::JmpLinkMM: return "MipsISD::JmpLinkMM";
case MipsISD::TailCall: return "MipsISD::TailCall";
case MipsISD::Hi: return "MipsISD::Hi";
case MipsISD::Lo: return "MipsISD::Lo";
@ -2546,9 +2545,7 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
if (IsTailCall)
return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, &Ops[0], Ops.size());
MipsISD::NodeType JmpLink = isMicroMips ? MipsISD::JmpLinkMM
: MipsISD::JmpLink;
Chain = DAG.getNode(JmpLink, DL, NodeTys, &Ops[0], Ops.size());
Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, &Ops[0], Ops.size());
SDValue InFlag = Chain.getValue(1);
// Create the CALLSEQ_END node.

3
llvm/lib/Target/Mips/MipsISelLowering.h
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@ -34,9 +34,6 @@ namespace llvm {
// Jump and link (call)
JmpLink,
// MicroMIPS Jump and link (call)
JmpLinkMM,
// Tail call
TailCall,

4
llvm/lib/Target/Mips/MipsInstrInfo.td
View File

@ -1044,11 +1044,11 @@ def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
def B : UncondBranch<BEQ>;
def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
let Predicates = [NotInMicroMips] in {
let Predicates = [NotInMicroMips, HasStdEnc] in {
def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
}
def JALX : JumpLink<"jalx", calltarget>, FJ<0x1D>;
def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>;
def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>;
def BAL_BR : BAL_BR_Pseudo<BGEZAL>;

48
llvm/test/CodeGen/Mips/micromips-jal.ll Normal file
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@ -0,0 +1,48 @@
; RUN: llc %s -march=mipsel -mcpu=mips32r2 -mattr=micromips -filetype=asm \
; RUN: -relocation-model=static -o - | FileCheck %s
define i32 @sum(i32 %a, i32 %b) nounwind uwtable {
entry:
%a.addr = alloca i32, align 4
%b.addr = alloca i32, align 4
store i32 %a, i32* %a.addr, align 4
store i32 %b, i32* %b.addr, align 4
%0 = load i32* %a.addr, align 4
%1 = load i32* %b.addr, align 4
%add = add nsw i32 %0, %1
ret i32 %add
}
define i32 @main() nounwind uwtable {
entry:
%retval = alloca i32, align 4
%x = alloca i32, align 4
%y = alloca i32, align 4
%z = alloca i32, align 4
store i32 0, i32* %retval
%0 = load i32* %y, align 4
%1 = load i32* %z, align 4
%call = call i32 @sum(i32 %0, i32 %1)
store i32 %call, i32* %x, align 4
%2 = load i32* %x, align 4
ret i32 %2
}
; CHECK: .text
; CHECK: .globl sum
; CHECK: .type sum,@function
; CHECK: .set micromips
; CHECK: .ent sum
; CHECK-LABEL: sum:
; CHECK: .end sum
; CHECK: .globl main
; CHECK: .type main,@function
; CHECK: .set micromips
; CHECK: .ent main
; CHECK-LABEL: main:
; CHECK: jal sum
; CHECK: .end main