From 9a4d42855d2f21239332e69ecb3cfdd1524b9738 Mon Sep 17 00:00:00 2001 From: Owen Anderson Date: Mon, 13 Dec 2010 22:51:08 +0000 Subject: [PATCH] Revert r121721, which broke buildbots. llvm-svn: 121726 --- llvm/lib/Target/ARM/ARMAsmBackend.cpp | 20 --------- llvm/lib/Target/ARM/ARMCodeEmitter.cpp | 2 - llvm/lib/Target/ARM/ARMConstantIslandPass.cpp | 10 ++--- llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp | 15 ------- llvm/lib/Target/ARM/ARMFixupKinds.h | 3 -- llvm/lib/Target/ARM/ARMInstrThumb2.td | 41 ++++++++----------- llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp | 15 ------- llvm/utils/TableGen/EDEmitter.cpp | 1 - 8 files changed, 21 insertions(+), 86 deletions(-) diff --git a/llvm/lib/Target/ARM/ARMAsmBackend.cpp b/llvm/lib/Target/ARM/ARMAsmBackend.cpp index 789bae09bee1..cb0c54386ed6 100644 --- a/llvm/lib/Target/ARM/ARMAsmBackend.cpp +++ b/llvm/lib/Target/ARM/ARMAsmBackend.cpp @@ -136,25 +136,6 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) { // Encode the immediate and shift the opcode into place. return ARM_AM::getSOImmVal(Value) | (opc << 21); } - - case ARM::fixup_t2_adr_pcrel_12: { - Value -= 4; - unsigned opc = 0; - if ((int64_t)Value < 0) { - Value = -Value; - opc = 5; - } - - uint32_t out = (opc << 21); - out |= (Value & 0x800) << 14; - out |= (Value & 0x700) << 4; - out |= (Value & 0x0FF); - - uint64_t swapped = (out & 0xFFFF0000) >> 16; - swapped |= (out & 0x0000FFFF) << 16; - return swapped; - } - case ARM::fixup_arm_branch: // These values don't encode the low two bits since they're always zero. // Offset by 8 just as above. @@ -375,7 +356,6 @@ static unsigned getFixupKindNumBytes(unsigned Kind) { case ARM::fixup_t2_condbranch: case ARM::fixup_t2_uncondbranch: case ARM::fixup_t2_pcrel_10: - case ARM::fixup_t2_adr_pcrel_12: case ARM::fixup_arm_thumb_bl: case ARM::fixup_arm_thumb_blx: return 4; diff --git a/llvm/lib/Target/ARM/ARMCodeEmitter.cpp b/llvm/lib/Target/ARM/ARMCodeEmitter.cpp index 5e302ae28136..101c07b4db62 100644 --- a/llvm/lib/Target/ARM/ARMCodeEmitter.cpp +++ b/llvm/lib/Target/ARM/ARMCodeEmitter.cpp @@ -213,8 +213,6 @@ namespace { const { return 0; } unsigned getImmMinusOneOpValue(const MachineInstr &MI, unsigned Op) const { return 0; } - unsigned getT2AdrLabelOpValue(const MachineInstr &MI, unsigned Op) - const { return 0; } unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op) const { return 0; } unsigned getAddrMode6DupAddressOpValue(const MachineInstr &MI, unsigned Op) diff --git a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp index 9434ecf40bdc..8066cb735b13 100644 --- a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp +++ b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp @@ -594,7 +594,7 @@ void ARMConstantIslands::InitialFunctionScan(MachineFunction &MF, NegOk = true; IsSoImm = true; break; - case ARM::t2ADR: + case ARM::t2LEApcrel: Bits = 12; NegOk = true; break; @@ -1555,7 +1555,7 @@ bool ARMConstantIslands::OptimizeThumb2Instructions(MachineFunction &MF) { unsigned Bits = 0; switch (Opcode) { default: break; - case ARM::t2ADR: + case ARM::t2LEApcrel: if (isARMLowRegister(U.MI->getOperand(0).getReg())) { NewOpc = ARM::tLEApcrel; Bits = 8; @@ -1754,16 +1754,16 @@ bool ARMConstantIslands::OptimizeThumb2JumpTables(MachineFunction &MF) { if (!OptOk) continue; - // Now scan back again to find the tLEApcrel or t2ADR instruction + // Now scan back again to find the tLEApcrel or t2LEApcrelJT instruction // that gave us the initial base register definition. for (--PrevI; PrevI != B && !PrevI->definesRegister(BaseReg); --PrevI) ; - // The instruction should be a tLEApcrel or t2ADR; we want + // The instruction should be a tLEApcrel or t2LEApcrelJT; we want // to delete it as well. MachineInstr *LeaMI = PrevI; if ((LeaMI->getOpcode() != ARM::tLEApcrelJT && - LeaMI->getOpcode() != ARM::t2ADR) || + LeaMI->getOpcode() != ARM::t2LEApcrelJT) || LeaMI->getOperand(0).getReg() != BaseReg) OptOk = false; diff --git a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp index 109ec0c4478e..2714dd256db8 100644 --- a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp +++ b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp @@ -763,21 +763,6 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) { break; } - case ARM::t2LEApcrel: - case ARM::t2LEApcrelJT: { - bool DstIsDead = MI.getOperand(0).isDead(); - MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), - TII->get(ARM::t2ADR)) - .addReg(MI.getOperand(0).getReg(), - RegState::Define | getDeadRegState(DstIsDead)) // Dst reg - .addOperand(MI.getOperand(1)) // Label - .addOperand(MI.getOperand(2)) // Pred - .addOperand(MI.getOperand(3)); - TransferImpOps(MI, MIB, MIB); - MI.eraseFromParent(); - return MIB; - } - case ARM::MOVi32imm: case ARM::MOVCCi32imm: case ARM::t2MOVi32imm: diff --git a/llvm/lib/Target/ARM/ARMFixupKinds.h b/llvm/lib/Target/ARM/ARMFixupKinds.h index f535608d89a5..48d495396e22 100644 --- a/llvm/lib/Target/ARM/ARMFixupKinds.h +++ b/llvm/lib/Target/ARM/ARMFixupKinds.h @@ -33,9 +33,6 @@ enum Fixups { // fixup_arm_adr_pcrel_12 - 12-bit PC relative relocation for the ADR // instruction. fixup_arm_adr_pcrel_12, - // fixup_t2_adr_pcrel_12 - 12-bit PC relative relocation for the ADR - // instruction. - fixup_t2_adr_pcrel_12, // fixup_arm_branch - 24-bit PC relative relocation for direct branch // instructions. fixup_arm_branch, diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td index 30d94e4205f9..2fedb5398ebc 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb2.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td @@ -131,12 +131,6 @@ def t2addrmode_imm12 : Operand, let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); } -// ADR instruction labels. -def t2adrlabel : Operand { - let EncoderMethod = "getT2AdrLabelOpValue"; -} - - // t2addrmode_imm8 := reg +/- imm8 def t2addrmode_imm8 : Operand, ComplexPattern { @@ -1134,11 +1128,10 @@ class T2PCOneRegImm { +let neverHasSideEffects = 1 in { +let isReMaterializable = 1 in +def t2LEApcrel : T2PCOneRegImm<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p), IIC_iALUi, + "adr${p}.w\t$Rd, #$label", []> { let Inst{31-27} = 0b11110; let Inst{25-24} = 0b10; // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE) @@ -1146,22 +1139,20 @@ def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd), let Inst{20} = 0; let Inst{19-16} = 0b1111; // Rn let Inst{15} = 0; - - bits<4> Rd; - bits<13> addr; - let Inst{11-8} = Rd; - let Inst{23} = addr{12}; - let Inst{21} = addr{12}; - let Inst{26} = addr{11}; - let Inst{14-12} = addr{10-8}; - let Inst{7-0} = addr{7-0}; -} -def t2LEApcrel : PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p), - IIC_iALUi, []>; -def t2LEApcrelJT : PseudoInst<(outs rGPR:$Rd), + +} +} // neverHasSideEffects +def t2LEApcrelJT : T2PCOneRegImm<(outs rGPR:$Rd), (ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi, - []>; + "adr${p}.w\t$Rd, #${label}_${id}", []> { + let Inst{31-27} = 0b11110; + let Inst{25-24} = 0b10; + // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE) + let Inst{22} = 0; + let Inst{20} = 0; + let Inst{19-16} = 0b1111; // Rn + let Inst{15} = 0; } diff --git a/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp index 8dca2c35c65b..7f34ee96e379 100644 --- a/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp +++ b/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp @@ -56,8 +56,6 @@ public: { "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_IsAligned}, { "fixup_arm_adr_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel }, -{ "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel | - MCFixupKindInfo::FKF_IsAligned}, { "fixup_arm_branch", 1, 24, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, @@ -135,9 +133,6 @@ public: /// ADR label target. uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl &Fixups) const; - uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const; - /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' /// operand. @@ -549,16 +544,6 @@ getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, Fixups); } -/// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label -/// target. -uint32_t ARMMCCodeEmitter:: -getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { - assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!"); - return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12, - Fixups); -} - /// getTAddrModeRegRegOpValue - Return encoding info for 'reg + reg' operand. uint32_t ARMMCCodeEmitter:: getTAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx, diff --git a/llvm/utils/TableGen/EDEmitter.cpp b/llvm/utils/TableGen/EDEmitter.cpp index 9c27515ec779..dede4b024464 100644 --- a/llvm/utils/TableGen/EDEmitter.cpp +++ b/llvm/utils/TableGen/EDEmitter.cpp @@ -584,7 +584,6 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type, IMM("t_imm_s4"); IMM("pclabel"); IMM("adrlabel"); - IMM("t2adrlabel"); IMM("shift_imm"); IMM("neon_vcvt_imm32");