From 9a103563f44ee06146a774458ea1f9e2a16fe231 Mon Sep 17 00:00:00 2001 From: Jyotsna Verma Date: Mon, 19 May 2014 16:22:11 +0000 Subject: [PATCH] reverting r209132 llvm-svn: 209139 --- llvm/lib/Target/Hexagon/HexagonIntrinsics.td | 364 +++++++++----- .../lib/Target/Hexagon/HexagonRegisterInfo.td | 7 +- llvm/test/CodeGen/Hexagon/intrinsics-mpy.ll | 456 ------------------ llvm/test/MC/Hexagon/mpy.s | 126 ----- 4 files changed, 250 insertions(+), 703 deletions(-) delete mode 100644 llvm/test/CodeGen/Hexagon/intrinsics-mpy.ll delete mode 100644 llvm/test/MC/Hexagon/mpy.s diff --git a/llvm/lib/Target/Hexagon/HexagonIntrinsics.td b/llvm/lib/Target/Hexagon/HexagonIntrinsics.td index 105ad371ca6e..99f59d5ea669 100644 --- a/llvm/lib/Target/Hexagon/HexagonIntrinsics.td +++ b/llvm/lib/Target/Hexagon/HexagonIntrinsics.td @@ -13,123 +13,6 @@ // March 4, 2008 //===----------------------------------------------------------------------===// -// MTYPE / MPYS / Scalar 16x16 multiply signed/unsigned. -//Rd=mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat] - -// M2_mpyu_lh_s1: -let hasNewValue = 1, opNewValue = 0 in -class T_M2_mpy < bits<2> LHbits, bit isSat, bit isRnd, - bit hasShift, bit isUnsigned, Intrinsic IntID > - : MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt), - "$Rd = "#!if(isUnsigned,"mpyu","mpy")#"($Rs."#!if(LHbits{1},"h","l") - #", $Rt."#!if(LHbits{0},"h)","l)") - #!if(hasShift,":<<1","") - #!if(isRnd,":rnd","") - #!if(isSat,":sat",""), - [(set IntRegs:$Rd, (IntID IntRegs:$Rs, IntRegs:$Rt))], "", M_tc_3x_SLOT23 > { - bits<5> Rd; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1110; - - let Inst{27-24} = 0b1100; - let Inst{23} = hasShift; - let Inst{22} = isUnsigned; - let Inst{21} = isRnd; - let Inst{7} = isSat; - let Inst{6-5} = LHbits; - let Inst{4-0} = Rd; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - } - -//Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1] -def HEXAGON_M2_mpy_ll_s1: T_M2_mpy<0b00, 0, 0, 1, 0, int_hexagon_M2_mpy_ll_s1>; -def HEXAGON_M2_mpy_ll_s0: T_M2_mpy<0b00, 0, 0, 0, 0, int_hexagon_M2_mpy_ll_s0>; -def HEXAGON_M2_mpy_lh_s1: T_M2_mpy<0b01, 0, 0, 1, 0, int_hexagon_M2_mpy_lh_s1>; -def HEXAGON_M2_mpy_lh_s0: T_M2_mpy<0b01, 0, 0, 0, 0, int_hexagon_M2_mpy_lh_s0>; -def HEXAGON_M2_mpy_hl_s1: T_M2_mpy<0b10, 0, 0, 1, 0, int_hexagon_M2_mpy_hl_s1>; -def HEXAGON_M2_mpy_hl_s0: T_M2_mpy<0b10, 0, 0, 0, 0, int_hexagon_M2_mpy_hl_s0>; -def HEXAGON_M2_mpy_hh_s1: T_M2_mpy<0b11, 0, 0, 1, 0, int_hexagon_M2_mpy_hh_s1>; -def HEXAGON_M2_mpy_hh_s0: T_M2_mpy<0b11, 0, 0, 0, 0, int_hexagon_M2_mpy_hh_s0>; - -//Rd=mpyu(Rs.[H|L],Rt.[H|L])[:<<1] -def HEXAGON_M2_mpyu_ll_s1: - T_M2_mpy<0b00, 0, 0, 1, 1, int_hexagon_M2_mpyu_ll_s1>; -def HEXAGON_M2_mpyu_ll_s0: - T_M2_mpy<0b00, 0, 0, 0, 1, int_hexagon_M2_mpyu_ll_s0>; -def HEXAGON_M2_mpyu_lh_s1: - T_M2_mpy<0b01, 0, 0, 1, 1, int_hexagon_M2_mpyu_lh_s1>; -def HEXAGON_M2_mpyu_lh_s0: - T_M2_mpy<0b01, 0, 0, 0, 1, int_hexagon_M2_mpyu_lh_s0>; -def HEXAGON_M2_mpyu_hl_s1: - T_M2_mpy<0b10, 0, 0, 1, 1, int_hexagon_M2_mpyu_hl_s1>; -def HEXAGON_M2_mpyu_hl_s0: - T_M2_mpy<0b10, 0, 0, 0, 1, int_hexagon_M2_mpyu_hl_s0>; -def HEXAGON_M2_mpyu_hh_s1: - T_M2_mpy<0b11, 0, 0, 1, 1, int_hexagon_M2_mpyu_hh_s1>; -def HEXAGON_M2_mpyu_hh_s0: - T_M2_mpy<0b11, 0, 0, 0, 1, int_hexagon_M2_mpyu_hh_s0>; - -//Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1][:sat] -let Defs = [USR] in { -def HEXAGON_M2_mpy_sat_ll_s1 : - T_M2_mpy <0b00, 1, 0, 1, 0, int_hexagon_M2_mpy_sat_ll_s1>; -def HEXAGON_M2_mpy_sat_ll_s0 : - T_M2_mpy <0b00, 1, 0, 0, 0, int_hexagon_M2_mpy_sat_ll_s0>; -def HEXAGON_M2_mpy_sat_lh_s1 : - T_M2_mpy <0b01, 1, 0, 1, 0, int_hexagon_M2_mpy_sat_lh_s1>; -def HEXAGON_M2_mpy_sat_lh_s0 : - T_M2_mpy <0b01, 1, 0, 0, 0, int_hexagon_M2_mpy_sat_lh_s0>; -def HEXAGON_M2_mpy_sat_hl_s1 : - T_M2_mpy <0b10, 1, 0, 1, 0, int_hexagon_M2_mpy_sat_hl_s1>; -def HEXAGON_M2_mpy_sat_hl_s0 : - T_M2_mpy <0b10, 1, 0, 0, 0, int_hexagon_M2_mpy_sat_hl_s0>; -def HEXAGON_M2_mpy_sat_hh_s1 : - T_M2_mpy <0b11, 1, 0, 1, 0, int_hexagon_M2_mpy_sat_hh_s1>; -def HEXAGON_M2_mpy_sat_hh_s0 : - T_M2_mpy <0b11, 1, 0, 0, 0, int_hexagon_M2_mpy_sat_hh_s0>; -} - -//Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1][:rnd] -def HEXAGON_M2_mpy_rnd_ll_s1 : - T_M2_mpy <0b00, 0, 1, 1, 0, int_hexagon_M2_mpy_rnd_ll_s1>; -def HEXAGON_M2_mpy_rnd_ll_s0 : - T_M2_mpy <0b00, 0, 1, 0, 0, int_hexagon_M2_mpy_rnd_ll_s0>; -def HEXAGON_M2_mpy_rnd_lh_s1 : - T_M2_mpy <0b01, 0, 1, 1, 0, int_hexagon_M2_mpy_rnd_lh_s1>; -def HEXAGON_M2_mpy_rnd_lh_s0 : - T_M2_mpy <0b01, 0, 1, 0, 0, int_hexagon_M2_mpy_rnd_lh_s0>; -def HEXAGON_M2_mpy_rnd_hl_s1 : - T_M2_mpy <0b10, 0, 1, 1, 0, int_hexagon_M2_mpy_rnd_hl_s1>; -def HEXAGON_M2_mpy_rnd_hl_s0 : - T_M2_mpy <0b10, 0, 1, 0, 0, int_hexagon_M2_mpy_rnd_hl_s0>; -def HEXAGON_M2_mpy_rnd_hh_s1 : - T_M2_mpy <0b11, 0, 1, 1, 0, int_hexagon_M2_mpy_rnd_hh_s1>; -def HEXAGON_M2_mpy_rnd_hh_s0 : - T_M2_mpy <0b11, 0, 1, 0, 0, int_hexagon_M2_mpy_rnd_hh_s0>; - -//Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat] -let Defs = [USR] in { -def HEXAGON_M2_mpy_sat_rnd_ll_s1 : - T_M2_mpy <0b00, 1, 1, 1, 0, int_hexagon_M2_mpy_sat_rnd_ll_s1>; -def HEXAGON_M2_mpy_sat_rnd_ll_s0 : - T_M2_mpy <0b00, 1, 1, 0, 0, int_hexagon_M2_mpy_sat_rnd_ll_s0>; -def HEXAGON_M2_mpy_sat_rnd_lh_s1 : - T_M2_mpy <0b01, 1, 1, 1, 0, int_hexagon_M2_mpy_sat_rnd_lh_s1>; -def HEXAGON_M2_mpy_sat_rnd_lh_s0 : - T_M2_mpy <0b01, 1, 1, 0, 0, int_hexagon_M2_mpy_sat_rnd_lh_s0>; -def HEXAGON_M2_mpy_sat_rnd_hl_s1 : - T_M2_mpy <0b10, 1, 1, 1, 0, int_hexagon_M2_mpy_sat_rnd_hl_s1>; -def HEXAGON_M2_mpy_sat_rnd_hl_s0 : - T_M2_mpy <0b10, 1, 1, 0, 0, int_hexagon_M2_mpy_sat_rnd_hl_s0>; -def HEXAGON_M2_mpy_sat_rnd_hh_s1 : - T_M2_mpy <0b11, 1, 1, 1, 0, int_hexagon_M2_mpy_sat_rnd_hh_s1>; -def HEXAGON_M2_mpy_sat_rnd_hh_s0 : - T_M2_mpy <0b11, 1, 1, 0, 0, int_hexagon_M2_mpy_sat_rnd_hh_s0>; -} - // // ALU 32 types. // @@ -984,21 +867,41 @@ class si_MInst_sisi_hh !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H)")), [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>; +class si_MInst_sisi_hh_s1 + : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), + !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):<<1")), + [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>; + class si_MInst_sisi_lh : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")), [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>; +class si_MInst_sisi_lh_s1 + : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), + !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):<<1")), + [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>; + class si_MInst_sisi_hl : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L)")), [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>; +class si_MInst_sisi_hl_s1 + : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), + !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):<<1")), + [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>; + class si_MInst_sisi_ll : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")), [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>; +class si_MInst_sisi_ll_s1 + : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), + !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):<<1")), + [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>; + class si_MInst_sisi_up : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")), @@ -1558,6 +1461,147 @@ class si_MInst_didi_rnd_sat !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd:sat")), [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>; +class si_MInst_sisi_sat_hh + : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), + !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):sat")), + [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>; + +class si_MInst_sisi_sat_hh_s1 + : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), + !strconcat("$dst = ", !strconcat(opc , + "($src1.H, $src2.H):<<1:sat")), + [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>; + +class si_MInst_sisi_sat_hl + : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), + !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):sat")), + [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>; + +class si_MInst_sisi_sat_hl_s1 + : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), + !strconcat("$dst = ", !strconcat(opc , + "($src1.H, $src2.L):<<1:sat")), + [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>; + +class si_MInst_sisi_sat_lh + : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), + !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):sat")), + [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>; + +class si_MInst_sisi_sat_lh_s1 + : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), + !strconcat("$dst = ", !strconcat(opc , + "($src1.L, $src2.H):<<1:sat")), + [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>; + +class si_MInst_sisi_sat_ll + : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), + !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):sat")), + [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>; + +class si_MInst_sisi_sat_ll_s1 + : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), + !strconcat("$dst = ", !strconcat(opc , + "($src1.L, $src2.L):<<1:sat")), + [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>; + +class si_MInst_sisi_sat_rnd_hh + : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), + !strconcat("$dst = ", !strconcat(opc , + "($src1.H, $src2.H):rnd:sat")), + [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>; + +class si_MInst_sisi_rnd_hh + : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), + !strconcat("$dst = ", !strconcat(opc , + "($src1.H, $src2.H):rnd")), + [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>; + +class si_MInst_sisi_rnd_hh_s1 + : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), + !strconcat("$dst = ", !strconcat(opc , + "($src1.H, $src2.H):<<1:rnd")), + [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>; + +class si_MInst_sisi_sat_rnd_hh_s1 + : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), + !strconcat("$dst = ", + !strconcat(opc , + "($src1.H, $src2.H):<<1:rnd:sat")), + [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>; + +class si_MInst_sisi_rnd_hl + : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), + !strconcat("$dst = ", + !strconcat(opc , "($src1.H, $src2.L):rnd")), + [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>; + +class si_MInst_sisi_rnd_hl_s1 + : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), + !strconcat("$dst = ", + !strconcat(opc , "($src1.H, $src2.L):<<1:rnd")), + [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>; + +class si_MInst_sisi_sat_rnd_hl + : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), + !strconcat("$dst = ", + !strconcat(opc , "($src1.H, $src2.L):rnd:sat")), + [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>; + +class si_MInst_sisi_sat_rnd_hl_s1 + : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), + !strconcat("$dst = ", + !strconcat(opc , "($src1.H, $src2.L):<<1:rnd:sat")), + [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>; + +class si_MInst_sisi_rnd_lh + : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), + !strconcat("$dst = ", + !strconcat(opc , "($src1.L, $src2.H):rnd")), + [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>; + +class si_MInst_sisi_sat_rnd_lh + : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), + !strconcat("$dst = ", + !strconcat(opc , "($src1.L, $src2.H):rnd:sat")), + [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>; + +class si_MInst_sisi_sat_rnd_lh_s1 + : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), + !strconcat("$dst = ", + !strconcat(opc , "($src1.L, $src2.H):<<1:rnd:sat")), + [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>; + +class si_MInst_sisi_rnd_lh_s1 + : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), + !strconcat("$dst = ", + !strconcat(opc , "($src1.L, $src2.H):<<1:rnd")), + [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>; + +class si_MInst_sisi_sat_rnd_ll + : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), + !strconcat("$dst = ", + !strconcat(opc , "($src1.L, $src2.L):rnd:sat")), + [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>; + +class si_MInst_sisi_sat_rnd_ll_s1 + : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), + !strconcat("$dst = ", + !strconcat(opc , "($src1.L, $src2.L):<<1:rnd:sat")), + [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>; + +class si_MInst_sisi_rnd_ll + : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), + !strconcat("$dst = ", + !strconcat(opc , "($src1.L, $src2.L):rnd")), + [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>; + +class si_MInst_sisi_rnd_ll_s1 + : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2), + !strconcat("$dst = ", + !strconcat(opc , "($src1.L, $src2.L):<<1:rnd")), + [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>; + class di_MInst_dididi_acc_sat : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1, DoubleRegs:$src2), @@ -2520,6 +2564,74 @@ def HEXAGON_M2_dpmpyss_nac_s0: // MTYPE / MPYS / Scalar 16x16 multiply signed. //Rd=mpy(Rs.[H|L],Rt.[H|L:<<0|:<<1]| // [:<<0[:rnd|:sat|:rnd:sat]|:<<1[:rnd|:sat|:rnd:sat]]] +def HEXAGON_M2_mpy_hh_s0: + si_MInst_sisi_hh <"mpy", int_hexagon_M2_mpy_hh_s0>; +def HEXAGON_M2_mpy_hh_s1: + si_MInst_sisi_hh_s1 <"mpy", int_hexagon_M2_mpy_hh_s1>; +def HEXAGON_M2_mpy_rnd_hh_s1: + si_MInst_sisi_rnd_hh_s1 <"mpy", int_hexagon_M2_mpy_rnd_hh_s1>; +def HEXAGON_M2_mpy_sat_rnd_hh_s1: + si_MInst_sisi_sat_rnd_hh_s1 <"mpy", int_hexagon_M2_mpy_sat_rnd_hh_s1>; +def HEXAGON_M2_mpy_sat_hh_s1: + si_MInst_sisi_sat_hh_s1 <"mpy", int_hexagon_M2_mpy_sat_hh_s1>; +def HEXAGON_M2_mpy_rnd_hh_s0: + si_MInst_sisi_rnd_hh <"mpy", int_hexagon_M2_mpy_rnd_hh_s0>; +def HEXAGON_M2_mpy_sat_rnd_hh_s0: + si_MInst_sisi_sat_rnd_hh <"mpy", int_hexagon_M2_mpy_sat_rnd_hh_s0>; +def HEXAGON_M2_mpy_sat_hh_s0: + si_MInst_sisi_sat_hh <"mpy", int_hexagon_M2_mpy_sat_hh_s0>; + +def HEXAGON_M2_mpy_hl_s0: + si_MInst_sisi_hl <"mpy", int_hexagon_M2_mpy_hl_s0>; +def HEXAGON_M2_mpy_hl_s1: + si_MInst_sisi_hl_s1 <"mpy", int_hexagon_M2_mpy_hl_s1>; +def HEXAGON_M2_mpy_rnd_hl_s1: + si_MInst_sisi_rnd_hl_s1 <"mpy", int_hexagon_M2_mpy_rnd_hl_s1>; +def HEXAGON_M2_mpy_sat_rnd_hl_s1: + si_MInst_sisi_sat_rnd_hl_s1 <"mpy", int_hexagon_M2_mpy_sat_rnd_hl_s1>; +def HEXAGON_M2_mpy_sat_hl_s1: + si_MInst_sisi_sat_hl_s1 <"mpy", int_hexagon_M2_mpy_sat_hl_s1>; +def HEXAGON_M2_mpy_rnd_hl_s0: + si_MInst_sisi_rnd_hl <"mpy", int_hexagon_M2_mpy_rnd_hl_s0>; +def HEXAGON_M2_mpy_sat_rnd_hl_s0: + si_MInst_sisi_sat_rnd_hl <"mpy", int_hexagon_M2_mpy_sat_rnd_hl_s0>; +def HEXAGON_M2_mpy_sat_hl_s0: + si_MInst_sisi_sat_hl <"mpy", int_hexagon_M2_mpy_sat_hl_s0>; + +def HEXAGON_M2_mpy_lh_s0: + si_MInst_sisi_lh <"mpy", int_hexagon_M2_mpy_lh_s0>; +def HEXAGON_M2_mpy_lh_s1: + si_MInst_sisi_lh_s1 <"mpy", int_hexagon_M2_mpy_lh_s1>; +def HEXAGON_M2_mpy_rnd_lh_s1: + si_MInst_sisi_rnd_lh_s1 <"mpy", int_hexagon_M2_mpy_rnd_lh_s1>; +def HEXAGON_M2_mpy_sat_rnd_lh_s1: + si_MInst_sisi_sat_rnd_lh_s1 <"mpy", int_hexagon_M2_mpy_sat_rnd_lh_s1>; +def HEXAGON_M2_mpy_sat_lh_s1: + si_MInst_sisi_sat_lh_s1 <"mpy", int_hexagon_M2_mpy_sat_lh_s1>; +def HEXAGON_M2_mpy_rnd_lh_s0: + si_MInst_sisi_rnd_lh <"mpy", int_hexagon_M2_mpy_rnd_lh_s0>; +def HEXAGON_M2_mpy_sat_rnd_lh_s0: + si_MInst_sisi_sat_rnd_lh <"mpy", int_hexagon_M2_mpy_sat_rnd_lh_s0>; +def HEXAGON_M2_mpy_sat_lh_s0: + si_MInst_sisi_sat_lh <"mpy", int_hexagon_M2_mpy_sat_lh_s0>; + +def HEXAGON_M2_mpy_ll_s0: + si_MInst_sisi_ll <"mpy", int_hexagon_M2_mpy_ll_s0>; +def HEXAGON_M2_mpy_ll_s1: + si_MInst_sisi_ll_s1 <"mpy", int_hexagon_M2_mpy_ll_s1>; +def HEXAGON_M2_mpy_rnd_ll_s1: + si_MInst_sisi_rnd_ll_s1 <"mpy", int_hexagon_M2_mpy_rnd_ll_s1>; +def HEXAGON_M2_mpy_sat_rnd_ll_s1: + si_MInst_sisi_sat_rnd_ll_s1 <"mpy", int_hexagon_M2_mpy_sat_rnd_ll_s1>; +def HEXAGON_M2_mpy_sat_ll_s1: + si_MInst_sisi_sat_ll_s1 <"mpy", int_hexagon_M2_mpy_sat_ll_s1>; +def HEXAGON_M2_mpy_rnd_ll_s0: + si_MInst_sisi_rnd_ll <"mpy", int_hexagon_M2_mpy_rnd_ll_s0>; +def HEXAGON_M2_mpy_sat_rnd_ll_s0: + si_MInst_sisi_sat_rnd_ll <"mpy", int_hexagon_M2_mpy_sat_rnd_ll_s0>; +def HEXAGON_M2_mpy_sat_ll_s0: + si_MInst_sisi_sat_ll <"mpy", int_hexagon_M2_mpy_sat_ll_s0>; + //Rdd=mpy(Rs.[H|L],Rt.[H|L])[[:<<0|:<<1]|[:<<0:rnd|:<<1:rnd]] def HEXAGON_M2_mpyd_hh_s0: di_MInst_sisi_hh <"mpy", int_hexagon_M2_mpyd_hh_s0>; @@ -2673,6 +2785,24 @@ def HEXAGON_M2_mpyd_nac_ll_s0: def HEXAGON_M2_mpyd_nac_ll_s1: di_MInst_disisi_nac_ll_s1 <"mpy", int_hexagon_M2_mpyd_nac_ll_s1>; +// MTYPE / MPYS / Scalar 16x16 multiply unsigned. +//Rd=mpyu(Rs.[H|L],Rt.[H|L])[:<<0|:<<1] +def HEXAGON_M2_mpyu_hh_s0: + si_MInst_sisi_hh <"mpyu", int_hexagon_M2_mpyu_hh_s0>; +def HEXAGON_M2_mpyu_hh_s1: + si_MInst_sisi_hh_s1 <"mpyu", int_hexagon_M2_mpyu_hh_s1>; +def HEXAGON_M2_mpyu_hl_s0: + si_MInst_sisi_hl <"mpyu", int_hexagon_M2_mpyu_hl_s0>; +def HEXAGON_M2_mpyu_hl_s1: + si_MInst_sisi_hl_s1 <"mpyu", int_hexagon_M2_mpyu_hl_s1>; +def HEXAGON_M2_mpyu_lh_s0: + si_MInst_sisi_lh <"mpyu", int_hexagon_M2_mpyu_lh_s0>; +def HEXAGON_M2_mpyu_lh_s1: + si_MInst_sisi_lh_s1 <"mpyu", int_hexagon_M2_mpyu_lh_s1>; +def HEXAGON_M2_mpyu_ll_s0: + si_MInst_sisi_ll <"mpyu", int_hexagon_M2_mpyu_ll_s0>; +def HEXAGON_M2_mpyu_ll_s1: + si_MInst_sisi_ll_s1 <"mpyu", int_hexagon_M2_mpyu_ll_s1>; //Rdd=mpyu(Rs.[H|L],Rt.[H|L])[:<<0|:<<1] def HEXAGON_M2_mpyud_hh_s0: diff --git a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td index 486bd5cec61b..8ea1b7e75db7 100644 --- a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td +++ b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td @@ -134,9 +134,8 @@ let Namespace = "Hexagon" in { def M0 : Rc<6, "m0">, DwarfRegNum<[71]>; def M1 : Rc<7, "m1">, DwarfRegNum<[72]>; - def USR : Rc<8, "usr">, DwarfRegNum<[34]>; - def PC : Rc<9, "pc">, DwarfRegNum<[32]>; - def GP : Rc<11, "gp">, DwarfRegNum<[33]>; + def PC : Rc<9, "pc">, DwarfRegNum<[32]>; // is the Dwarf number correct? + def GP : Rc<11, "gp">, DwarfRegNum<[33]>; // is the Dwarf number correct? } // Register classes. @@ -163,6 +162,6 @@ def PredRegs : RegisterClass<"Hexagon", [i1], 32, (add (sequence "P%u", 0, 3))> def CRRegs : RegisterClass<"Hexagon", [i32], 32, (add (sequence "LC%u", 0, 1), (sequence "SA%u", 0, 1), - (sequence "M%u", 0, 1), PC, GP, USR)> { + (sequence "M%u", 0, 1), PC, GP)> { let Size = 32; } diff --git a/llvm/test/CodeGen/Hexagon/intrinsics-mpy.ll b/llvm/test/CodeGen/Hexagon/intrinsics-mpy.ll deleted file mode 100644 index 74d181319307..000000000000 --- a/llvm/test/CodeGen/Hexagon/intrinsics-mpy.ll +++ /dev/null @@ -1,456 +0,0 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s - -; Verify that the mpy intrinsics are lowered into the right instructions. - -@c = external global i32 - -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.l) - -define void @test1(i32 %a1, i32 %b1) #0 { -entry: - %0 = tail call i32 @llvm.hexagon.M2.mpy.ll.s0(i32 %a1, i32 %b1) - store i32 %0, i32* @c, align 4, !tbaa !1 - ret void -} - -declare i32 @llvm.hexagon.M2.mpy.ll.s0(i32, i32) #1 - -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.h) - -define void @test2(i32 %a2, i32 %b2) #0 { -entry: - %0 = tail call i32 @llvm.hexagon.M2.mpy.lh.s0(i32 %a2, i32 %b2) - store i32 %0, i32* @c, align 4, !tbaa !1 - ret void -} - -declare i32 @llvm.hexagon.M2.mpy.lh.s0(i32, i32) #1 - -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.l) - -define void @test3(i32 %a3, i32 %b3) #0 { -entry: - %0 = tail call i32 @llvm.hexagon.M2.mpy.hl.s0(i32 %a3, i32 %b3) - store i32 %0, i32* @c, align 4, !tbaa !1 - ret void -} - -declare i32 @llvm.hexagon.M2.mpy.hl.s0(i32, i32) #1 - -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.h) - -define void @test4(i32 %a4, i32 %b4) #0 { -entry: - %0 = tail call i32 @llvm.hexagon.M2.mpy.hh.s0(i32 %a4, i32 %b4) - store i32 %0, i32* @c, align 4, !tbaa !1 - ret void -} - -declare i32 @llvm.hexagon.M2.mpy.hh.s0(i32, i32) #1 - -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.l):sat - -define void @test5(i32 %a5, i32 %b5) #0 { -entry: - %0 = tail call i32 @llvm.hexagon.M2.mpy.sat.ll.s0(i32 %a5, i32 %b5) - store i32 %0, i32* @c, align 4, !tbaa !1 - ret void -} - -declare i32 @llvm.hexagon.M2.mpy.sat.ll.s0(i32, i32) #1 - -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.h):sat - -define void @test6(i32 %a6, i32 %b6) #0 { -entry: - %0 = tail call i32 @llvm.hexagon.M2.mpy.sat.lh.s0(i32 %a6, i32 %b6) - store i32 %0, i32* @c, align 4, !tbaa !1 - ret void -} - -declare i32 @llvm.hexagon.M2.mpy.sat.lh.s0(i32, i32) #1 - -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.l):sat - -define void @test7(i32 %a7, i32 %b7) #0 { -entry: - %0 = tail call i32 @llvm.hexagon.M2.mpy.sat.hl.s0(i32 %a7, i32 %b7) - store i32 %0, i32* @c, align 4, !tbaa !1 - ret void -} - -declare i32 @llvm.hexagon.M2.mpy.sat.hl.s0(i32, i32) #1 - -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.h):sat - -define void @test8(i32 %a8, i32 %b8) #0 { -entry: - %0 = tail call i32 @llvm.hexagon.M2.mpy.sat.hh.s0(i32 %a8, i32 %b8) - store i32 %0, i32* @c, align 4, !tbaa !1 - ret void -} - -declare i32 @llvm.hexagon.M2.mpy.sat.hh.s0(i32, i32) #1 - -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.l):rnd - -define void @test9(i32 %a9, i32 %b9) #0 { -entry: - %0 = tail call i32 @llvm.hexagon.M2.mpy.rnd.ll.s0(i32 %a9, i32 %b9) - store i32 %0, i32* @c, align 4, !tbaa !1 - ret void -} - -declare i32 @llvm.hexagon.M2.mpy.rnd.ll.s0(i32, i32) #1 - -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.h):rnd - -define void @test10(i32 %a10, i32 %b10) #0 { -entry: - %0 = tail call i32 @llvm.hexagon.M2.mpy.rnd.lh.s0(i32 %a10, i32 %b10) - store i32 %0, i32* @c, align 4, !tbaa !1 - ret void -} - -declare i32 @llvm.hexagon.M2.mpy.rnd.lh.s0(i32, i32) #1 - -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.l):rnd - -define void @test11(i32 %a11, i32 %b11) #0 { -entry: - %0 = tail call i32 @llvm.hexagon.M2.mpy.rnd.hl.s0(i32 %a11, i32 %b11) - store i32 %0, i32* @c, align 4, !tbaa !1 - ret void -} - -declare i32 @llvm.hexagon.M2.mpy.rnd.hl.s0(i32, i32) #1 - -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.h):rnd - -define void @test12(i32 %a12, i32 %b12) #0 { -entry: - %0 = tail call i32 @llvm.hexagon.M2.mpy.rnd.hh.s0(i32 %a12, i32 %b12) - store i32 %0, i32* @c, align 4, !tbaa !1 - ret void -} - -declare i32 @llvm.hexagon.M2.mpy.rnd.hh.s0(i32, i32) #1 - -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.l):rnd:sat - -define void @test13(i32 %a13, i32 %b13) #0 { -entry: - %0 = tail call i32 @llvm.hexagon.M2.mpy.sat.rnd.ll.s0(i32 %a13, i32 %b13) - store i32 %0, i32* @c, align 4, !tbaa !1 - ret void -} - -declare i32 @llvm.hexagon.M2.mpy.sat.rnd.ll.s0(i32, i32) #1 - -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.h):rnd:sat - -define void @test14(i32 %a14, i32 %b14) #0 { -entry: - %0 = tail call i32 @llvm.hexagon.M2.mpy.sat.rnd.lh.s0(i32 %a14, i32 %b14) - store i32 %0, i32* @c, align 4, !tbaa !1 - ret void -} - -declare i32 @llvm.hexagon.M2.mpy.sat.rnd.lh.s0(i32, i32) #1 - -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.l):rnd:sat - -define void @test15(i32 %a15, i32 %b15) #0 { -entry: - %0 = tail call i32 @llvm.hexagon.M2.mpy.sat.rnd.hl.s0(i32 %a15, i32 %b15) - store i32 %0, i32* @c, align 4, !tbaa !1 - ret void -} - -declare i32 @llvm.hexagon.M2.mpy.sat.rnd.hl.s0(i32, i32) #1 - -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.h):rnd:sat - -define void @test16(i32 %a16, i32 %b16) #0 { -entry: - %0 = tail call i32 @llvm.hexagon.M2.mpy.sat.rnd.hh.s0(i32 %a16, i32 %b16) - store i32 %0, i32* @c, align 4, !tbaa !1 - ret void -} - -declare i32 @llvm.hexagon.M2.mpy.sat.rnd.hh.s0(i32, i32) #1 - -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpyu(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.l) - -define void @test17(i32 %a17, i32 %b17) #0 { -entry: - %0 = tail call i32 @llvm.hexagon.M2.mpyu.ll.s0(i32 %a17, i32 %b17) - store i32 %0, i32* @c, align 4, !tbaa !1 - ret void -} - -declare i32 @llvm.hexagon.M2.mpyu.ll.s0(i32, i32) #1 - -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpyu(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.h) - -define void @test18(i32 %a18, i32 %b18) #0 { -entry: - %0 = tail call i32 @llvm.hexagon.M2.mpyu.lh.s0(i32 %a18, i32 %b18) - store i32 %0, i32* @c, align 4, !tbaa !1 - ret void -} - -declare i32 @llvm.hexagon.M2.mpyu.lh.s0(i32, i32) #1 - -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpyu(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.l) - -define void @test19(i32 %a19, i32 %b19) #0 { -entry: - %0 = tail call i32 @llvm.hexagon.M2.mpyu.hl.s0(i32 %a19, i32 %b19) - store i32 %0, i32* @c, align 4, !tbaa !1 - ret void -} - -declare i32 @llvm.hexagon.M2.mpyu.hl.s0(i32, i32) #1 - -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpyu(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.h) - -define void @test20(i32 %a20, i32 %b20) #0 { -entry: - %0 = tail call i32 @llvm.hexagon.M2.mpyu.hh.s0(i32 %a20, i32 %b20) - store i32 %0, i32* @c, align 4, !tbaa !1 - ret void -} - -declare i32 @llvm.hexagon.M2.mpyu.hh.s0(i32, i32) #1 - -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.l):<<1 - -define void @test21(i32 %a21, i32 %b21) #0 { -entry: - %0 = tail call i32 @llvm.hexagon.M2.mpy.ll.s1(i32 %a21, i32 %b21) - store i32 %0, i32* @c, align 4, !tbaa !1 - ret void -} - -declare i32 @llvm.hexagon.M2.mpy.ll.s1(i32, i32) #1 - -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.h):<<1 - -define void @test22(i32 %a22, i32 %b22) #0 { -entry: - %0 = tail call i32 @llvm.hexagon.M2.mpy.lh.s1(i32 %a22, i32 %b22) - store i32 %0, i32* @c, align 4, !tbaa !1 - ret void -} - -declare i32 @llvm.hexagon.M2.mpy.lh.s1(i32, i32) #1 - -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.l):<<1 - -define void @test23(i32 %a23, i32 %b23) #0 { -entry: - %0 = tail call i32 @llvm.hexagon.M2.mpy.hl.s1(i32 %a23, i32 %b23) - store i32 %0, i32* @c, align 4, !tbaa !1 - ret void -} - -declare i32 @llvm.hexagon.M2.mpy.hl.s1(i32, i32) #1 - -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.h):<<1 - -define void @test24(i32 %a24, i32 %b24) #0 { -entry: - %0 = tail call i32 @llvm.hexagon.M2.mpy.hh.s1(i32 %a24, i32 %b24) - store i32 %0, i32* @c, align 4, !tbaa !1 - ret void -} - -declare i32 @llvm.hexagon.M2.mpy.hh.s1(i32, i32) #1 - -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.l):<<1:sat - -define void @test25(i32 %a25, i32 %b25) #0 { -entry: - %0 = tail call i32 @llvm.hexagon.M2.mpy.sat.ll.s1(i32 %a25, i32 %b25) - store i32 %0, i32* @c, align 4, !tbaa !1 - ret void -} - -declare i32 @llvm.hexagon.M2.mpy.sat.ll.s1(i32, i32) #1 - -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.h):<<1:sat - -define void @test26(i32 %a26, i32 %b26) #0 { -entry: - %0 = tail call i32 @llvm.hexagon.M2.mpy.sat.lh.s1(i32 %a26, i32 %b26) - store i32 %0, i32* @c, align 4, !tbaa !1 - ret void -} - -declare i32 @llvm.hexagon.M2.mpy.sat.lh.s1(i32, i32) #1 - -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.l):<<1:sat - -define void @test27(i32 %a27, i32 %b27) #0 { -entry: - %0 = tail call i32 @llvm.hexagon.M2.mpy.sat.hl.s1(i32 %a27, i32 %b27) - store i32 %0, i32* @c, align 4, !tbaa !1 - ret void -} - -declare i32 @llvm.hexagon.M2.mpy.sat.hl.s1(i32, i32) #1 - -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.h):<<1:sat - -define void @test28(i32 %a28, i32 %b28) #0 { -entry: - %0 = tail call i32 @llvm.hexagon.M2.mpy.sat.hh.s1(i32 %a28, i32 %b28) - store i32 %0, i32* @c, align 4, !tbaa !1 - ret void -} - -declare i32 @llvm.hexagon.M2.mpy.sat.hh.s1(i32, i32) #1 - -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.l):<<1:rnd - -define void @test29(i32 %a29, i32 %b29) #0 { -entry: - %0 = tail call i32 @llvm.hexagon.M2.mpy.rnd.ll.s1(i32 %a29, i32 %b29) - store i32 %0, i32* @c, align 4, !tbaa !1 - ret void -} - -declare i32 @llvm.hexagon.M2.mpy.rnd.ll.s1(i32, i32) #1 - -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.h):<<1:rnd - -define void @test30(i32 %a30, i32 %b30) #0 { -entry: - %0 = tail call i32 @llvm.hexagon.M2.mpy.rnd.lh.s1(i32 %a30, i32 %b30) - store i32 %0, i32* @c, align 4, !tbaa !1 - ret void -} - -declare i32 @llvm.hexagon.M2.mpy.rnd.lh.s1(i32, i32) #1 - -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.l):<<1:rnd - -define void @test31(i32 %a31, i32 %b31) #0 { -entry: - %0 = tail call i32 @llvm.hexagon.M2.mpy.rnd.hl.s1(i32 %a31, i32 %b31) - store i32 %0, i32* @c, align 4, !tbaa !1 - ret void -} - -declare i32 @llvm.hexagon.M2.mpy.rnd.hl.s1(i32, i32) #1 - -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.h):<<1:rnd - -define void @test32(i32 %a32, i32 %b32) #0 { -entry: - %0 = tail call i32 @llvm.hexagon.M2.mpy.rnd.hh.s1(i32 %a32, i32 %b32) - store i32 %0, i32* @c, align 4, !tbaa !1 - ret void -} - -declare i32 @llvm.hexagon.M2.mpy.rnd.hh.s1(i32, i32) #1 - -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.l):<<1:rnd:sat - -define void @test33(i32 %a33, i32 %b33) #0 { -entry: - %0 = tail call i32 @llvm.hexagon.M2.mpy.sat.rnd.ll.s1(i32 %a33, i32 %b33) - store i32 %0, i32* @c, align 4, !tbaa !1 - ret void -} - -declare i32 @llvm.hexagon.M2.mpy.sat.rnd.ll.s1(i32, i32) #1 - -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.h):<<1:rnd:sat - -define void @test34(i32 %a34, i32 %b34) #0 { -entry: - %0 = tail call i32 @llvm.hexagon.M2.mpy.sat.rnd.lh.s1(i32 %a34, i32 %b34) - store i32 %0, i32* @c, align 4, !tbaa !1 - ret void -} - -declare i32 @llvm.hexagon.M2.mpy.sat.rnd.lh.s1(i32, i32) #1 - -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.l):<<1:rnd:sat - -define void @test35(i32 %a35, i32 %b35) #0 { -entry: - %0 = tail call i32 @llvm.hexagon.M2.mpy.sat.rnd.hl.s1(i32 %a35, i32 %b35) - store i32 %0, i32* @c, align 4, !tbaa !1 - ret void -} - -declare i32 @llvm.hexagon.M2.mpy.sat.rnd.hl.s1(i32, i32) #1 - -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.h):<<1:rnd:sat - -define void @test36(i32 %a36, i32 %b36) #0 { -entry: - %0 = tail call i32 @llvm.hexagon.M2.mpy.sat.rnd.hh.s1(i32 %a36, i32 %b36) - store i32 %0, i32* @c, align 4, !tbaa !1 - ret void -} - -declare i32 @llvm.hexagon.M2.mpy.sat.rnd.hh.s1(i32, i32) #1 - -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpyu(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.l):<<1 - -define void @test37(i32 %a37, i32 %b37) #0 { -entry: - %0 = tail call i32 @llvm.hexagon.M2.mpyu.ll.s1(i32 %a37, i32 %b37) - store i32 %0, i32* @c, align 4, !tbaa !1 - ret void -} - -declare i32 @llvm.hexagon.M2.mpyu.ll.s1(i32, i32) #1 - -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpyu(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.h):<<1 - -define void @test38(i32 %a38, i32 %b38) #0 { -entry: - %0 = tail call i32 @llvm.hexagon.M2.mpyu.lh.s1(i32 %a38, i32 %b38) - store i32 %0, i32* @c, align 4, !tbaa !1 - ret void -} - -declare i32 @llvm.hexagon.M2.mpyu.lh.s1(i32, i32) #1 - -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpyu(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.l):<<1 - -define void @test39(i32 %a39, i32 %b39) #0 { -entry: - %0 = tail call i32 @llvm.hexagon.M2.mpyu.hl.s1(i32 %a39, i32 %b39) - store i32 %0, i32* @c, align 4, !tbaa !1 - ret void -} - -declare i32 @llvm.hexagon.M2.mpyu.hl.s1(i32, i32) #1 - -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpyu(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.h):<<1 - -define void @test40(i32 %a40, i32 %b40) #0 { -entry: - %0 = tail call i32 @llvm.hexagon.M2.mpyu.hh.s1(i32 %a40, i32 %b40) - store i32 %0, i32* @c, align 4, !tbaa !1 - ret void -} - -declare i32 @llvm.hexagon.M2.mpyu.hh.s1(i32, i32) #1 - -attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { nounwind readnone } - -!llvm.ident = !{!0} - -!0 = metadata !{metadata !"QuIC LLVM Hexagon Clang version 7.1-internal"} -!1 = metadata !{metadata !2, metadata !2, i64 0} -!2 = metadata !{metadata !"int", metadata !3, i64 0} -!3 = metadata !{metadata !"omnipotent char", metadata !4, i64 0} -!4 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/llvm/test/MC/Hexagon/mpy.s b/llvm/test/MC/Hexagon/mpy.s deleted file mode 100644 index 9e9706fc4c7c..000000000000 --- a/llvm/test/MC/Hexagon/mpy.s +++ /dev/null @@ -1,126 +0,0 @@ -#REQUIRES: object-emission -#This test will be enabled when assembler support has been added. - -#RUN: llvm-mc -filetype=obj %s | llvm-objdump -d - | FileCheck %s - -# Check encoding bits for half-word multiply instructions. - -r7=mpy(r28.l,r20.h):<<1:rnd -#CHECK: ecbcd427 { r7 = mpy(r28.l, r20.h):<<1:rnd } - -r18=mpy(r9.l,r21.h):rnd -#CHECK: ec29d532 { r18 = mpy(r9.l, r21.h):rnd } - -r19=mpyu(r23.l,r20.l) -#CHECK: ec57d413 { r19 = mpyu(r23.l, r20.l) } - -r22=mpyu(r19.l,r30.l):<<1 -#CHECK: ecd3de16 { r22 = mpyu(r19.l, r30.l):<<1 } - -r19=mpy(r16.h,r19.h) -#CHECK: ec10d373 { r19 = mpy(r16.h, r19.h) } - -r30=mpy(r0.h,r16.h):<<1 -#CHECK: ec80d07e { r30 = mpy(r0.h, r16.h):<<1 } - -lr=mpy(r15.h,r25.l) -#CHECK: ec0fd95f { r31 = mpy(r15.h, r25.l) } - -r29=mpy(r28.h,r15.l):<<1 -#CHECK: ec9ccf5d { r29 = mpy(r28.h, r15.l):<<1 } - -r20=mpy(r31.l,r19.h) -#CHECK: ec1fd334 { r20 = mpy(r31.l, r19.h) } - -r24=mpy(r19.l,r15.h):<<1 -#CHECK: ec93cf38 { r24 = mpy(r19.l, r15.h):<<1 } - -r30=mpy(r10.l,sp.l) -#CHECK: ec0add1e { r30 = mpy(r10.l, r29.l) } - -r7=mpy(r3.l,r4.l):<<1 -#CHECK: ec83c407 { r7 = mpy(r3.l, r4.l):<<1 } - -r30=mpy(r23.h,r2.h):rnd:sat -#CHECK: ec37c2fe { r30 = mpy(r23.h, r2.h):rnd:sat } - -r5=mpy(r28.h,r27.h):<<1:rnd:sat -#CHECK: ecbcdbe5 { r5 = mpy(r28.h, r27.h):<<1:rnd:sat } - -r26=mpy(r21.l,r23.l):rnd -#CHECK: ec35d71a { r26 = mpy(r21.l, r23.l):rnd } - -sp=mpy(r25.h,r12.h):<<1:rnd -#CHECK: ecb9cc7d { r29 = mpy(r25.h, r12.h):<<1:rnd } - -r1=mpy(r27.h,r29.h):rnd -#CHECK: ec3bdd61 { r1 = mpy(r27.h, r29.h):rnd } - -r0=mpy(r2.h,r11.h):<<1:sat -#CHECK: ec82cbe0 { r0 = mpy(r2.h, r11.h):<<1:sat } - -r3=mpy(r20.l,r30.l):rnd:sat -#CHECK: ec34de83 { r3 = mpy(r20.l, r30.l):rnd:sat } - -r4=mpy(r21.h,r5.l):<<1:sat -#CHECK: ec95c5c4 { r4 = mpy(r21.h, r5.l):<<1:sat } - -fp=mpy(r20.l,r12.h):rnd:sat -#CHECK: ec34ccbe { r30 = mpy(r20.l, r12.h):rnd:sat } - -r12=mpy(sp.l,r30.h):<<1:rnd:sat -#CHECK: ecbddeac { r12 = mpy(r29.l, r30.h):<<1:rnd:sat } - -r6=mpy(r10.h,fp.l):rnd:sat -#CHECK: ec2adec6 { r6 = mpy(r10.h, r30.l):rnd:sat } - -r24=mpy(r12.h,r1.h):sat -#CHECK: ec0cc1f8 { r24 = mpy(r12.h, r1.h):sat } - -r29=mpyu(r25.h,sp.l) -#CHECK: ec59dd5d { r29 = mpyu(r25.h, r29.l) } - -r24=mpyu(lr.h,r29.l):<<1 -#CHECK: ecdfdd58 { r24 = mpyu(r31.h, r29.l):<<1 } - -r26=mpyu(r21.l,r18.h) -#CHECK: ec55d23a { r26 = mpyu(r21.l, r18.h) } - -r29=mpyu(r4.l,r26.h):<<1 -#CHECK: ecc4da3d { r29 = mpyu(r4.l, r26.h):<<1 } - -fp=mpy(r8.l,r0.l):sat -#CHECK: ec08c09e { r30 = mpy(r8.l, r0.l):sat } - -r1=mpy(r26.l,r16.l):<<1:sat -#CHECK: ec9ad081 { r1 = mpy(r26.l, r16.l):<<1:sat } - -r16=mpyu(r26.h,r6.h) -#CHECK: ec5ac670 { r16 = mpyu(r26.h, r6.h) } - -lr=mpyu(r23.h,r13.h):<<1 -#CHECK: ecd7cd7f { r31 = mpyu(r23.h, r13.h):<<1 } - -r14=mpy(r2.l,r7.h):sat -#CHECK: ec02c7ae { r14 = mpy(r2.l, r7.h):sat } - -r9=mpy(r1.l,r9.h):<<1:sat -#CHECK: ec81c9a9 { r9 = mpy(r1.l, r9.h):<<1:sat } - -r9=mpy(r30.l,r4.l):<<1:rnd:sat -#CHECK: ecbec489 { r9 = mpy(r30.l, r4.l):<<1:rnd:sat } - -r9=mpy(r15.h,r27.l):<<1:rnd -#CHECK: ecafdb49 { r9 = mpy(r15.h, r27.l):<<1:rnd } - -r16=mpy(r6.h,r16.l):rnd -#CHECK: ec26d050 { r16 = mpy(r6.h, r16.l):rnd } - -r1=mpy(r10.l,r29.l):<<1:rnd -#CHECK: ecaadd01 { r1 = mpy(r10.l, r29.l):<<1:rnd } - -r7=mpy(r4.h,r23.l):sat -#CHECK: ec04d7c7 { r7 = mpy(r4.h, r23.l):sat } - -r17=mpy(r12.h,r26.l):<<1:rnd:sat -#CHECK: ecacdad1 { r17 = mpy(r12.h, r26.l):<<1:rnd:sat }