From 99827e861f8b2407778154ab582bdcd9bb88ead0 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Thu, 17 Feb 2011 22:53:48 +0000 Subject: [PATCH] Add basic register allocator statistics. llvm-svn: 125789 --- llvm/lib/CodeGen/RegAllocBasic.cpp | 8 ++++++++ llvm/lib/CodeGen/RegAllocGreedy.cpp | 10 ++++++++++ 2 files changed, 18 insertions(+) diff --git a/llvm/lib/CodeGen/RegAllocBasic.cpp b/llvm/lib/CodeGen/RegAllocBasic.cpp index 7fbb035ed617..c0d4d8146a81 100644 --- a/llvm/lib/CodeGen/RegAllocBasic.cpp +++ b/llvm/lib/CodeGen/RegAllocBasic.cpp @@ -20,6 +20,7 @@ #include "VirtRegMap.h" #include "VirtRegRewriter.h" #include "llvm/ADT/OwningPtr.h" +#include "llvm/ADT/Statistic.h" #include "llvm/Analysis/AliasAnalysis.h" #include "llvm/Function.h" #include "llvm/PassAnalysisSupport.h" @@ -48,6 +49,10 @@ using namespace llvm; +STATISTIC(NumAssigned , "Number of registers assigned"); +STATISTIC(NumUnassigned , "Number of registers unassigned"); +STATISTIC(NumNewQueued , "Number of new live ranges queued"); + static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator", createBasicRegisterAllocator); @@ -242,12 +247,14 @@ void RegAllocBase::assign(LiveInterval &VirtReg, unsigned PhysReg) { assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment"); VRM->assignVirt2Phys(VirtReg.reg, PhysReg); PhysReg2LiveUnion[PhysReg].unify(VirtReg); + ++NumAssigned; } void RegAllocBase::unassign(LiveInterval &VirtReg, unsigned PhysReg) { assert(VRM->getPhys(VirtReg.reg) == PhysReg && "Inconsistent unassign"); PhysReg2LiveUnion[PhysReg].extract(VirtReg); VRM->clearVirt(VirtReg.reg); + ++NumUnassigned; } // Top-level driver to manage the queue of unassigned VirtRegs and call the @@ -287,6 +294,7 @@ void RegAllocBase::allocatePhysRegs() { "expect split value in virtual register"); VirtRegQ.push(std::make_pair(getPriority(SplitVirtReg), SplitVirtReg->reg)); + ++NumNewQueued; } } } diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp index ab56ec32721d..7c35ceb1f561 100644 --- a/llvm/lib/CodeGen/RegAllocGreedy.cpp +++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp @@ -22,6 +22,7 @@ #include "SplitKit.h" #include "VirtRegMap.h" #include "VirtRegRewriter.h" +#include "llvm/ADT/Statistic.h" #include "llvm/Analysis/AliasAnalysis.h" #include "llvm/Function.h" #include "llvm/PassAnalysisSupport.h" @@ -45,6 +46,11 @@ using namespace llvm; +STATISTIC(NumGlobalSplits, "Number of split global live ranges"); +STATISTIC(NumLocalSplits, "Number of split local live ranges"); +STATISTIC(NumReassigned, "Number of interferences reassigned"); +STATISTIC(NumEvicted, "Number of interferences evicted"); + static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator", createGreedyRegisterAllocator); @@ -265,6 +271,7 @@ bool RAGreedy::reassignVReg(LiveInterval &InterferingVReg, TRI->getName(OldAssign) << " to " << TRI->getName(PhysReg) << '\n'); unassign(InterferingVReg, OldAssign); assign(InterferingVReg, PhysReg); + ++NumReassigned; return true; } return false; @@ -307,6 +314,7 @@ unsigned RAGreedy::tryReassignOrEvict(LiveInterval &VirtReg, if (BestVirt) { DEBUG(dbgs() << "evicting lighter " << *BestVirt << '\n'); unassign(*BestVirt, VRM->getPhys(BestVirt->reg)); + ++NumEvicted; NewVRegs.push_back(BestVirt); return BestPhys; } @@ -782,6 +790,7 @@ void RAGreedy::splitAroundRegion(LiveInterval &VirtReg, unsigned PhysReg, // per-block segments? The current approach allows the stack region to // separate into connected components. Some components may be allocatable. SE.finish(); + ++NumGlobalSplits; if (VerifyEnabled) { MF->verify(this, "After splitting live range around region"); @@ -1094,6 +1103,7 @@ unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order, SE.useIntv(SegStart, SegStop); SE.closeIntv(); SE.finish(); + ++NumLocalSplits; return 0; }