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Fix CodeGen/arm64-microsoft-status-reg.cpp test 

Summary: This test is failing after r356499 (verified with `ninja check-clang-codegen`). Update the register selection used in the test from x0 to x8.

Reviewers: arsenm, MatzeB, efriedma

Reviewed By: efriedma

Subscribers: efriedma, wdng, javed.absar, kristof.beyls, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D59557

llvm-svn: 356517
This commit is contained in:
Jordan Rupprecht 2019-03-19 20:55:14 +00:00
parent c67a759c99
commit 993a05fe1b
1 changed files with 20 additions and 20 deletions
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40
clang/test/CodeGen/arm64-microsoft-status-reg.cpp
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@ -30,103 +30,103 @@ void _WriteStatusReg(int, __int64);
void check_ReadWriteStatusReg(__int64 v) {
__int64 ret;
ret = _ReadStatusReg(ARM64_CNTVCT);
// CHECK-ASM: mrs x0, CNTVCT_EL0
// CHECK-ASM: mrs x8, CNTVCT_EL0
// CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2:.*]])
// CHECK-IR-NEXT: store i64 %[[VAR]]
ret = _ReadStatusReg(ARM64_PMCCNTR_EL0);
// CHECK-ASM: mrs x0, PMCCNTR_EL0
// CHECK-ASM: mrs x8, PMCCNTR_EL0
// CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD3:.*]])
// CHECK-IR-NEXT: store i64 %[[VAR]]
ret = _ReadStatusReg(ARM64_PMSELR_EL0);
// CHECK-ASM: mrs x0, PMSELR_EL0
// CHECK-ASM: mrs x8, PMSELR_EL0
// CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD4:.*]])
// CHECK-IR-NEXT: store i64 %[[VAR]]
ret = _ReadStatusReg(ARM64_PMXEVCNTR_EL0);
// CHECK-ASM: mrs x0, PMXEVCNTR_EL0
// CHECK-ASM: mrs x8, PMXEVCNTR_EL0
// CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD5:.*]])
// CHECK-IR-NEXT: store i64 %[[VAR]]
ret = _ReadStatusReg(ARM64_PMXEVCNTRn_EL0(0));
// CHECK-ASM: mrs x0, PMEVCNTR0_EL0
// CHECK-ASM: mrs x8, PMEVCNTR0_EL0
// CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD6:.*]])
// CHECK-IR-NEXT: store i64 %[[VAR]]
ret = _ReadStatusReg(ARM64_PMXEVCNTRn_EL0(1));
// CHECK-ASM: mrs x0, PMEVCNTR1_EL0
// CHECK-ASM: mrs x8, PMEVCNTR1_EL0
// CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD7:.*]])
// CHECK-IR-NEXT: store i64 %[[VAR]]
ret = _ReadStatusReg(ARM64_PMXEVCNTRn_EL0(30));
// CHECK-ASM: mrs x0, PMEVCNTR30_EL0
// CHECK-ASM: mrs x8, PMEVCNTR30_EL0
// CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD8:.*]])
// CHECK-IR-NEXT: store i64 %[[VAR]]
ret = _ReadStatusReg(ARM64_TPIDR_EL0);
// CHECK-ASM: mrs x0, TPIDR_EL0
// CHECK-ASM: mrs x8, TPIDR_EL0
// CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD9:.*]])
// CHECK-IR-NEXT: store i64 %[[VAR]]
ret = _ReadStatusReg(ARM64_TPIDRRO_EL0);
// CHECK-ASM: mrs x0, TPIDRRO_EL0
// CHECK-ASM: mrs x8, TPIDRRO_EL0
// CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD10:.*]])
// CHECK-IR-NEXT: store i64 %[[VAR]]
ret = _ReadStatusReg(ARM64_TPIDR_EL1);
// CHECK-ASM: mrs x0, TPIDR_EL1
// CHECK-ASM: mrs x8, TPIDR_EL1
// CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD11:.*]])
// CHECK-IR-NEXT: store i64 %[[VAR]]
_WriteStatusReg(ARM64_CNTVCT, v);
// CHECK-ASM: msr S3_3_C14_C0_2, x0
// CHECK-ASM: msr S3_3_C14_C0_2, x8
// CHECK-IR: %[[VAR:.*]] = load i64,
// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD2:.*]], i64 %[[VAR]])
_WriteStatusReg(ARM64_PMCCNTR_EL0, v);
// CHECK-ASM: msr PMCCNTR_EL0, x0
// CHECK-ASM: msr PMCCNTR_EL0, x8
// CHECK-IR: %[[VAR:.*]] = load i64,
// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD3:.*]], i64 %[[VAR]])
_WriteStatusReg(ARM64_PMSELR_EL0, v);
// CHECK-ASM: msr PMSELR_EL0, x0
// CHECK-ASM: msr PMSELR_EL0, x8
// CHECK-IR: %[[VAR:.*]] = load i64,
// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD4:.*]], i64 %[[VAR]])
_WriteStatusReg(ARM64_PMXEVCNTR_EL0, v);
// CHECK-ASM: msr PMXEVCNTR_EL0, x0
// CHECK-ASM: msr PMXEVCNTR_EL0, x8
// CHECK-IR: %[[VAR:.*]] = load i64,
// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD5:.*]], i64 %[[VAR]])
_WriteStatusReg(ARM64_PMXEVCNTRn_EL0(0), v);
// CHECK-ASM: msr PMEVCNTR0_EL0, x0
// CHECK-ASM: msr PMEVCNTR0_EL0, x8
// CHECK-IR: %[[VAR:.*]] = load i64,
// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD6:.*]], i64 %[[VAR]])
_WriteStatusReg(ARM64_PMXEVCNTRn_EL0(1), v);
// CHECK-ASM: msr PMEVCNTR1_EL0, x0
// CHECK-ASM: msr PMEVCNTR1_EL0, x8
// CHECK-IR: %[[VAR:.*]] = load i64,
// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD7:.*]], i64 %[[VAR]])
_WriteStatusReg(ARM64_PMXEVCNTRn_EL0(30), v);
// CHECK-ASM: msr PMEVCNTR30_EL0, x0
// CHECK-ASM: msr PMEVCNTR30_EL0, x8
// CHECK-IR: %[[VAR:.*]] = load i64,
// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD8:.*]], i64 %[[VAR]])
_WriteStatusReg(ARM64_TPIDR_EL0, v);
// CHECK-ASM: msr TPIDR_EL0, x0
// CHECK-ASM: msr TPIDR_EL0, x8
// CHECK-IR: %[[VAR:.*]] = load i64,
// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD9:.*]], i64 %[[VAR]])
_WriteStatusReg(ARM64_TPIDRRO_EL0, v);
// CHECK-ASM: msr TPIDRRO_EL0, x0
// CHECK-ASM: msr TPIDRRO_EL0, x8
// CHECK-IR: %[[VAR:.*]] = load i64,
// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD10:.*]], i64 %[[VAR]])
_WriteStatusReg(ARM64_TPIDR_EL1, v);
// CHECK-ASM: msr TPIDR_EL1, x0
// CHECK-ASM: msr TPIDR_EL1, x8
// CHECK-IR: %[[VAR:.*]] = load i64,
// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD11:.*]], i64 %[[VAR]])
}