[AArch64][GlobalISel] Actually select G_INTRINSIC_TRUNC
Apparently FileCheck wasn't actually matching the fallback check lines in arm64-vfloatintrinsics.ll properly. So, there were selection fallbacks for G_INTRINSIC_TRUNC there. Actually hook it up into AArch64InstructionSelector.cpp and write a proper selection test. I guess I'll figure out the FileCheck magic to make the fallback checks work properly in arm64-vfloatintrinsics.ll. llvm-svn: 359030
This commit is contained in:
Jessica Paquette
parent
108cbbc262
commit
991cb39242
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@ -102,7 +102,7 @@ private:
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bool selectIntrinsicWithSideEffects(MachineInstr &I,
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MachineRegisterInfo &MRI) const;
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bool selectVectorICmp(MachineInstr &I, MachineRegisterInfo &MRI) const;
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bool selectIntrinsicTrunc(MachineInstr &I, MachineRegisterInfo &MRI) const;
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unsigned emitConstantPoolEntry(Constant *CPVal, MachineFunction &MF) const;
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MachineInstr *emitLoadFromConstantPool(Constant *CPVal,
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MachineIRBuilder &MIRBuilder) const;
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@ -1847,6 +1847,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I,
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return constrainSelectedInstRegOperands(*MovMI, TII, TRI, RBI);
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}
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}
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case TargetOpcode::G_INTRINSIC_TRUNC:
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return selectIntrinsicTrunc(I, MRI);
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case TargetOpcode::G_BUILD_VECTOR:
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return selectBuildVector(I, MRI);
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case TargetOpcode::G_MERGE_VALUES:
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@ -1866,6 +1868,61 @@ bool AArch64InstructionSelector::select(MachineInstr &I,
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return false;
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}
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bool AArch64InstructionSelector::selectIntrinsicTrunc(
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MachineInstr &I, MachineRegisterInfo &MRI) const {
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const LLT SrcTy = MRI.getType(I.getOperand(0).getReg());
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// Select the correct opcode.
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unsigned Opc = 0;
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if (!SrcTy.isVector()) {
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switch (SrcTy.getSizeInBits()) {
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default:
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case 16:
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Opc = AArch64::FRINTZHr;
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break;
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case 32:
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Opc = AArch64::FRINTZSr;
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break;
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case 64:
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Opc = AArch64::FRINTZDr;
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break;
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}
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} else {
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unsigned NumElts = SrcTy.getNumElements();
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switch (SrcTy.getElementType().getSizeInBits()) {
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default:
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break;
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case 16:
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if (NumElts == 4)
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Opc = AArch64::FRINTZv4f16;
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else if (NumElts == 8)
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Opc = AArch64::FRINTZv8f16;
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break;
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case 32:
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if (NumElts == 2)
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Opc = AArch64::FRINTZv2f32;
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else if (NumElts == 4)
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Opc = AArch64::FRINTZv4f32;
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break;
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case 64:
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if (NumElts == 2)
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Opc = AArch64::FRINTZv2f64;
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break;
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}
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}
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if (!Opc) {
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// Didn't get an opcode above, bail.
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LLVM_DEBUG(dbgs() << "Unsupported type for G_INTRINSIC_TRUNC!\n");
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return false;
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}
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// Legalization would have set us up perfectly for this; we just need to
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// set the opcode and move on.
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I.setDesc(TII.get(Opc));
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return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
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}
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bool AArch64InstructionSelector::selectVectorICmp(
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MachineInstr &I, MachineRegisterInfo &MRI) const {
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unsigned DstReg = I.getOperand(0).getReg();
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@ -0,0 +1,198 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc %s -verify-machineinstrs -mtriple=aarch64-unknown-unknown -run-pass=instruction-select -mattr=+fullfp16 -o - | FileCheck %s
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...
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---
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name: test_f64.intrinsic_trunc
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: test_f64.intrinsic_trunc
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[FRINTZDr:%[0-9]+]]:fpr64 = FRINTZDr [[COPY]]
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; CHECK: $d0 = COPY [[FRINTZDr]]
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; CHECK: RET_ReallyLR implicit $d0
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%0:fpr(s64) = COPY $d0
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%1:fpr(s64) = G_INTRINSIC_TRUNC %0
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$d0 = COPY %1(s64)
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RET_ReallyLR implicit $d0
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...
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---
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name: test_f32.intrinsic_trunc
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $s0
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; CHECK-LABEL: name: test_f32.intrinsic_trunc
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; CHECK: liveins: $s0
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; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
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; CHECK: [[FRINTZSr:%[0-9]+]]:fpr32 = FRINTZSr [[COPY]]
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; CHECK: $s0 = COPY [[FRINTZSr]]
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; CHECK: RET_ReallyLR implicit $s0
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%0:fpr(s32) = COPY $s0
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%1:fpr(s32) = G_INTRINSIC_TRUNC %0
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$s0 = COPY %1(s32)
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RET_ReallyLR implicit $s0
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...
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---
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name: test_f16.intrinsic_trunc
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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frameInfo:
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maxCallFrameSize: 0
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $h0
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; CHECK-LABEL: name: test_f16.intrinsic_trunc
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; CHECK: liveins: $h0
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; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
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; CHECK: [[FRINTZHr:%[0-9]+]]:fpr16 = FRINTZHr [[COPY]]
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; CHECK: $h0 = COPY [[FRINTZHr]]
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; CHECK: RET_ReallyLR implicit $h0
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%0:fpr(s16) = COPY $h0
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%1:fpr(s16) = G_INTRINSIC_TRUNC %0
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$h0 = COPY %1(s16)
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RET_ReallyLR implicit $h0
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...
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---
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name: test_v4f16.intrinsic_trunc
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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frameInfo:
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maxCallFrameSize: 0
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: test_v4f16.intrinsic_trunc
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[FRINTZv4f16_:%[0-9]+]]:fpr64 = FRINTZv4f16 [[COPY]]
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; CHECK: $d0 = COPY [[FRINTZv4f16_]]
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; CHECK: RET_ReallyLR implicit $d0
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%0:fpr(<4 x s16>) = COPY $d0
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%1:fpr(<4 x s16>) = G_INTRINSIC_TRUNC %0
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$d0 = COPY %1(<4 x s16>)
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RET_ReallyLR implicit $d0
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...
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---
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name: test_v8f16.intrinsic_trunc
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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frameInfo:
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maxCallFrameSize: 0
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: test_v8f16.intrinsic_trunc
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[FRINTZv8f16_:%[0-9]+]]:fpr128 = FRINTZv8f16 [[COPY]]
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; CHECK: $q0 = COPY [[FRINTZv8f16_]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<8 x s16>) = COPY $q0
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%1:fpr(<8 x s16>) = G_INTRINSIC_TRUNC %0
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$q0 = COPY %1(<8 x s16>)
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RET_ReallyLR implicit $q0
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...
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---
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name: test_v2f32.intrinsic_trunc
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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frameInfo:
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maxCallFrameSize: 0
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: test_v2f32.intrinsic_trunc
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[FRINTZv2f32_:%[0-9]+]]:fpr64 = FRINTZv2f32 [[COPY]]
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; CHECK: $d0 = COPY [[FRINTZv2f32_]]
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; CHECK: RET_ReallyLR implicit $d0
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%0:fpr(<2 x s32>) = COPY $d0
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%1:fpr(<2 x s32>) = G_INTRINSIC_TRUNC %0
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$d0 = COPY %1(<2 x s32>)
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RET_ReallyLR implicit $d0
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...
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---
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name: test_v4f32.intrinsic_trunc
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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frameInfo:
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maxCallFrameSize: 0
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: test_v4f32.intrinsic_trunc
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[FRINTZv4f32_:%[0-9]+]]:fpr128 = FRINTZv4f32 [[COPY]]
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; CHECK: $q0 = COPY [[FRINTZv4f32_]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<4 x s32>) = COPY $q0
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%1:fpr(<4 x s32>) = G_INTRINSIC_TRUNC %0
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$q0 = COPY %1(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: test_v2f64.intrinsic_trunc
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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frameInfo:
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maxCallFrameSize: 0
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: test_v2f64.intrinsic_trunc
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[FRINTZv2f64_:%[0-9]+]]:fpr128 = FRINTZv2f64 [[COPY]]
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; CHECK: $q0 = COPY [[FRINTZv2f64_]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<2 x s64>) = COPY $q0
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%1:fpr(<2 x s64>) = G_INTRINSIC_TRUNC %0
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$q0 = COPY %1(<2 x s64>)
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RET_ReallyLR implicit $q0
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