Expand the sel pseudo/macro. This generates basic blocks where previously
there were inline br .+4 instructions. Soon everything can enjoy the full instruction scheduling experience. llvm-svn: 175718
This commit is contained in:
Reed Kotler
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dff9587640
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97ba5f2772
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@ -76,6 +76,10 @@ class F2RI16_ins<bits<5> _op, string asmstr,
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let Constraints = "$rx_ = $rx";
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}
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class FRI16_B_ins<bits<5> _op, string asmstr,
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InstrItinClass itin>:
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FRI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm),
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!strconcat(asmstr, "\t$rx, $imm # 16 bit inst"), [], itin>;
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//
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// Compare a register and immediate and place result in CC
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// Implicit use of T8
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@ -362,6 +366,7 @@ class Sel<string op>:
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!strconcat(op, "\t$rt, .+4\n\t\n\tmove $rd, $rs"), []> {
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//let isCodeGenOnly=1;
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let Constraints = "$rd = $rd_";
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let usesCustomInserter = 1;
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}
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//
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@ -518,6 +523,14 @@ def AdduRxRyRz16: FRRR16_ins<01, "addu", IIAlu>, ArithLogic16Defs<1>;
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def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIAlu>, ArithLogic16Defs<1>;
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//
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// Format: BEQZ rx, offset MIPS16e
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// Purpose: Branch on Equal to Zero
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// To test a GPR then do a PC-relative conditional branch.
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//
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def BeqzRxImm16: FRI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16;
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//
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// Format: BEQZ rx, offset MIPS16e
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// Purpose: Branch on Equal to Zero (Extended)
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@ -531,6 +544,13 @@ def BeqzRxImmX16: FEXT_RI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16;
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//
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def BimmX16: FEXT_I16_ins<0b00010, "b", IIAlu>, branch16;
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//
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// Format: BNEZ rx, offset MIPS16e
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// Purpose: Branch on Not Equal to Zero
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// To test a GPR then do a PC-relative conditional branch.
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//
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def BnezRxImm16: FRI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16;
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//
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// Format: BNEZ rx, offset MIPS16e
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// Purpose: Branch on Not Equal to Zero (Extended)
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@ -55,6 +55,12 @@ Mips16HardFloat("mips16-hard-float", cl::NotHidden,
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cl::desc("MIPS: mips16 hard float enable."),
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cl::init(false));
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static cl::opt<bool> DontExpandCondPseudos16(
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"mips16-dont-expand-cond-pseudo",
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cl::init(false),
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cl::desc("Dont expand conditional move related "
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"pseudos for Mips 16"),
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cl::Hidden);
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static const uint16_t O32IntRegs[4] = {
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@ -1230,11 +1236,74 @@ MipsTargetLowering::EmitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
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return Sink;
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}
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MachineBasicBlock *MipsTargetLowering::EmitSel16(unsigned Opc, MachineInstr *MI,
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MachineBasicBlock *BB) const {
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if (DontExpandCondPseudos16)
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return BB;
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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DebugLoc dl = MI->getDebugLoc();
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// To "insert" a SELECT_CC instruction, we actually have to insert the
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// diamond control-flow pattern. The incoming instruction knows the
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// destination vreg to set, the condition code register to branch on, the
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// true/false values to select between, and a branch opcode to use.
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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MachineFunction::iterator It = BB;
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++It;
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// thisMBB:
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// ...
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// TrueVal = ...
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// setcc r1, r2, r3
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// bNE r1, r0, copy1MBB
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// fallthrough --> copy0MBB
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MachineBasicBlock *thisMBB = BB;
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MachineFunction *F = BB->getParent();
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MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
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F->insert(It, copy0MBB);
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F->insert(It, sinkMBB);
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// Transfer the remainder of BB and its successor edges to sinkMBB.
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sinkMBB->splice(sinkMBB->begin(), BB,
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llvm::next(MachineBasicBlock::iterator(MI)),
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BB->end());
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sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
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// Next, add the true and fallthrough blocks as its successors.
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BB->addSuccessor(copy0MBB);
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BB->addSuccessor(sinkMBB);
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BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(3).getReg())
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.addMBB(sinkMBB);
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// copy0MBB:
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// %FalseValue = ...
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// # fallthrough to sinkMBB
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BB = copy0MBB;
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// Update machine-CFG edges
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BB->addSuccessor(sinkMBB);
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// sinkMBB:
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// %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
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// ...
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BB = sinkMBB;
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BuildMI(*BB, BB->begin(), dl,
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TII->get(Mips::PHI), MI->getOperand(0).getReg())
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.addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
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.addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
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MI->eraseFromParent(); // The pseudo instruction is gone now.
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return BB;
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}
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MachineBasicBlock *
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MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *BB) const {
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switch (MI->getOpcode()) {
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default: llvm_unreachable("Unexpected instr type to insert");
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default:
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llvm_unreachable("Unexpected instr type to insert");
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case Mips::ATOMIC_LOAD_ADD_I8:
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case Mips::ATOMIC_LOAD_ADD_I8_P8:
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return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
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@ -1340,6 +1409,10 @@ MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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return EmitAtomicCmpSwap(MI, BB, 8);
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case Mips::BPOSGE32_PSEUDO:
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return EmitBPOSGE32(MI, BB);
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case Mips::SelBeqZ:
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return EmitSel16(Mips::BeqzRxImm16, MI, BB);
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case Mips::SelBneZ:
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return EmitSel16(Mips::BnezRxImm16, MI, BB);
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}
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}
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@ -404,6 +404,9 @@ namespace llvm {
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MachineBasicBlock *BB, unsigned Size) const;
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MachineBasicBlock *EmitAtomicCmpSwapPartword(MachineInstr *MI,
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MachineBasicBlock *BB, unsigned Size) const;
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MachineBasicBlock *EmitSel16(unsigned Opc, MachineInstr *MI,
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MachineBasicBlock *BB) const;
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};
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}
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@ -67,7 +67,7 @@ entry:
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%2 = load i32* @f, align 4
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%cond = select i1 %cmp, i32 %1, i32 %2
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store i32 %cond, i32* @z1, align 4
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; 16: beqz ${{[0-9]+}}, .+4
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; 16: beqz ${{[0-9]+}}, $BB{{[0-9]+}}_{{[0-9]}}
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; 16: move ${{[0-9]+}}, ${{[0-9]+}}
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%3 = load i32* @b, align 4
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%cmp1 = icmp eq i32 %3, 0
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@ -238,7 +238,7 @@ entry:
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%2 = load i32* @t, align 4
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%cond = select i1 %cmp, i32 %1, i32 %2
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store i32 %cond, i32* @z1, align 4
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; 16: bnez ${{[0-9]+}}, .+4
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; 16: bnez ${{[0-9]+}}, $BB{{[0-9]+}}_{{[0-9]}}
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; 16: move ${{[0-9]+}}, ${{[0-9]+}}
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%3 = load i32* @b, align 4
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%cmp1 = icmp ne i32 %3, 0
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@ -260,7 +260,7 @@ entry:
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%2 = load i32* @t, align 4
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%cond = select i1 %tobool, i32 %1, i32 %2
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store i32 %cond, i32* @z1, align 4
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; 16: bnez ${{[0-9]+}}, .+4
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; 16: bnez ${{[0-9]+}}, $BB{{[0-9]+}}_{{[0-9]}}
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; 16: move ${{[0-9]+}}, ${{[0-9]+}}
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%3 = load i32* @b, align 4
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%tobool1 = icmp ne i32 %3, 0
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