[PowerPC] Fix the wrong implementation of builtin vec_rlnm.

llvm-svn: 291702
This commit is contained in:
Tony Jiang 2017-01-11 20:59:42 +00:00
parent 8396265655
commit 974e4c7899
2 changed files with 12 additions and 6 deletions

View File

@ -7664,13 +7664,15 @@ vec_rlmi(vector unsigned long long __a, vector unsigned long long __b,
static __inline__ vector unsigned int __ATTRS_o_ai
vec_rlnm(vector unsigned int __a, vector unsigned int __b,
vector unsigned int __c) {
return __builtin_altivec_vrlwnm(__a, __b) & __c;
vector unsigned int OneByte = { 0x8, 0x8, 0x8, 0x8 };
return __builtin_altivec_vrlwnm(__a, ((__c << OneByte) | __b));
}
static __inline__ vector unsigned long long __ATTRS_o_ai
vec_rlnm(vector unsigned long long __a, vector unsigned long long __b,
vector unsigned long long __c) {
return __builtin_altivec_vrldnm(__a, __b) & __c;
vector unsigned long long OneByte = { 0x8, 0x8 };
return __builtin_altivec_vrldnm(__a, ((__c << OneByte) | __b));
}
#endif

View File

@ -868,20 +868,24 @@ vector unsigned long long test76(void) {
return vec_rlmi(vula, vula, vula);
}
vector unsigned int test77(void) {
// CHECK-BE: %[[RES1:.+]] = shl <4 x i32
// CHECK-BE: %[[RES2:.+]] = or <4 x i32> %[[RES1]]
// CHECK-BE: @llvm.ppc.altivec.vrlwnm(<4 x i32
// CHECK-BE: and <4 x i32
// CHECK-BE: ret <4 x i32>
// CHECK: %[[RES1:.+]] = shl <4 x i32
// CHECK: %[[RES2:.+]] = or <4 x i32> %[[RES1]]
// CHECK: @llvm.ppc.altivec.vrlwnm(<4 x i32
// CHECK: and <4 x i32
// CHECK: ret <4 x i32>
return vec_rlnm(vuia, vuia, vuia);
}
vector unsigned long long test78(void) {
// CHECK-BE: %[[RES1:.+]] = shl <2 x i64
// CHECK-BE: %[[RES2:.+]] = or <2 x i64> %[[RES1]]
// CHECK-BE: @llvm.ppc.altivec.vrldnm(<2 x i64
// CHECK-BE: and <2 x i64
// CHECK-BE-NEXT: ret <2 x i64>
// CHECK: %[[RES1:.+]] = shl <2 x i64
// CHECK: %[[RES2:.+]] = or <2 x i64> %[[RES1]]
// CHECK: @llvm.ppc.altivec.vrldnm(<2 x i64
// CHECK: and <2 x i64
// CHECK-NEXT: ret <2 x i64>
return vec_rlnm(vula, vula, vula);
}