[PowerPC] Fix the wrong implementation of builtin vec_rlnm.
llvm-svn: 291702
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@ -7664,13 +7664,15 @@ vec_rlmi(vector unsigned long long __a, vector unsigned long long __b,
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static __inline__ vector unsigned int __ATTRS_o_ai
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vec_rlnm(vector unsigned int __a, vector unsigned int __b,
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vector unsigned int __c) {
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return __builtin_altivec_vrlwnm(__a, __b) & __c;
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vector unsigned int OneByte = { 0x8, 0x8, 0x8, 0x8 };
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return __builtin_altivec_vrlwnm(__a, ((__c << OneByte) | __b));
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}
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static __inline__ vector unsigned long long __ATTRS_o_ai
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vec_rlnm(vector unsigned long long __a, vector unsigned long long __b,
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vector unsigned long long __c) {
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return __builtin_altivec_vrldnm(__a, __b) & __c;
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vector unsigned long long OneByte = { 0x8, 0x8 };
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return __builtin_altivec_vrldnm(__a, ((__c << OneByte) | __b));
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}
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#endif
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@ -868,20 +868,24 @@ vector unsigned long long test76(void) {
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return vec_rlmi(vula, vula, vula);
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}
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vector unsigned int test77(void) {
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// CHECK-BE: %[[RES1:.+]] = shl <4 x i32
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// CHECK-BE: %[[RES2:.+]] = or <4 x i32> %[[RES1]]
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// CHECK-BE: @llvm.ppc.altivec.vrlwnm(<4 x i32
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// CHECK-BE: and <4 x i32
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// CHECK-BE: ret <4 x i32>
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// CHECK: %[[RES1:.+]] = shl <4 x i32
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// CHECK: %[[RES2:.+]] = or <4 x i32> %[[RES1]]
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// CHECK: @llvm.ppc.altivec.vrlwnm(<4 x i32
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// CHECK: and <4 x i32
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// CHECK: ret <4 x i32>
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return vec_rlnm(vuia, vuia, vuia);
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}
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vector unsigned long long test78(void) {
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// CHECK-BE: %[[RES1:.+]] = shl <2 x i64
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// CHECK-BE: %[[RES2:.+]] = or <2 x i64> %[[RES1]]
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// CHECK-BE: @llvm.ppc.altivec.vrldnm(<2 x i64
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// CHECK-BE: and <2 x i64
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// CHECK-BE-NEXT: ret <2 x i64>
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// CHECK: %[[RES1:.+]] = shl <2 x i64
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// CHECK: %[[RES2:.+]] = or <2 x i64> %[[RES1]]
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// CHECK: @llvm.ppc.altivec.vrldnm(<2 x i64
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// CHECK: and <2 x i64
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// CHECK-NEXT: ret <2 x i64>
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return vec_rlnm(vula, vula, vula);
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}
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