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[X86][AVX512] Add support for AVX512 VMOVQ (load) shuffle decoding 

llvm-svn: 259496
This commit is contained in:
Simon Pilgrim 2016-02-02 13:32:56 +00:00
parent cc77950b2b
commit 96fe4ef5f7
5 changed files with 37 additions and 108 deletions
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1
llvm/lib/Target/X86/InstPrinter/X86InstComments.cpp
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@ -687,6 +687,7 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
case X86::MOVZQI2PQIrm:
case X86::MOVZPQILo2PQIrm:
case X86::VMOVQI2PQIrm:
case X86::VMOVQI2PQIZrm:
case X86::VMOVZQI2PQIrm:
case X86::VMOVZPQILo2PQIrm:
case X86::VMOVZPQILo2PQIZrm:

18
llvm/test/CodeGen/X86/merge-consecutive-loads-256.ll
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@ -162,20 +162,10 @@ define <4 x i64> @merge_4i64_i64_1234(i64* %ptr) nounwind uwtable noinline ssp {
}
define <4 x i64> @merge_4i64_i64_1zzu(i64* %ptr) nounwind uwtable noinline ssp {
; AVX1-LABEL: merge_4i64_i64_1zzu:
; AVX1: # BB#0:
; AVX1-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
; AVX1-NEXT: retq
;
; AVX2-LABEL: merge_4i64_i64_1zzu:
; AVX2: # BB#0:
; AVX2-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
; AVX2-NEXT: retq
;
; AVX512F-LABEL: merge_4i64_i64_1zzu:
; AVX512F: # BB#0:
; AVX512F-NEXT: vmovq 8(%rdi), %xmm0
; AVX512F-NEXT: retq
; AVX-LABEL: merge_4i64_i64_1zzu:
; AVX: # BB#0:
; AVX-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
; AVX-NEXT: retq
%ptr0 = getelementptr inbounds i64, i64* %ptr, i64 1
%val0 = load i64, i64* %ptr0
%res0 = insertelement <4 x i64> undef, i64 %val0, i32 0

8
llvm/test/CodeGen/X86/merge-consecutive-loads-512.ll
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@ -137,7 +137,7 @@ define <8 x i64> @merge_8i64_i64_56zz9uzz(i64* %ptr) nounwind uwtable noinline s
; ALL-NEXT: vmovdqu 40(%rdi), %xmm0
; ALL-NEXT: vpxor %xmm1, %xmm1, %xmm1
; ALL-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
; ALL-NEXT: vmovq 72(%rdi), %xmm1
; ALL-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
; ALL-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
; ALL-NEXT: retq
%ptr0 = getelementptr inbounds i64, i64* %ptr, i64 5
@ -159,11 +159,11 @@ define <8 x i64> @merge_8i64_i64_56zz9uzz(i64* %ptr) nounwind uwtable noinline s
define <8 x i64> @merge_8i64_i64_1u3u5zu8(i64* %ptr) nounwind uwtable noinline ssp {
; ALL-LABEL: merge_8i64_i64_1u3u5zu8:
; ALL: # BB#0:
; ALL-NEXT: vmovq 40(%rdi), %xmm0
; ALL-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
; ALL-NEXT: vpbroadcastq 64(%rdi), %xmm1
; ALL-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
; ALL-NEXT: vmovq 8(%rdi), %xmm1
; ALL-NEXT: vmovq 24(%rdi), %xmm2
; ALL-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
; ALL-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero
; ALL-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1
; ALL-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
; ALL-NEXT: retq

80
llvm/test/CodeGen/X86/vector-shuffle-128-v2.ll
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@ -953,7 +953,7 @@ define <2 x i64> @shuffle_v2i64_bitcast_z123(<2 x i64> %x) {
;
; AVX512VL-LABEL: shuffle_v2i64_bitcast_z123:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vmovss {{.*}}(%rip), %xmm1
; AVX512VL-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; AVX512VL-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
; AVX512VL-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX512VL-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
@ -986,20 +986,10 @@ define <2 x i64> @insert_mem_and_zero_v2i64(i64* %ptr) {
; SSE-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
; SSE-NEXT: retq
;
; AVX1-LABEL: insert_mem_and_zero_v2i64:
; AVX1: # BB#0:
; AVX1-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
; AVX1-NEXT: retq
;
; AVX2-LABEL: insert_mem_and_zero_v2i64:
; AVX2: # BB#0:
; AVX2-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
; AVX2-NEXT: retq
;
; AVX512VL-LABEL: insert_mem_and_zero_v2i64:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vmovq (%rdi), %xmm0
; AVX512VL-NEXT: retq
; AVX-LABEL: insert_mem_and_zero_v2i64:
; AVX: # BB#0:
; AVX-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
; AVX-NEXT: retq
%a = load i64, i64* %ptr
%v = insertelement <2 x i64> undef, i64 %a, i32 0
%shuffle = shufflevector <2 x i64> %v, <2 x i64> zeroinitializer, <2 x i32> <i32 0, i32 3>
@ -1027,20 +1017,10 @@ define <2 x double> @insert_mem_and_zero_v2f64(double* %ptr) {
; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; SSE-NEXT: retq
;
; AVX1-LABEL: insert_mem_and_zero_v2f64:
; AVX1: # BB#0:
; AVX1-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX1-NEXT: retq
;
; AVX2-LABEL: insert_mem_and_zero_v2f64:
; AVX2: # BB#0:
; AVX2-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX2-NEXT: retq
;
; AVX512VL-LABEL: insert_mem_and_zero_v2f64:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vmovsd (%rdi), %xmm0
; AVX512VL-NEXT: retq
; AVX-LABEL: insert_mem_and_zero_v2f64:
; AVX: # BB#0:
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX-NEXT: retq
%a = load double, double* %ptr
%v = insertelement <2 x double> undef, double %a, i32 0
%shuffle = shufflevector <2 x double> %v, <2 x double> zeroinitializer, <2 x i32> <i32 0, i32 3>
@ -1130,7 +1110,7 @@ define <2 x i64> @insert_mem_lo_v2i64(i64* %ptr, <2 x i64> %b) {
;
; AVX512VL-LABEL: insert_mem_lo_v2i64:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vmovq (%rdi), %xmm1
; AVX512VL-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
; AVX512VL-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
; AVX512VL-NEXT: retq
%a = load i64, i64* %ptr
@ -1163,23 +1143,11 @@ define <2 x i64> @insert_mem_hi_v2i64(i64* %ptr, <2 x i64> %b) {
; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE-NEXT: retq
;
; AVX1-LABEL: insert_mem_hi_v2i64:
; AVX1: # BB#0:
; AVX1-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX1-NEXT: retq
;
; AVX2-LABEL: insert_mem_hi_v2i64:
; AVX2: # BB#0:
; AVX2-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX2-NEXT: retq
;
; AVX512VL-LABEL: insert_mem_hi_v2i64:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vmovq (%rdi), %xmm1
; AVX512VL-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX512VL-NEXT: retq
; AVX-LABEL: insert_mem_hi_v2i64:
; AVX: # BB#0:
; AVX-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX-NEXT: retq
%a = load i64, i64* %ptr
%v = insertelement <2 x i64> undef, i64 %a, i32 0
%shuffle = shufflevector <2 x i64> %v, <2 x i64> %b, <2 x i32> <i32 2, i32 0>
@ -1193,20 +1161,10 @@ define <2 x double> @insert_reg_lo_v2f64(double %a, <2 x double> %b) {
; SSE-NEXT: movapd %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX1-LABEL: insert_reg_lo_v2f64:
; AVX1: # BB#0:
; AVX1-NEXT: vmovsd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
; AVX1-NEXT: retq
;
; AVX2-LABEL: insert_reg_lo_v2f64:
; AVX2: # BB#0:
; AVX2-NEXT: vmovsd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
; AVX2-NEXT: retq
;
; AVX512VL-LABEL: insert_reg_lo_v2f64:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vmovsd %xmm0, %xmm1, %xmm0
; AVX512VL-NEXT: retq
; AVX-LABEL: insert_reg_lo_v2f64:
; AVX: # BB#0:
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
; AVX-NEXT: retq
%v = insertelement <2 x double> undef, double %a, i32 0
%shuffle = shufflevector <2 x double> %v, <2 x double> %b, <2 x i32> <i32 0, i32 3>
ret <2 x double> %shuffle

38
llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll
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@ -1212,20 +1212,10 @@ define <4 x i64> @insert_reg_and_zero_v4i64(i64 %a) {
}
define <4 x i64> @insert_mem_and_zero_v4i64(i64* %ptr) {
; AVX1-LABEL: insert_mem_and_zero_v4i64:
; AVX1: # BB#0:
; AVX1-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
; AVX1-NEXT: retq
;
; AVX2-LABEL: insert_mem_and_zero_v4i64:
; AVX2: # BB#0:
; AVX2-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
; AVX2-NEXT: retq
;
; AVX512VL-LABEL: insert_mem_and_zero_v4i64:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vmovq (%rdi), %xmm0
; AVX512VL-NEXT: retq
; ALL-LABEL: insert_mem_and_zero_v4i64:
; ALL: # BB#0:
; ALL-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
; ALL-NEXT: retq
%a = load i64, i64* %ptr
%v = insertelement <4 x i64> undef, i64 %a, i64 0
%shuffle = shufflevector <4 x i64> %v, <4 x i64> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
@ -1248,7 +1238,7 @@ define <4 x double> @insert_reg_and_zero_v4f64(double %a) {
; AVX512VL-LABEL: insert_reg_and_zero_v4f64:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vxorpd %xmm1, %xmm1, %xmm1
; AVX512VL-NEXT: vmovsd %xmm0, %xmm1, %xmm0
; AVX512VL-NEXT: vmovsd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
; AVX512VL-NEXT: retq
%v = insertelement <4 x double> undef, double %a, i32 0
%shuffle = shufflevector <4 x double> %v, <4 x double> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
@ -1256,20 +1246,10 @@ define <4 x double> @insert_reg_and_zero_v4f64(double %a) {
}
define <4 x double> @insert_mem_and_zero_v4f64(double* %ptr) {
; AVX1-LABEL: insert_mem_and_zero_v4f64:
; AVX1: # BB#0:
; AVX1-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX1-NEXT: retq
;
; AVX2-LABEL: insert_mem_and_zero_v4f64:
; AVX2: # BB#0:
; AVX2-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX2-NEXT: retq
;
; AVX512VL-LABEL: insert_mem_and_zero_v4f64:
; AVX512VL: # BB#0:
; AVX512VL-NEXT: vmovsd (%rdi), %xmm0
; AVX512VL-NEXT: retq
; ALL-LABEL: insert_mem_and_zero_v4f64:
; ALL: # BB#0:
; ALL-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; ALL-NEXT: retq
%a = load double, double* %ptr
%v = insertelement <4 x double> undef, double %a, i32 0
%shuffle = shufflevector <4 x double> %v, <4 x double> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 6, i32 7>