From 96f87069c4f02f727e635d77fb326eb2079b4195 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Fri, 31 Aug 2012 15:34:59 +0000 Subject: [PATCH] Don't enforce ordered inline asm operands. I was too optimistic, inline asm can have tied operands that don't follow the def order. Fixes PR13742. llvm-svn: 162998 --- llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 10 ---------- llvm/test/CodeGen/X86/inline-asm-tied.ll | 9 +++++++++ 2 files changed, 9 insertions(+), 10 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp index 4d09c444945c..5399a51557b2 100644 --- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp @@ -895,7 +895,6 @@ EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned, // Remember to operand index of the group flags. SmallVector GroupIdx; - unsigned PrevDefGroup = 0; // Add all of the operand registers to the instruction. for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) { @@ -944,15 +943,6 @@ EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned, if (InlineAsm::getKind(Flags) == InlineAsm::Kind_RegUse) { unsigned DefGroup = 0; if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) { - // Check that the def groups are monotonically increasing. - // Otherwise, the tied uses and defs won't line up, and - // MI::findTiedOperandIdx() will find the wrong operand. This - // should be automatically enforced by the front ends when - // translating "+" constraints into tied def+use pairs. - assert(DefGroup >= PrevDefGroup && - "Tied inline asm operands must be in increasing order."); - PrevDefGroup = DefGroup; - unsigned DefIdx = GroupIdx[DefGroup] + 1; unsigned UseIdx = GroupIdx.back() + 1; for (unsigned j = 0; j != NumVals; ++j) { diff --git a/llvm/test/CodeGen/X86/inline-asm-tied.ll b/llvm/test/CodeGen/X86/inline-asm-tied.ll index 91576fb09ec2..597236e36281 100644 --- a/llvm/test/CodeGen/X86/inline-asm-tied.ll +++ b/llvm/test/CodeGen/X86/inline-asm-tied.ll @@ -19,3 +19,12 @@ entry: %1 = load i64* %retval ; [#uses=1] ret i64 %1 } + +; The tied operands are not necessarily in the same order as the defs. +; PR13742 +define i64 @swapped(i64 %x, i64 %y) nounwind { +entry: + %x0 = call { i64, i64 } asm "foo", "=r,=r,1,0,~{dirflag},~{fpsr},~{flags}"(i64 %x, i64 %y) nounwind + %x1 = extractvalue { i64, i64 } %x0, 0 + ret i64 %x1 +}