[RISCV] Add codegen support for atomic load/stores with RV32A
Fences are inserted according to table A.6 in the current draft of version 2.3 of the RISC-V Instruction Set Manual, which incorporates the memory model changes and definitions contributed by the RISC-V Memory Consistency Model task group. Instruction selection failures will now occur for 8/16/32-bit atomicrmw and cmpxchg operations when targeting RV32IA until lowering for these operations is added in a follow-on patch. Differential Revision: https://reviews.llvm.org/D47589 llvm-svn: 334591
This commit is contained in:
Alex Bradbury
parent
dc790dd5d0
commit
96f492d7df
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@ -137,8 +137,10 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::BlockAddress, XLenVT, Custom);
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setOperationAction(ISD::ConstantPool, XLenVT, Custom);
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// Atomic operations aren't suported in the base RV32I ISA.
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setMaxAtomicSizeInBitsSupported(0);
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if (Subtarget.hasStdExtA())
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setMaxAtomicSizeInBitsSupported(Subtarget.getXLen());
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else
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setMaxAtomicSizeInBitsSupported(0);
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setBooleanContents(ZeroOrOneBooleanContent);
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@ -1553,3 +1555,21 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
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}
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Instruction *RISCVTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
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Instruction *Inst,
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AtomicOrdering Ord) const {
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if (isa<LoadInst>(Inst) && Ord == AtomicOrdering::SequentiallyConsistent)
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return Builder.CreateFence(Ord);
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if (isa<StoreInst>(Inst) && isReleaseOrStronger(Ord))
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return Builder.CreateFence(AtomicOrdering::Release);
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return nullptr;
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}
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Instruction *RISCVTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
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Instruction *Inst,
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AtomicOrdering Ord) const {
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if (isa<LoadInst>(Inst) && isAcquireOrStronger(Ord))
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return Builder.CreateFence(AtomicOrdering::Acquire);
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return nullptr;
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}
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@ -66,6 +66,14 @@ public:
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EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
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EVT VT) const override;
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bool shouldInsertFencesForAtomic(const Instruction *I) const override {
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return isa<LoadInst>(I) || isa<StoreInst>(I);
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}
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Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
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AtomicOrdering Ord) const override;
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Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst,
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AtomicOrdering Ord) const override;
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private:
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void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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@ -757,6 +757,12 @@ def : Pat<(atomic_fence (i32 6), (imm)), (FENCE_TSO)>;
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// fence seq_cst -> fence rw, rw
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def : Pat<(atomic_fence (i32 7), (imm)), (FENCE 0b11, 0b11)>;
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// Lowering for atomic load and store is defined in RISCVInstrInfoA.td.
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// Although these are lowered to fence+load/store instructions defined in the
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// base RV32I/RV64I ISA, this lowering is only used when the A extension is
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// present. This is necessary as it isn't valid to mix __atomic_* libcalls
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// with inline atomic operations for the same object.
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/// Other pseudo-instructions
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// Pessimistically assume the stack pointer will be clobbered
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@ -75,3 +75,23 @@ defm AMOMAX_D : AMO_rr_aq_rl<0b10100, 0b011, "amomax.d">;
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defm AMOMINU_D : AMO_rr_aq_rl<0b11000, 0b011, "amominu.d">;
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defm AMOMAXU_D : AMO_rr_aq_rl<0b11100, 0b011, "amomaxu.d">;
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} // Predicates = [HasStedExtA, IsRV64]
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//===----------------------------------------------------------------------===//
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// Pseudo-instructions and codegen patterns
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtA] in {
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/// Atomic loads and stores
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// Fences will be inserted for atomic load/stores according to the logic in
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// RISCVTargetLowering::{emitLeadingFence,emitTrailingFence}.
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defm : LdPat<atomic_load_8, LB>;
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defm : LdPat<atomic_load_16, LH>;
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defm : LdPat<atomic_load_32, LW>;
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defm : StPat<atomic_store_8, SB, GPR>;
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defm : StPat<atomic_store_16, SH, GPR>;
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defm : StPat<atomic_store_32, SW, GPR>;
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} // Predicates = [HasStdExtF]
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@ -1,6 +1,8 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32IA %s
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define i8 @atomic_load_i8_unordered(i8 *%a) nounwind {
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; RV32I-LABEL: atomic_load_i8_unordered:
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@ -12,6 +14,11 @@ define i8 @atomic_load_i8_unordered(i8 *%a) nounwind {
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IA-LABEL: atomic_load_i8_unordered:
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; RV32IA: # %bb.0:
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; RV32IA-NEXT: lb a0, 0(a0)
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; RV32IA-NEXT: ret
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%1 = load atomic i8, i8* %a unordered, align 1
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ret i8 %1
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}
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@ -26,6 +33,11 @@ define i8 @atomic_load_i8_monotonic(i8 *%a) nounwind {
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IA-LABEL: atomic_load_i8_monotonic:
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; RV32IA: # %bb.0:
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; RV32IA-NEXT: lb a0, 0(a0)
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; RV32IA-NEXT: ret
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%1 = load atomic i8, i8* %a monotonic, align 1
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ret i8 %1
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}
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@ -40,6 +52,12 @@ define i8 @atomic_load_i8_acquire(i8 *%a) nounwind {
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IA-LABEL: atomic_load_i8_acquire:
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; RV32IA: # %bb.0:
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; RV32IA-NEXT: lb a0, 0(a0)
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; RV32IA-NEXT: fence r, rw
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; RV32IA-NEXT: ret
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%1 = load atomic i8, i8* %a acquire, align 1
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ret i8 %1
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}
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@ -54,6 +72,13 @@ define i8 @atomic_load_i8_seq_cst(i8 *%a) nounwind {
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IA-LABEL: atomic_load_i8_seq_cst:
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; RV32IA: # %bb.0:
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; RV32IA-NEXT: fence rw, rw
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; RV32IA-NEXT: lb a0, 0(a0)
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; RV32IA-NEXT: fence r, rw
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; RV32IA-NEXT: ret
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%1 = load atomic i8, i8* %a seq_cst, align 1
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ret i8 %1
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}
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@ -68,6 +93,11 @@ define i16 @atomic_load_i16_unordered(i16 *%a) nounwind {
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IA-LABEL: atomic_load_i16_unordered:
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; RV32IA: # %bb.0:
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; RV32IA-NEXT: lh a0, 0(a0)
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; RV32IA-NEXT: ret
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%1 = load atomic i16, i16* %a unordered, align 2
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ret i16 %1
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}
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@ -82,6 +112,11 @@ define i16 @atomic_load_i16_monotonic(i16 *%a) nounwind {
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IA-LABEL: atomic_load_i16_monotonic:
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; RV32IA: # %bb.0:
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; RV32IA-NEXT: lh a0, 0(a0)
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; RV32IA-NEXT: ret
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%1 = load atomic i16, i16* %a monotonic, align 2
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ret i16 %1
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}
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@ -96,6 +131,12 @@ define i16 @atomic_load_i16_acquire(i16 *%a) nounwind {
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IA-LABEL: atomic_load_i16_acquire:
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; RV32IA: # %bb.0:
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; RV32IA-NEXT: lh a0, 0(a0)
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; RV32IA-NEXT: fence r, rw
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; RV32IA-NEXT: ret
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%1 = load atomic i16, i16* %a acquire, align 2
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ret i16 %1
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}
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@ -110,6 +151,13 @@ define i16 @atomic_load_i16_seq_cst(i16 *%a) nounwind {
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IA-LABEL: atomic_load_i16_seq_cst:
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; RV32IA: # %bb.0:
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; RV32IA-NEXT: fence rw, rw
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; RV32IA-NEXT: lh a0, 0(a0)
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; RV32IA-NEXT: fence r, rw
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; RV32IA-NEXT: ret
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%1 = load atomic i16, i16* %a seq_cst, align 2
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ret i16 %1
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}
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@ -124,6 +172,11 @@ define i32 @atomic_load_i32_unordered(i32 *%a) nounwind {
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IA-LABEL: atomic_load_i32_unordered:
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; RV32IA: # %bb.0:
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; RV32IA-NEXT: lw a0, 0(a0)
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; RV32IA-NEXT: ret
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%1 = load atomic i32, i32* %a unordered, align 4
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ret i32 %1
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}
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@ -138,6 +191,11 @@ define i32 @atomic_load_i32_monotonic(i32 *%a) nounwind {
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IA-LABEL: atomic_load_i32_monotonic:
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; RV32IA: # %bb.0:
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; RV32IA-NEXT: lw a0, 0(a0)
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; RV32IA-NEXT: ret
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%1 = load atomic i32, i32* %a monotonic, align 4
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ret i32 %1
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}
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@ -152,6 +210,12 @@ define i32 @atomic_load_i32_acquire(i32 *%a) nounwind {
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IA-LABEL: atomic_load_i32_acquire:
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; RV32IA: # %bb.0:
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; RV32IA-NEXT: lw a0, 0(a0)
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; RV32IA-NEXT: fence r, rw
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; RV32IA-NEXT: ret
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%1 = load atomic i32, i32* %a acquire, align 4
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ret i32 %1
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}
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@ -166,6 +230,13 @@ define i32 @atomic_load_i32_seq_cst(i32 *%a) nounwind {
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IA-LABEL: atomic_load_i32_seq_cst:
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; RV32IA: # %bb.0:
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; RV32IA-NEXT: fence rw, rw
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; RV32IA-NEXT: lw a0, 0(a0)
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; RV32IA-NEXT: fence r, rw
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; RV32IA-NEXT: ret
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%1 = load atomic i32, i32* %a seq_cst, align 4
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ret i32 %1
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}
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@ -180,6 +251,16 @@ define i64 @atomic_load_i64_unordered(i64 *%a) nounwind {
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IA-LABEL: atomic_load_i64_unordered:
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; RV32IA: # %bb.0:
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; RV32IA-NEXT: addi sp, sp, -16
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; RV32IA-NEXT: sw ra, 12(sp)
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; RV32IA-NEXT: mv a1, zero
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; RV32IA-NEXT: call __atomic_load_8
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; RV32IA-NEXT: lw ra, 12(sp)
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; RV32IA-NEXT: addi sp, sp, 16
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; RV32IA-NEXT: ret
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%1 = load atomic i64, i64* %a unordered, align 8
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ret i64 %1
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}
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@ -194,6 +275,16 @@ define i64 @atomic_load_i64_monotonic(i64 *%a) nounwind {
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IA-LABEL: atomic_load_i64_monotonic:
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; RV32IA: # %bb.0:
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; RV32IA-NEXT: addi sp, sp, -16
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; RV32IA-NEXT: sw ra, 12(sp)
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; RV32IA-NEXT: mv a1, zero
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; RV32IA-NEXT: call __atomic_load_8
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; RV32IA-NEXT: lw ra, 12(sp)
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; RV32IA-NEXT: addi sp, sp, 16
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; RV32IA-NEXT: ret
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%1 = load atomic i64, i64* %a monotonic, align 8
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ret i64 %1
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}
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@ -208,6 +299,16 @@ define i64 @atomic_load_i64_acquire(i64 *%a) nounwind {
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IA-LABEL: atomic_load_i64_acquire:
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; RV32IA: # %bb.0:
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; RV32IA-NEXT: addi sp, sp, -16
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; RV32IA-NEXT: sw ra, 12(sp)
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; RV32IA-NEXT: addi a1, zero, 2
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; RV32IA-NEXT: call __atomic_load_8
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; RV32IA-NEXT: lw ra, 12(sp)
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; RV32IA-NEXT: addi sp, sp, 16
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; RV32IA-NEXT: ret
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%1 = load atomic i64, i64* %a acquire, align 8
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ret i64 %1
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}
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@ -222,6 +323,16 @@ define i64 @atomic_load_i64_seq_cst(i64 *%a) nounwind {
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IA-LABEL: atomic_load_i64_seq_cst:
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; RV32IA: # %bb.0:
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; RV32IA-NEXT: addi sp, sp, -16
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; RV32IA-NEXT: sw ra, 12(sp)
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; RV32IA-NEXT: addi a1, zero, 5
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; RV32IA-NEXT: call __atomic_load_8
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; RV32IA-NEXT: lw ra, 12(sp)
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; RV32IA-NEXT: addi sp, sp, 16
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; RV32IA-NEXT: ret
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%1 = load atomic i64, i64* %a seq_cst, align 8
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ret i64 %1
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}
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@ -236,6 +347,11 @@ define void @atomic_store_i8_unordered(i8 *%a, i8 %b) nounwind {
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IA-LABEL: atomic_store_i8_unordered:
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; RV32IA: # %bb.0:
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; RV32IA-NEXT: sb a0, 0(a1)
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; RV32IA-NEXT: ret
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store atomic i8 %b, i8* %a unordered, align 1
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ret void
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}
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@ -250,6 +366,11 @@ define void @atomic_store_i8_monotonic(i8 *%a, i8 %b) nounwind {
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IA-LABEL: atomic_store_i8_monotonic:
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; RV32IA: # %bb.0:
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; RV32IA-NEXT: sb a0, 0(a1)
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; RV32IA-NEXT: ret
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store atomic i8 %b, i8* %a monotonic, align 1
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ret void
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}
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@ -264,6 +385,12 @@ define void @atomic_store_i8_release(i8 *%a, i8 %b) nounwind {
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IA-LABEL: atomic_store_i8_release:
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; RV32IA: # %bb.0:
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; RV32IA-NEXT: fence rw, w
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; RV32IA-NEXT: sb a0, 0(a1)
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; RV32IA-NEXT: ret
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store atomic i8 %b, i8* %a release, align 1
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ret void
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}
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@ -278,6 +405,12 @@ define void @atomic_store_i8_seq_cst(i8 *%a, i8 %b) nounwind {
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IA-LABEL: atomic_store_i8_seq_cst:
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; RV32IA: # %bb.0:
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; RV32IA-NEXT: fence rw, w
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; RV32IA-NEXT: sb a0, 0(a1)
|
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; RV32IA-NEXT: ret
|
||||
store atomic i8 %b, i8* %a seq_cst, align 1
|
||||
ret void
|
||||
}
|
||||
|
|
@ -292,6 +425,11 @@ define void @atomic_store_i16_unordered(i16 *%a, i16 %b) nounwind {
|
|||
; RV32I-NEXT: lw ra, 12(sp)
|
||||
; RV32I-NEXT: addi sp, sp, 16
|
||||
; RV32I-NEXT: ret
|
||||
;
|
||||
; RV32IA-LABEL: atomic_store_i16_unordered:
|
||||
; RV32IA: # %bb.0:
|
||||
; RV32IA-NEXT: sh a0, 0(a1)
|
||||
; RV32IA-NEXT: ret
|
||||
store atomic i16 %b, i16* %a unordered, align 2
|
||||
ret void
|
||||
}
|
||||
|
|
@ -306,6 +444,11 @@ define void @atomic_store_i16_monotonic(i16 *%a, i16 %b) nounwind {
|
|||
; RV32I-NEXT: lw ra, 12(sp)
|
||||
; RV32I-NEXT: addi sp, sp, 16
|
||||
; RV32I-NEXT: ret
|
||||
;
|
||||
; RV32IA-LABEL: atomic_store_i16_monotonic:
|
||||
; RV32IA: # %bb.0:
|
||||
; RV32IA-NEXT: sh a0, 0(a1)
|
||||
; RV32IA-NEXT: ret
|
||||
store atomic i16 %b, i16* %a monotonic, align 2
|
||||
ret void
|
||||
}
|
||||
|
|
@ -320,6 +463,12 @@ define void @atomic_store_i16_release(i16 *%a, i16 %b) nounwind {
|
|||
; RV32I-NEXT: lw ra, 12(sp)
|
||||
; RV32I-NEXT: addi sp, sp, 16
|
||||
; RV32I-NEXT: ret
|
||||
;
|
||||
; RV32IA-LABEL: atomic_store_i16_release:
|
||||
; RV32IA: # %bb.0:
|
||||
; RV32IA-NEXT: fence rw, w
|
||||
; RV32IA-NEXT: sh a0, 0(a1)
|
||||
; RV32IA-NEXT: ret
|
||||
store atomic i16 %b, i16* %a release, align 2
|
||||
ret void
|
||||
}
|
||||
|
|
@ -334,6 +483,12 @@ define void @atomic_store_i16_seq_cst(i16 *%a, i16 %b) nounwind {
|
|||
; RV32I-NEXT: lw ra, 12(sp)
|
||||
; RV32I-NEXT: addi sp, sp, 16
|
||||
; RV32I-NEXT: ret
|
||||
;
|
||||
; RV32IA-LABEL: atomic_store_i16_seq_cst:
|
||||
; RV32IA: # %bb.0:
|
||||
; RV32IA-NEXT: fence rw, w
|
||||
; RV32IA-NEXT: sh a0, 0(a1)
|
||||
; RV32IA-NEXT: ret
|
||||
store atomic i16 %b, i16* %a seq_cst, align 2
|
||||
ret void
|
||||
}
|
||||
|
|
@ -348,6 +503,11 @@ define void @atomic_store_i32_unordered(i32 *%a, i32 %b) nounwind {
|
|||
; RV32I-NEXT: lw ra, 12(sp)
|
||||
; RV32I-NEXT: addi sp, sp, 16
|
||||
; RV32I-NEXT: ret
|
||||
;
|
||||
; RV32IA-LABEL: atomic_store_i32_unordered:
|
||||
; RV32IA: # %bb.0:
|
||||
; RV32IA-NEXT: sw a0, 0(a1)
|
||||
; RV32IA-NEXT: ret
|
||||
store atomic i32 %b, i32* %a unordered, align 4
|
||||
ret void
|
||||
}
|
||||
|
|
@ -362,6 +522,11 @@ define void @atomic_store_i32_monotonic(i32 *%a, i32 %b) nounwind {
|
|||
; RV32I-NEXT: lw ra, 12(sp)
|
||||
; RV32I-NEXT: addi sp, sp, 16
|
||||
; RV32I-NEXT: ret
|
||||
;
|
||||
; RV32IA-LABEL: atomic_store_i32_monotonic:
|
||||
; RV32IA: # %bb.0:
|
||||
; RV32IA-NEXT: sw a0, 0(a1)
|
||||
; RV32IA-NEXT: ret
|
||||
store atomic i32 %b, i32* %a monotonic, align 4
|
||||
ret void
|
||||
}
|
||||
|
|
@ -376,6 +541,12 @@ define void @atomic_store_i32_release(i32 *%a, i32 %b) nounwind {
|
|||
; RV32I-NEXT: lw ra, 12(sp)
|
||||
; RV32I-NEXT: addi sp, sp, 16
|
||||
; RV32I-NEXT: ret
|
||||
;
|
||||
; RV32IA-LABEL: atomic_store_i32_release:
|
||||
; RV32IA: # %bb.0:
|
||||
; RV32IA-NEXT: fence rw, w
|
||||
; RV32IA-NEXT: sw a0, 0(a1)
|
||||
; RV32IA-NEXT: ret
|
||||
store atomic i32 %b, i32* %a release, align 4
|
||||
ret void
|
||||
}
|
||||
|
|
@ -390,6 +561,12 @@ define void @atomic_store_i32_seq_cst(i32 *%a, i32 %b) nounwind {
|
|||
; RV32I-NEXT: lw ra, 12(sp)
|
||||
; RV32I-NEXT: addi sp, sp, 16
|
||||
; RV32I-NEXT: ret
|
||||
;
|
||||
; RV32IA-LABEL: atomic_store_i32_seq_cst:
|
||||
; RV32IA: # %bb.0:
|
||||
; RV32IA-NEXT: fence rw, w
|
||||
; RV32IA-NEXT: sw a0, 0(a1)
|
||||
; RV32IA-NEXT: ret
|
||||
store atomic i32 %b, i32* %a seq_cst, align 4
|
||||
ret void
|
||||
}
|
||||
|
|
@ -404,6 +581,16 @@ define void @atomic_store_i64_unordered(i64 *%a, i64 %b) nounwind {
|
|||
; RV32I-NEXT: lw ra, 12(sp)
|
||||
; RV32I-NEXT: addi sp, sp, 16
|
||||
; RV32I-NEXT: ret
|
||||
;
|
||||
; RV32IA-LABEL: atomic_store_i64_unordered:
|
||||
; RV32IA: # %bb.0:
|
||||
; RV32IA-NEXT: addi sp, sp, -16
|
||||
; RV32IA-NEXT: sw ra, 12(sp)
|
||||
; RV32IA-NEXT: mv a3, zero
|
||||
; RV32IA-NEXT: call __atomic_store_8
|
||||
; RV32IA-NEXT: lw ra, 12(sp)
|
||||
; RV32IA-NEXT: addi sp, sp, 16
|
||||
; RV32IA-NEXT: ret
|
||||
store atomic i64 %b, i64* %a unordered, align 8
|
||||
ret void
|
||||
}
|
||||
|
|
@ -418,6 +605,16 @@ define void @atomic_store_i64_monotonic(i64 *%a, i64 %b) nounwind {
|
|||
; RV32I-NEXT: lw ra, 12(sp)
|
||||
; RV32I-NEXT: addi sp, sp, 16
|
||||
; RV32I-NEXT: ret
|
||||
;
|
||||
; RV32IA-LABEL: atomic_store_i64_monotonic:
|
||||
; RV32IA: # %bb.0:
|
||||
; RV32IA-NEXT: addi sp, sp, -16
|
||||
; RV32IA-NEXT: sw ra, 12(sp)
|
||||
; RV32IA-NEXT: mv a3, zero
|
||||
; RV32IA-NEXT: call __atomic_store_8
|
||||
; RV32IA-NEXT: lw ra, 12(sp)
|
||||
; RV32IA-NEXT: addi sp, sp, 16
|
||||
; RV32IA-NEXT: ret
|
||||
store atomic i64 %b, i64* %a monotonic, align 8
|
||||
ret void
|
||||
}
|
||||
|
|
@ -432,6 +629,16 @@ define void @atomic_store_i64_release(i64 *%a, i64 %b) nounwind {
|
|||
; RV32I-NEXT: lw ra, 12(sp)
|
||||
; RV32I-NEXT: addi sp, sp, 16
|
||||
; RV32I-NEXT: ret
|
||||
;
|
||||
; RV32IA-LABEL: atomic_store_i64_release:
|
||||
; RV32IA: # %bb.0:
|
||||
; RV32IA-NEXT: addi sp, sp, -16
|
||||
; RV32IA-NEXT: sw ra, 12(sp)
|
||||
; RV32IA-NEXT: addi a3, zero, 3
|
||||
; RV32IA-NEXT: call __atomic_store_8
|
||||
; RV32IA-NEXT: lw ra, 12(sp)
|
||||
; RV32IA-NEXT: addi sp, sp, 16
|
||||
; RV32IA-NEXT: ret
|
||||
store atomic i64 %b, i64* %a release, align 8
|
||||
ret void
|
||||
}
|
||||
|
|
@ -446,6 +653,16 @@ define void @atomic_store_i64_seq_cst(i64 *%a, i64 %b) nounwind {
|
|||
; RV32I-NEXT: lw ra, 12(sp)
|
||||
; RV32I-NEXT: addi sp, sp, 16
|
||||
; RV32I-NEXT: ret
|
||||
;
|
||||
; RV32IA-LABEL: atomic_store_i64_seq_cst:
|
||||
; RV32IA: # %bb.0:
|
||||
; RV32IA-NEXT: addi sp, sp, -16
|
||||
; RV32IA-NEXT: sw ra, 12(sp)
|
||||
; RV32IA-NEXT: addi a3, zero, 5
|
||||
; RV32IA-NEXT: call __atomic_store_8
|
||||
; RV32IA-NEXT: lw ra, 12(sp)
|
||||
; RV32IA-NEXT: addi sp, sp, 16
|
||||
; RV32IA-NEXT: ret
|
||||
store atomic i64 %b, i64* %a seq_cst, align 8
|
||||
ret void
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue