Define classes for definitions of atomic instructions.
llvm-svn: 135546
This commit is contained in:
Akira Hatanaka
parent
da5d2b761a
commit
969edcdf74
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@ -396,6 +396,22 @@ class ReadHardware: FR<0x1f, 0x3b, (outs CPURegs:$dst), (ins HWRegs:$src),
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let shamt = 0;
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}
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// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
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class Atomic2<PatFrag Op, string Opstr> :
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MipsPseudo<(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
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!strconcat("atomic_", Opstr, "\t$dst, $ptr, $incr"),
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[(set CPURegs:$dst,
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(Op CPURegs:$ptr, CPURegs:$incr))]>;
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// Atomic Compare & Swap.
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class AtomicCmpSwap<PatFrag Op, string Width> :
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MipsPseudo<(outs CPURegs:$dst),
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(ins CPURegs:$ptr, CPURegs:$cmp, CPURegs:$swap),
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!strconcat("atomic_cmp_swap_", Width,
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"\t$dst, $ptr, $cmp, $swap"),
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[(set CPURegs:$dst,
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(Op CPURegs:$ptr, CPURegs:$cmp, CPURegs:$swap))]>;
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//===----------------------------------------------------------------------===//
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// Pseudo instructions
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//===----------------------------------------------------------------------===//
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@ -430,112 +446,32 @@ def CPLOAD : MipsPseudo<(outs), (ins CPURegs:$picreg), ".cpload\t$picreg", []>;
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def CPRESTORE : MipsPseudo<(outs), (ins i32imm:$loc), ".cprestore\t$loc", []>;
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let usesCustomInserter = 1 in {
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def ATOMIC_LOAD_ADD_I8 : MipsPseudo<
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(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
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"atomic_load_add_8\t$dst, $ptr, $incr",
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[(set CPURegs:$dst, (atomic_load_add_8 CPURegs:$ptr, CPURegs:$incr))]>;
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def ATOMIC_LOAD_ADD_I16 : MipsPseudo<
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(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
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"atomic_load_add_16\t$dst, $ptr, $incr",
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[(set CPURegs:$dst, (atomic_load_add_16 CPURegs:$ptr, CPURegs:$incr))]>;
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def ATOMIC_LOAD_ADD_I32 : MipsPseudo<
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(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
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"atomic_load_add_32\t$dst, $ptr, $incr",
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[(set CPURegs:$dst, (atomic_load_add_32 CPURegs:$ptr, CPURegs:$incr))]>;
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def ATOMIC_LOAD_ADD_I8 : Atomic2<atomic_load_add_8, "load_add_8">;
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def ATOMIC_LOAD_ADD_I16 : Atomic2<atomic_load_add_16, "load_add_16">;
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def ATOMIC_LOAD_ADD_I32 : Atomic2<atomic_load_add_32, "load_add_32">;
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def ATOMIC_LOAD_SUB_I8 : Atomic2<atomic_load_sub_8, "load_sub_8">;
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def ATOMIC_LOAD_SUB_I16 : Atomic2<atomic_load_sub_16, "load_sub_16">;
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def ATOMIC_LOAD_SUB_I32 : Atomic2<atomic_load_sub_32, "load_sub_32">;
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def ATOMIC_LOAD_AND_I8 : Atomic2<atomic_load_and_8, "load_and_8">;
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def ATOMIC_LOAD_AND_I16 : Atomic2<atomic_load_and_16, "load_and_16">;
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def ATOMIC_LOAD_AND_I32 : Atomic2<atomic_load_and_32, "load_and_32">;
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def ATOMIC_LOAD_OR_I8 : Atomic2<atomic_load_or_8, "load_or_8">;
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def ATOMIC_LOAD_OR_I16 : Atomic2<atomic_load_or_16, "load_or_16">;
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def ATOMIC_LOAD_OR_I32 : Atomic2<atomic_load_or_32, "load_or_32">;
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def ATOMIC_LOAD_XOR_I8 : Atomic2<atomic_load_xor_8, "load_xor_8">;
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def ATOMIC_LOAD_XOR_I16 : Atomic2<atomic_load_xor_16, "load_xor_16">;
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def ATOMIC_LOAD_XOR_I32 : Atomic2<atomic_load_xor_32, "load_xor_32">;
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def ATOMIC_LOAD_NAND_I8 : Atomic2<atomic_load_nand_8, "load_nand_8">;
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def ATOMIC_LOAD_NAND_I16 : Atomic2<atomic_load_nand_16, "load_nand_16">;
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def ATOMIC_LOAD_NAND_I32 : Atomic2<atomic_load_nand_32, "load_nand_32">;
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def ATOMIC_LOAD_SUB_I8 : MipsPseudo<
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(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
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"atomic_load_sub_8\t$dst, $ptr, $incr",
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[(set CPURegs:$dst, (atomic_load_sub_8 CPURegs:$ptr, CPURegs:$incr))]>;
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def ATOMIC_LOAD_SUB_I16 : MipsPseudo<
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(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
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"atomic_load_sub_16\t$dst, $ptr, $incr",
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[(set CPURegs:$dst, (atomic_load_sub_16 CPURegs:$ptr, CPURegs:$incr))]>;
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def ATOMIC_LOAD_SUB_I32 : MipsPseudo<
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(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
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"atomic_load_sub_32\t$dst, $ptr, $incr",
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[(set CPURegs:$dst, (atomic_load_sub_32 CPURegs:$ptr, CPURegs:$incr))]>;
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def ATOMIC_SWAP_I8 : Atomic2<atomic_swap_8, "swap_8">;
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def ATOMIC_SWAP_I16 : Atomic2<atomic_swap_16, "swap_16">;
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def ATOMIC_SWAP_I32 : Atomic2<atomic_swap_32, "swap_32">;
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def ATOMIC_LOAD_AND_I8 : MipsPseudo<
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(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
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"atomic_load_and_8\t$dst, $ptr, $incr",
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[(set CPURegs:$dst, (atomic_load_and_8 CPURegs:$ptr, CPURegs:$incr))]>;
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def ATOMIC_LOAD_AND_I16 : MipsPseudo<
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(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
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"atomic_load_and_16\t$dst, $ptr, $incr",
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[(set CPURegs:$dst, (atomic_load_and_16 CPURegs:$ptr, CPURegs:$incr))]>;
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def ATOMIC_LOAD_AND_I32 : MipsPseudo<
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(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
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"atomic_load_and_32\t$dst, $ptr, $incr",
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[(set CPURegs:$dst, (atomic_load_and_32 CPURegs:$ptr, CPURegs:$incr))]>;
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def ATOMIC_LOAD_OR_I8 : MipsPseudo<
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(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
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"atomic_load_or_8\t$dst, $ptr, $incr",
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[(set CPURegs:$dst, (atomic_load_or_8 CPURegs:$ptr, CPURegs:$incr))]>;
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def ATOMIC_LOAD_OR_I16 : MipsPseudo<
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(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
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"atomic_load_or_16\t$dst, $ptr, $incr",
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[(set CPURegs:$dst, (atomic_load_or_16 CPURegs:$ptr, CPURegs:$incr))]>;
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def ATOMIC_LOAD_OR_I32 : MipsPseudo<
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(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
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"atomic_load_or_32\t$dst, $ptr, $incr",
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[(set CPURegs:$dst, (atomic_load_or_32 CPURegs:$ptr, CPURegs:$incr))]>;
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def ATOMIC_LOAD_XOR_I8 : MipsPseudo<
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(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
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"atomic_load_xor_8\t$dst, $ptr, $incr",
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[(set CPURegs:$dst, (atomic_load_xor_8 CPURegs:$ptr, CPURegs:$incr))]>;
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def ATOMIC_LOAD_XOR_I16 : MipsPseudo<
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(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
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"atomic_load_xor_16\t$dst, $ptr, $incr",
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[(set CPURegs:$dst, (atomic_load_xor_16 CPURegs:$ptr, CPURegs:$incr))]>;
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def ATOMIC_LOAD_XOR_I32 : MipsPseudo<
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(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
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"atomic_load_xor_32\t$dst, $ptr, $incr",
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[(set CPURegs:$dst, (atomic_load_xor_32 CPURegs:$ptr, CPURegs:$incr))]>;
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def ATOMIC_LOAD_NAND_I8 : MipsPseudo<
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(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
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"atomic_load_nand_8\t$dst, $ptr, $incr",
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[(set CPURegs:$dst, (atomic_load_nand_8 CPURegs:$ptr, CPURegs:$incr))]>;
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def ATOMIC_LOAD_NAND_I16 : MipsPseudo<
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(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
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"atomic_load_nand_16\t$dst, $ptr, $incr",
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[(set CPURegs:$dst, (atomic_load_nand_16 CPURegs:$ptr, CPURegs:$incr))]>;
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def ATOMIC_LOAD_NAND_I32 : MipsPseudo<
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(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
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"atomic_load_nand_32\t$dst, $ptr, $incr",
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[(set CPURegs:$dst, (atomic_load_nand_32 CPURegs:$ptr, CPURegs:$incr))]>;
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def ATOMIC_SWAP_I8 : MipsPseudo<
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(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$val),
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"atomic_swap_8\t$dst, $ptr, $val",
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[(set CPURegs:$dst, (atomic_swap_8 CPURegs:$ptr, CPURegs:$val))]>;
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def ATOMIC_SWAP_I16 : MipsPseudo<
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(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$val),
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"atomic_swap_16\t$dst, $ptr, $val",
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[(set CPURegs:$dst, (atomic_swap_16 CPURegs:$ptr, CPURegs:$val))]>;
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def ATOMIC_SWAP_I32 : MipsPseudo<
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(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$val),
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"atomic_swap_32\t$dst, $ptr, $val",
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[(set CPURegs:$dst, (atomic_swap_32 CPURegs:$ptr, CPURegs:$val))]>;
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def ATOMIC_CMP_SWAP_I8 : MipsPseudo<
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(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$oldval, CPURegs:$newval),
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"atomic_cmp_swap_8\t$dst, $ptr, $oldval, $newval",
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[(set CPURegs:$dst,
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(atomic_cmp_swap_8 CPURegs:$ptr, CPURegs:$oldval, CPURegs:$newval))]>;
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def ATOMIC_CMP_SWAP_I16 : MipsPseudo<
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(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$oldval, CPURegs:$newval),
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"atomic_cmp_swap_16\t$dst, $ptr, $oldval, $newval",
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[(set CPURegs:$dst,
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(atomic_cmp_swap_16 CPURegs:$ptr, CPURegs:$oldval, CPURegs:$newval))]>;
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def ATOMIC_CMP_SWAP_I32 : MipsPseudo<
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(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$oldval, CPURegs:$newval),
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"atomic_cmp_swap_32\t$dst, $ptr, $oldval, $newval",
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[(set CPURegs:$dst,
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(atomic_cmp_swap_32 CPURegs:$ptr, CPURegs:$oldval, CPURegs:$newval))]>;
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def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, "8">;
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def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, "16">;
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def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, "32">;
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}
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//===----------------------------------------------------------------------===//
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