[X86][Haswell][SchedModel] Add architecture specific scheduling models.
Group: Floating Point XMM and YMM instructions. Sub-group: Other instructions. <rdar://problem/15607571> llvm-svn: 215923
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@ -2106,4 +2106,34 @@ def : InstRW<[WriteP5], (instregex "(V?)(AND|ANDN|OR|XOR)P(S|D)(Y?)rr")>;
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def : InstRW<[WriteP5Ld, ReadAfterLd],
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(instregex "(V?)(AND|ANDN|OR|XOR)P(S|D)(Y?)rm")>;
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//-- Other instructions --//
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// VZEROUPPER.
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def WriteVZEROUPPER : SchedWriteRes<[]> {
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let NumMicroOps = 4;
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}
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def : InstRW<[WriteVZEROUPPER], (instregex "VZEROUPPER")>;
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// VZEROALL.
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def WriteVZEROALL : SchedWriteRes<[]> {
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let NumMicroOps = 12;
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}
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def : InstRW<[WriteVZEROALL], (instregex "VZEROALL")>;
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// LDMXCSR.
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def WriteLDMXCSR : SchedWriteRes<[HWPort0, HWPort6, HWPort23]> {
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let Latency = 6;
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let NumMicroOps = 3;
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let ResourceCycles = [1, 1, 1];
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}
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def : InstRW<[WriteLDMXCSR], (instregex "(V)?LDMXCSR")>;
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// STMXCSR.
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def WriteSTMXCSR : SchedWriteRes<[HWPort0, HWPort4, HWPort6, HWPort237]> {
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let Latency = 7;
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let NumMicroOps = 4;
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let ResourceCycles = [1, 1, 1, 1];
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}
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def : InstRW<[WriteSTMXCSR], (instregex "(V)?STMXCSR")>;
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} // SchedModel
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