ARM: relax the atomic release barrier to "dmb ishst"
I believe the full "dmb ish" barrier is not required to guarantee release semantics for atomic operations. The weaker "dmb ishst" prevents previous operations being reordered with a store executed afterwards, which is enough. A key point to note (fortunately already correct) is that this barrier alone is *insufficient* for sequential consistency, no matter how liberally placed. llvm-svn: 185339
This commit is contained in:
Tim Northover
parent
8a4e24ea8b
commit
953abab40a
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@ -2557,8 +2557,12 @@ static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
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DAG.getConstant(0, MVT::i32));
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}
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ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
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AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
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unsigned Domain = Ord == Release ? ARM_MB::ISHST : ARM_MB::ISH;
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return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
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DAG.getConstant(ARM_MB::ISH, MVT::i32));
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DAG.getConstant(Domain, MVT::i32));
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}
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static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
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@ -3,24 +3,24 @@
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define i64 @test1(i64* %ptr, i64 %val) {
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; CHECK: test1:
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; CHECK: dmb ish
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; CHECK: dmb ishst
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; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
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; CHECK: adds [[REG3:(r[0-9]?[02468])]], [[REG1]]
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; CHECK: adc [[REG4:(r[0-9]?[13579])]], [[REG2]]
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; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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; CHECK: dmb {{ish$}}
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; CHECK-THUMB: test1:
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; CHECK-THUMB: dmb ish
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; CHECK-THUMB: dmb ishst
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; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
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; CHECK-THUMB: adds.w [[REG3:[a-z0-9]+]], [[REG1]]
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; CHECK-THUMB: adc.w [[REG4:[a-z0-9]+]], [[REG2]]
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; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
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; CHECK-THUMB: cmp
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; CHECK-THUMB: bne
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; CHECK-THUMB: dmb ish
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; CHECK-THUMB: dmb {{ish$}}
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%r = atomicrmw add i64* %ptr, i64 %val seq_cst
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ret i64 %r
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@ -28,24 +28,24 @@ define i64 @test1(i64* %ptr, i64 %val) {
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define i64 @test2(i64* %ptr, i64 %val) {
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; CHECK: test2:
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; CHECK: dmb ish
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; CHECK: dmb ishst
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; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
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; CHECK: subs [[REG3:(r[0-9]?[02468])]], [[REG1]]
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; CHECK: sbc [[REG4:(r[0-9]?[13579])]], [[REG2]]
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; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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; CHECK: dmb {{ish$}}
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; CHECK-THUMB: test2:
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; CHECK-THUMB: dmb ish
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; CHECK-THUMB: dmb ishst
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; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
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; CHECK-THUMB: subs.w [[REG3:[a-z0-9]+]], [[REG1]]
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; CHECK-THUMB: sbc.w [[REG4:[a-z0-9]+]], [[REG2]]
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; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
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; CHECK-THUMB: cmp
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; CHECK-THUMB: bne
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; CHECK-THUMB: dmb ish
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; CHECK-THUMB: dmb {{ish$}}
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%r = atomicrmw sub i64* %ptr, i64 %val seq_cst
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ret i64 %r
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@ -53,24 +53,24 @@ define i64 @test2(i64* %ptr, i64 %val) {
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define i64 @test3(i64* %ptr, i64 %val) {
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; CHECK: test3:
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; CHECK: dmb ish
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; CHECK: dmb ishst
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; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
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; CHECK: and [[REG3:(r[0-9]?[02468])]], [[REG1]]
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; CHECK: and [[REG4:(r[0-9]?[13579])]], [[REG2]]
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; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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; CHECK: dmb {{ish$}}
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; CHECK-THUMB: test3:
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; CHECK-THUMB: dmb ish
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; CHECK-THUMB: dmb ishst
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; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
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; CHECK-THUMB: and.w [[REG3:[a-z0-9]+]], [[REG1]]
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; CHECK-THUMB: and.w [[REG4:[a-z0-9]+]], [[REG2]]
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; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
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; CHECK-THUMB: cmp
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; CHECK-THUMB: bne
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; CHECK-THUMB: dmb ish
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; CHECK-THUMB: dmb {{ish$}}
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%r = atomicrmw and i64* %ptr, i64 %val seq_cst
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ret i64 %r
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@ -78,24 +78,24 @@ define i64 @test3(i64* %ptr, i64 %val) {
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define i64 @test4(i64* %ptr, i64 %val) {
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; CHECK: test4:
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; CHECK: dmb ish
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; CHECK: dmb ishst
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; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
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; CHECK: orr [[REG3:(r[0-9]?[02468])]], [[REG1]]
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; CHECK: orr [[REG4:(r[0-9]?[13579])]], [[REG2]]
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; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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; CHECK: dmb {{ish$}}
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; CHECK-THUMB: test4:
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; CHECK-THUMB: dmb ish
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; CHECK-THUMB: dmb ishst
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; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
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; CHECK-THUMB: orr.w [[REG3:[a-z0-9]+]], [[REG1]]
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; CHECK-THUMB: orr.w [[REG4:[a-z0-9]+]], [[REG2]]
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; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
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; CHECK-THUMB: cmp
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; CHECK-THUMB: bne
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; CHECK-THUMB: dmb ish
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; CHECK-THUMB: dmb {{ish$}}
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%r = atomicrmw or i64* %ptr, i64 %val seq_cst
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ret i64 %r
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@ -103,24 +103,24 @@ define i64 @test4(i64* %ptr, i64 %val) {
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define i64 @test5(i64* %ptr, i64 %val) {
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; CHECK: test5:
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; CHECK: dmb ish
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; CHECK: dmb ishst
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; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
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; CHECK: eor [[REG3:(r[0-9]?[02468])]], [[REG1]]
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; CHECK: eor [[REG4:(r[0-9]?[13579])]], [[REG2]]
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; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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; CHECK: dmb {{ish$}}
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; CHECK-THUMB: test5:
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; CHECK-THUMB: dmb ish
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; CHECK-THUMB: dmb ishst
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; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
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; CHECK-THUMB: eor.w [[REG3:[a-z0-9]+]], [[REG1]]
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; CHECK-THUMB: eor.w [[REG4:[a-z0-9]+]], [[REG2]]
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; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
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; CHECK-THUMB: cmp
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; CHECK-THUMB: bne
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; CHECK-THUMB: dmb ish
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; CHECK-THUMB: dmb {{ish$}}
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%r = atomicrmw xor i64* %ptr, i64 %val seq_cst
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ret i64 %r
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@ -128,20 +128,20 @@ define i64 @test5(i64* %ptr, i64 %val) {
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define i64 @test6(i64* %ptr, i64 %val) {
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; CHECK: test6:
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; CHECK: dmb ish
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; CHECK: dmb ishst
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; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
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; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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; CHECK: dmb {{ish$}}
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; CHECK-THUMB: test6:
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; CHECK-THUMB: dmb ish
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; CHECK-THUMB: dmb ishst
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; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
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; CHECK-THUMB: strexd {{[a-z0-9]+}}, {{[a-z0-9]+}}, {{[a-z0-9]+}}
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; CHECK-THUMB: cmp
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; CHECK-THUMB: bne
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; CHECK-THUMB: dmb ish
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; CHECK-THUMB: dmb {{ish$}}
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%r = atomicrmw xchg i64* %ptr, i64 %val seq_cst
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ret i64 %r
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@ -149,7 +149,7 @@ define i64 @test6(i64* %ptr, i64 %val) {
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define i64 @test7(i64* %ptr, i64 %val1, i64 %val2) {
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; CHECK: test7:
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; CHECK: dmb ish
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; CHECK: dmb ishst
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; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
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; CHECK: cmp [[REG1]]
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; CHECK: cmpeq [[REG2]]
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@ -157,10 +157,10 @@ define i64 @test7(i64* %ptr, i64 %val1, i64 %val2) {
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; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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; CHECK: dmb {{ish$}}
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; CHECK-THUMB: test7:
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; CHECK-THUMB: dmb ish
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; CHECK-THUMB: dmb ishst
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; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
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; CHECK-THUMB: cmp [[REG1]]
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; CHECK-THUMB: it eq
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@ -169,7 +169,7 @@ define i64 @test7(i64* %ptr, i64 %val1, i64 %val2) {
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; CHECK-THUMB: strexd {{[a-z0-9]+}}, {{[a-z0-9]+}}, {{[a-z0-9]+}}
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; CHECK-THUMB: cmp
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; CHECK-THUMB: bne
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; CHECK-THUMB: dmb ish
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; CHECK-THUMB: dmb {{ish$}}
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%r = cmpxchg i64* %ptr, i64 %val1, i64 %val2 seq_cst
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ret i64 %r
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@ -186,7 +186,7 @@ define i64 @test8(i64* %ptr) {
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; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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; CHECK: dmb {{ish$}}
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; CHECK-THUMB: test8:
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; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
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@ -197,7 +197,7 @@ define i64 @test8(i64* %ptr) {
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; CHECK-THUMB: strexd {{[a-z0-9]+}}, {{[a-z0-9]+}}, {{[a-z0-9]+}}
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; CHECK-THUMB: cmp
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; CHECK-THUMB: bne
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; CHECK-THUMB: dmb ish
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; CHECK-THUMB: dmb {{ish$}}
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%r = load atomic i64* %ptr seq_cst, align 8
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ret i64 %r
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@ -207,20 +207,20 @@ define i64 @test8(i64* %ptr) {
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; way to write it.
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define void @test9(i64* %ptr, i64 %val) {
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; CHECK: test9:
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; CHECK: dmb ish
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; CHECK: dmb ishst
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; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
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; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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; CHECK: dmb {{ish$}}
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; CHECK-THUMB: test9:
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; CHECK-THUMB: dmb ish
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; CHECK-THUMB: dmb ishst
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; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
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; CHECK-THUMB: strexd {{[a-z0-9]+}}, {{[a-z0-9]+}}, {{[a-z0-9]+}}
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; CHECK-THUMB: cmp
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; CHECK-THUMB: bne
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; CHECK-THUMB: dmb ish
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; CHECK-THUMB: dmb {{ish$}}
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store atomic i64 %val, i64* %ptr seq_cst, align 8
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ret void
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@ -228,7 +228,7 @@ define void @test9(i64* %ptr, i64 %val) {
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define i64 @test10(i64* %ptr, i64 %val) {
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; CHECK: test10:
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; CHECK: dmb ish
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; CHECK: dmb ishst
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; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
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; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
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; CHECK: sbcs {{[a-z0-9]+}}, [[REG2]], [[REG4:(r[0-9]?[13579])]]
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@ -236,10 +236,10 @@ define i64 @test10(i64* %ptr, i64 %val) {
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; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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; CHECK: dmb {{ish$}}
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; CHECK-THUMB: test10:
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; CHECK-THUMB: dmb ish
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; CHECK-THUMB: dmb ishst
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; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
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; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]]
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; CHECK-THUMB: sbcs.w {{[a-z0-9]+}}, [[REG2]], [[REG4:[a-z0-9]+]]
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@ -247,7 +247,7 @@ define i64 @test10(i64* %ptr, i64 %val) {
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; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
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; CHECK-THUMB: cmp
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; CHECK-THUMB: bne
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; CHECK-THUMB: dmb ish
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; CHECK-THUMB: dmb {{ish$}}
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%r = atomicrmw min i64* %ptr, i64 %val seq_cst
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ret i64 %r
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@ -255,7 +255,7 @@ define i64 @test10(i64* %ptr, i64 %val) {
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define i64 @test11(i64* %ptr, i64 %val) {
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; CHECK: test11:
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; CHECK: dmb ish
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; CHECK: dmb ishst
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; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
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; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
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; CHECK: sbcs {{[a-z0-9]+}}, [[REG2]], [[REG4:(r[0-9]?[13579])]]
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@ -263,11 +263,11 @@ define i64 @test11(i64* %ptr, i64 %val) {
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; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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; CHECK: dmb {{ish$}}
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; CHECK-THUMB: test11:
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; CHECK-THUMB: dmb ish
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; CHECK-THUMB: dmb ishst
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; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
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; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]]
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; CHECK-THUMB: sbcs.w {{[a-z0-9]+}}, [[REG2]], [[REG4:[a-z0-9]+]]
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@ -275,7 +275,7 @@ define i64 @test11(i64* %ptr, i64 %val) {
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; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
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; CHECK-THUMB: cmp
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; CHECK-THUMB: bne
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; CHECK-THUMB: dmb ish
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; CHECK-THUMB: dmb {{ish$}}
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%r = atomicrmw umin i64* %ptr, i64 %val seq_cst
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ret i64 %r
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@ -283,7 +283,7 @@ define i64 @test11(i64* %ptr, i64 %val) {
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define i64 @test12(i64* %ptr, i64 %val) {
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; CHECK: test12:
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; CHECK: dmb ish
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; CHECK: dmb ishst
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; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
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; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
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; CHECK: sbcs {{[a-z0-9]+}}, [[REG2]], [[REG4:(r[0-9]?[13579])]]
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@ -291,10 +291,10 @@ define i64 @test12(i64* %ptr, i64 %val) {
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; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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||||
; CHECK: dmb {{ish$}}
|
||||
|
||||
; CHECK-THUMB: test12:
|
||||
; CHECK-THUMB: dmb ish
|
||||
; CHECK-THUMB: dmb ishst
|
||||
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
|
||||
; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]]
|
||||
; CHECK-THUMB: sbcs.w {{[a-z0-9]+}}, [[REG2]], [[REG4:[a-z0-9]+]]
|
||||
|
|
@ -302,7 +302,7 @@ define i64 @test12(i64* %ptr, i64 %val) {
|
|||
; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
|
||||
; CHECK-THUMB: cmp
|
||||
; CHECK-THUMB: bne
|
||||
; CHECK-THUMB: dmb ish
|
||||
; CHECK-THUMB: dmb {{ish$}}
|
||||
|
||||
%r = atomicrmw max i64* %ptr, i64 %val seq_cst
|
||||
ret i64 %r
|
||||
|
|
@ -310,7 +310,7 @@ define i64 @test12(i64* %ptr, i64 %val) {
|
|||
|
||||
define i64 @test13(i64* %ptr, i64 %val) {
|
||||
; CHECK: test13:
|
||||
; CHECK: dmb ish
|
||||
; CHECK: dmb ishst
|
||||
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
|
||||
; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
|
||||
; CHECK: sbcs {{[a-z0-9]+}}, [[REG2]], [[REG4:(r[0-9]?[13579])]]
|
||||
|
|
@ -318,10 +318,10 @@ define i64 @test13(i64* %ptr, i64 %val) {
|
|||
; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
|
||||
; CHECK: cmp
|
||||
; CHECK: bne
|
||||
; CHECK: dmb ish
|
||||
; CHECK: dmb {{ish$}}
|
||||
|
||||
; CHECK-THUMB: test13:
|
||||
; CHECK-THUMB: dmb ish
|
||||
; CHECK-THUMB: dmb ishst
|
||||
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
|
||||
; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]]
|
||||
; CHECK-THUMB: sbcs.w {{[a-z0-9]+}}, [[REG2]], [[REG4:[a-z0-9]+]]
|
||||
|
|
@ -329,7 +329,7 @@ define i64 @test13(i64* %ptr, i64 %val) {
|
|||
; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
|
||||
; CHECK-THUMB: cmp
|
||||
; CHECK-THUMB: bne
|
||||
; CHECK-THUMB: dmb ish
|
||||
; CHECK-THUMB: dmb {{ish$}}
|
||||
%r = atomicrmw umax i64* %ptr, i64 %val seq_cst
|
||||
ret i64 %r
|
||||
}
|
||||
|
|
|
|||
|
|
@ -6,15 +6,15 @@
|
|||
|
||||
define void @test1(i32* %ptr, i32 %val1) {
|
||||
; ARM: test1
|
||||
; ARM: dmb ish
|
||||
; ARM: dmb ishst
|
||||
; ARM-NEXT: str
|
||||
; ARM-NEXT: dmb ish
|
||||
; ARM-NEXT: dmb {{ish$}}
|
||||
; THUMBONE: test1
|
||||
; THUMBONE: __sync_lock_test_and_set_4
|
||||
; THUMBTWO: test1
|
||||
; THUMBTWO: dmb ish
|
||||
; THUMBTWO: dmb ishst
|
||||
; THUMBTWO-NEXT: str
|
||||
; THUMBTWO-NEXT: dmb ish
|
||||
; THUMBTWO-NEXT: dmb {{ish$}}
|
||||
store atomic i32 %val1, i32* %ptr seq_cst, align 4
|
||||
ret void
|
||||
}
|
||||
|
|
@ -22,12 +22,12 @@ define void @test1(i32* %ptr, i32 %val1) {
|
|||
define i32 @test2(i32* %ptr) {
|
||||
; ARM: test2
|
||||
; ARM: ldr
|
||||
; ARM-NEXT: dmb ish
|
||||
; ARM-NEXT: dmb {{ish$}}
|
||||
; THUMBONE: test2
|
||||
; THUMBONE: __sync_val_compare_and_swap_4
|
||||
; THUMBTWO: test2
|
||||
; THUMBTWO: ldr
|
||||
; THUMBTWO-NEXT: dmb ish
|
||||
; THUMBTWO-NEXT: dmb {{ish$}}
|
||||
%val = load atomic i32* %ptr seq_cst, align 4
|
||||
ret i32 %val
|
||||
}
|
||||
|
|
@ -69,3 +69,37 @@ define void @test_old_store_64bit(i64* %p, i64 %v) {
|
|||
store atomic i64 %v, i64* %p seq_cst, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; Release operations only need the store barrier provided by a "dmb ishst",
|
||||
|
||||
define void @test_store_release(i32* %p, i32 %v) {
|
||||
; ARM: test_store_release:
|
||||
; ARM: dmb ishst
|
||||
; THUMBTWO: test_store_release:
|
||||
; THUMBTWO: dmb ishst
|
||||
|
||||
store atomic i32 %v, i32* %p release, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; However, if sequential consistency is needed *something* must ensure a release
|
||||
; followed by an acquire does not get reordered. In that case a "dmb ishst" is
|
||||
; not adequate.
|
||||
define i32 @test_seq_cst(i32* %p, i32 %v) {
|
||||
; ARM: test_seq_cst:
|
||||
; ARM: dmb ishst
|
||||
; ARM: str
|
||||
; ARM: dmb {{ish$}}
|
||||
; ARM: ldr
|
||||
; ARM: dmb {{ish$}}
|
||||
|
||||
; THUMBTWO: test_seq_cst:
|
||||
; THUMBTWO: dmb ishst
|
||||
; THUMBTWO: str
|
||||
; THUMBTWO: dmb {{ish$}}
|
||||
; THUMBTWO: ldr
|
||||
; THUMBTWO: dmb {{ish$}}
|
||||
store atomic i32 %v, i32* %p seq_cst, align 4
|
||||
%val = load atomic i32* %p seq_cst, align 4
|
||||
ret i32 %val
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue