[Hexagon] Some cleanup of instruction selection code
llvm-svn: 235552
This commit is contained in:
Krzysztof Parzyszek
parent
4b24f17c27
commit
952d951418
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@ -178,7 +178,7 @@ void HexagonFixupHwLoops::convertLoopInstr(MachineFunction &MF,
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.addReg(Scratch);
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}
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// Then, set the SA0 with the loop start address.
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BuildMI(*MBB, MII, DL, TII->get(Hexagon::CONST32_Label), Scratch)
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BuildMI(*MBB, MII, DL, TII->get(Hexagon::A2_tfrsi), Scratch)
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.addMBB(MII->getOperand(0).getMBB());
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BuildMI(*MBB, MII, DL, TII->get(Hexagon::A2_tfrrcr), Hexagon::SA0)
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.addReg(Scratch);
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File diff suppressed because it is too large
Load Diff
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@ -27,13 +27,11 @@ bool isPositiveHalfWord(SDNode *N);
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namespace HexagonISD {
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enum {
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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OP_BEGIN = ISD::BUILTIN_OP_END,
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CONST32,
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CONST32 = OP_BEGIN,
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CONST32_GP, // For marking data present in GP.
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CONST32_Int_Real,
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FCONST32,
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SETCC,
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ALLOCA,
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ARGEXTEND,
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@ -41,18 +39,6 @@ bool isPositiveHalfWord(SDNode *N);
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AT_GOT,
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AT_PCREL,
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CMPICC, // Compare two GPR operands, set icc.
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CMPFCC, // Compare two FP operands, set fcc.
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BRICC, // Branch to dest on icc condition
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BRFCC, // Branch to dest on fcc condition
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SELECT_ICC, // Select between two values using the current ICC flags.
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SELECT_FCC, // Select between two values using the current FCC flags.
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Hi, Lo, // Hi/Lo operations, typically on a global address.
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FTOI, // FP to Int within a FP register.
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ITOF, // Int to FP within a FP register.
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CALLv3, // A V3+ call instruction.
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CALLv3nr, // A V3+ call instruction that doesn't return.
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CALLR,
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@ -62,6 +48,7 @@ bool isPositiveHalfWord(SDNode *N);
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BARRIER, // Memory barrier.
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JT, // Jump table.
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CP, // Constant pool.
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POPCOUNT,
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COMBINE,
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PACKHL,
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@ -88,17 +75,16 @@ bool isPositiveHalfWord(SDNode *N);
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VCMPWEQ,
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VCMPWGT,
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VCMPWGTU,
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INSERT_ri,
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INSERT_rd,
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INSERT_riv,
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INSERT_rdv,
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EXTRACTU_ri,
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EXTRACTU_rd,
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EXTRACTU_riv,
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EXTRACTU_rdv,
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INSERT,
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INSERTRP,
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EXTRACTU,
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EXTRACTURP,
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TC_RETURN,
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EH_RETURN,
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DCFETCH
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DCFETCH,
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OP_END
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};
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}
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@ -107,30 +93,24 @@ bool isPositiveHalfWord(SDNode *N);
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class HexagonTargetLowering : public TargetLowering {
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int VarArgsFrameOffset; // Frame offset to start of varargs area.
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bool CanReturnSmallStruct(const Function* CalleeFn,
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unsigned& RetSize) const;
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bool CanReturnSmallStruct(const Function* CalleeFn, unsigned& RetSize)
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const;
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void promoteLdStType(EVT VT, EVT PromotedLdStVT);
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const HexagonTargetMachine &HTM;
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const HexagonSubtarget &Subtarget;
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public:
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const HexagonSubtarget *Subtarget;
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explicit HexagonTargetLowering(const TargetMachine &TM,
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const HexagonSubtarget &Subtarget);
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const HexagonSubtarget &ST);
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/// IsEligibleForTailCallOptimization - Check whether the call is eligible
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/// for tail call optimization. Targets which want to do tail call
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/// optimization should implement this function.
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bool
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IsEligibleForTailCallOptimization(SDValue Callee,
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CallingConv::ID CalleeCC,
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bool isVarArg,
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bool isCalleeStructRet,
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bool isCallerStructRet,
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const
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SmallVectorImpl<ISD::OutputArg> &Outs,
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bool IsEligibleForTailCallOptimization(SDValue Callee,
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CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet,
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bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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SelectionDAG& DAG) const;
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const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const;
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bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
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bool isTruncateFree(EVT VT1, EVT VT2) const override;
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@ -152,24 +132,19 @@ bool isPositiveHalfWord(SDNode *N);
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SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFormalArguments(SDValue Chain,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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SDLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const override;
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SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
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bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl,
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SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const override;
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SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const override;
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SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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SDLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals,
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const SmallVectorImpl<SDValue> &OutVals,
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SDValue Callee) const;
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const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl,
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SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
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const SmallVectorImpl<SDValue> &OutVals, SDValue Callee) const;
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SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
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@ -179,14 +154,13 @@ bool isPositiveHalfWord(SDNode *N);
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SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerReturn(SDValue Chain,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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SDLoc dl, SelectionDAG &DAG) const override;
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SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
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bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals, SDLoc dl,
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SelectionDAG &DAG) const override;
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MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr *MI,
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bool mayBeEmittedAsTailCall(CallInst *CI) const override;
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MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *BB) const override;
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SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
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@ -232,6 +206,9 @@ bool isPositiveHalfWord(SDNode *N);
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/// compare a register against the immediate without having to materialize
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/// the immediate into a register.
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bool isLegalICmpImmediate(int64_t Imm) const override;
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private:
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void setHexLibcallName(RTLIB::Libcall Call, Twine Name);
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};
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} // end namespace llvm
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@ -4191,12 +4191,27 @@ def S2_clb : T_COUNT_LEADING_32<"clb", 0b000, 0b100>;
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def S2_clbp : T_COUNT_LEADING_64<"clb", 0b010, 0b000>;
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def S2_clbnorm : T_COUNT_LEADING_32<"normamt", 0b000, 0b111>;
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// Count leading zeros.
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def: Pat<(i32 (ctlz I32:$Rs)), (S2_cl0 I32:$Rs)>;
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def: Pat<(i32 (ctlz (not I32:$Rs))), (S2_cl1 I32:$Rs)>;
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def: Pat<(i32 (cttz I32:$Rs)), (S2_ct0 I32:$Rs)>;
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def: Pat<(i32 (cttz (not I32:$Rs))), (S2_ct1 I32:$Rs)>;
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def: Pat<(i32 (trunc (ctlz I64:$Rss))), (S2_cl0p I64:$Rss)>;
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def: Pat<(i32 (ctlz_zero_undef I32:$Rs)), (S2_cl0 I32:$Rs)>;
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def: Pat<(i32 (trunc (ctlz_zero_undef I64:$Rss))), (S2_cl0p I64:$Rss)>;
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// Count trailing zeros: 32-bit.
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def: Pat<(i32 (cttz I32:$Rs)), (S2_ct0 I32:$Rs)>;
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def: Pat<(i32 (cttz_zero_undef I32:$Rs)), (S2_ct0 I32:$Rs)>;
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// Count leading ones.
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def: Pat<(i32 (ctlz (not I32:$Rs))), (S2_cl1 I32:$Rs)>;
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def: Pat<(i32 (trunc (ctlz (not I64:$Rss)))), (S2_cl1p I64:$Rss)>;
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def: Pat<(i32 (ctlz_zero_undef (not I32:$Rs))), (S2_cl1 I32:$Rs)>;
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def: Pat<(i32 (trunc (ctlz_zero_undef (not I64:$Rss)))), (S2_cl1p I64:$Rss)>;
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// Count trailing ones: 32-bit.
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def: Pat<(i32 (cttz (not I32:$Rs))), (S2_ct1 I32:$Rs)>;
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def: Pat<(i32 (cttz_zero_undef (not I32:$Rs))), (S2_ct1 I32:$Rs)>;
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// The 64-bit counts leading/trailing are defined in HexagonInstrInfoV4.td.
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// Bit set/clear/toggle
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@ -4832,11 +4847,6 @@ def CONST32_Int_Real : CONSTLDInst<(outs IntRegs:$dst), (ins i32imm:$global),
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def: Pat<(HexagonCONST32 tglobaltlsaddr:$addr), (A2_tfrsi s16Ext:$addr)>;
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def: Pat<(HexagonCONST32 bbl:$label), (A2_tfrsi s16Ext:$label)>;
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let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
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def CONST32_Label : LDInst2<(outs IntRegs:$dst), (ins bblabel:$label),
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"$dst = CONST32($label)",
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[(set (i32 IntRegs:$dst), (HexagonCONST32 bbl:$label))]>;
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let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
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def CONST64_Int_Real : CONSTLDInst<(outs DoubleRegs:$dst), (ins i64imm:$global),
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"$dst = CONST64(#$global)",
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@ -5578,41 +5588,34 @@ def S2_insertp_rp : T_S3op_insert<"insert", DoubleRegs>;
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def S2_insertp : T_S2op_insert <0b0011, DoubleRegs, u6Imm>;
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def SDTHexagonINSERT_ri : SDTypeProfile<1, 4, [SDTCisVT<0, i32>,
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SDTCisVT<1, i32>,
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SDTCisVT<2, i32>,
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SDTCisVT<3, i32>,
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SDTCisVT<4, i32>]>;
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def SDTHexagonINSERT_rd : SDTypeProfile<1, 4, [SDTCisVT<0, i64>,
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SDTCisVT<1, i64>,
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SDTCisVT<2, i64>,
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SDTCisVT<3, i32>,
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SDTCisVT<4, i32>]>;
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def SDTHexagonINSERT_riv : SDTypeProfile<1, 3, [SDTCisVT<0, i32>,
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SDTCisVT<1, i32>,
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SDTCisVT<2, i32>,
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SDTCisVT<3, i64>]>;
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def SDTHexagonINSERT_rdv : SDTypeProfile<1, 3, [SDTCisVT<0, i64>,
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SDTCisVT<1, i64>,
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SDTCisVT<2, i64>,
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SDTCisVT<3, i64>]>;
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def HexagonINSERT_ri : SDNode<"HexagonISD::INSERT_ri", SDTHexagonINSERT_ri>;
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def HexagonINSERT_rd : SDNode<"HexagonISD::INSERT_rd", SDTHexagonINSERT_rd>;
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def HexagonINSERT_riv: SDNode<"HexagonISD::INSERT_riv", SDTHexagonINSERT_riv>;
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def HexagonINSERT_rdv: SDNode<"HexagonISD::INSERT_rdv", SDTHexagonINSERT_rdv>;
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def SDTHexagonINSERT:
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SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
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SDTCisInt<0>, SDTCisVT<3, i32>, SDTCisVT<4, i32>]>;
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def SDTHexagonINSERTRP:
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SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
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SDTCisInt<0>, SDTCisVT<3, i64>]>;
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def: Pat<(HexagonINSERT_ri I32:$Rs, I32:$Rt, u5ImmPred:$u1, u5ImmPred:$u2),
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def HexagonINSERT : SDNode<"HexagonISD::INSERT", SDTHexagonINSERT>;
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def HexagonINSERTRP : SDNode<"HexagonISD::INSERTRP", SDTHexagonINSERTRP>;
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def: Pat<(HexagonINSERT I32:$Rs, I32:$Rt, u5ImmPred:$u1, u5ImmPred:$u2),
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(S2_insert I32:$Rs, I32:$Rt, u5ImmPred:$u1, u5ImmPred:$u2)>;
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def: Pat<(HexagonINSERT_rd I64:$Rs, I64:$Rt, u6ImmPred:$u1, u6ImmPred:$u2),
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def: Pat<(HexagonINSERT I64:$Rs, I64:$Rt, u6ImmPred:$u1, u6ImmPred:$u2),
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(S2_insertp I64:$Rs, I64:$Rt, u6ImmPred:$u1, u6ImmPred:$u2)>;
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def: Pat<(HexagonINSERT_riv I32:$Rs, I32:$Rt, I64:$Ru),
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def: Pat<(HexagonINSERTRP I32:$Rs, I32:$Rt, I64:$Ru),
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(S2_insert_rp I32:$Rs, I32:$Rt, I64:$Ru)>;
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def: Pat<(HexagonINSERT_rdv I64:$Rs, I64:$Rt, I64:$Ru),
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def: Pat<(HexagonINSERTRP I64:$Rs, I64:$Rt, I64:$Ru),
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(S2_insertp_rp I64:$Rs, I64:$Rt, I64:$Ru)>;
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let AddedComplexity = 100 in
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def: Pat<(or (or (shl (HexagonINSERT (i32 (zextloadi8 (add I32:$b, 2))),
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(i32 (extloadi8 (add I32:$b, 3))),
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24, 8),
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(i32 16)),
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(shl (i32 (zextloadi8 (add I32:$b, 1))), (i32 8))),
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(zextloadi8 I32:$b)),
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(A2_swiz (L2_loadri_io I32:$b, 0))>;
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//===----------------------------------------------------------------------===//
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// Template class for 'extract bitfield' instructions
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@ -5680,35 +5683,23 @@ let hasNewValue = 1 in {
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def S2_extractu : T_S2op_extract <"extractu", 0b1101, IntRegs, u5Imm>;
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}
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def SDTHexagonEXTRACTU_ri : SDTypeProfile<1, 3, [SDTCisVT<0, i32>,
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SDTCisVT<1, i32>,
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SDTCisVT<2, i32>,
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SDTCisVT<3, i32>]>;
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def SDTHexagonEXTRACTU_rd : SDTypeProfile<1, 3, [SDTCisVT<0, i64>,
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SDTCisVT<1, i64>,
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SDTCisVT<2, i32>,
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SDTCisVT<3, i32>]>;
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def SDTHexagonEXTRACTU_riv : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
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SDTCisVT<1, i32>,
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def SDTHexagonEXTRACTU:
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SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<1>,
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SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
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def SDTHexagonEXTRACTURP:
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SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<1>,
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SDTCisVT<2, i64>]>;
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def SDTHexagonEXTRACTU_rdv : SDTypeProfile<1, 2, [SDTCisVT<0, i64>,
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SDTCisVT<1, i64>,
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SDTCisVT<2, i64>]>;
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def HexagonEXTRACTU_ri : SDNode<"HexagonISD::EXTRACTU_ri", SDTHexagonEXTRACTU_ri>;
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def HexagonEXTRACTU_rd : SDNode<"HexagonISD::EXTRACTU_rd", SDTHexagonEXTRACTU_rd>;
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def HexagonEXTRACTU_riv: SDNode<"HexagonISD::EXTRACTU_riv", SDTHexagonEXTRACTU_riv>;
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def HexagonEXTRACTU_rdv: SDNode<"HexagonISD::EXTRACTU_rdv", SDTHexagonEXTRACTU_rdv>;
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def: Pat<(HexagonEXTRACTU_ri I32:$src1, u5ImmPred:$src2, u5ImmPred:$src3),
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def HexagonEXTRACTU : SDNode<"HexagonISD::EXTRACTU", SDTHexagonEXTRACTU>;
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def HexagonEXTRACTURP : SDNode<"HexagonISD::EXTRACTURP", SDTHexagonEXTRACTURP>;
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def: Pat<(HexagonEXTRACTU I32:$src1, u5ImmPred:$src2, u5ImmPred:$src3),
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(S2_extractu I32:$src1, u5ImmPred:$src2, u5ImmPred:$src3)>;
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def: Pat<(HexagonEXTRACTU_rd I64:$src1, u6ImmPred:$src2, u6ImmPred:$src3),
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def: Pat<(HexagonEXTRACTU I64:$src1, u6ImmPred:$src2, u6ImmPred:$src3),
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(S2_extractup I64:$src1, u6ImmPred:$src2, u6ImmPred:$src3)>;
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def: Pat<(HexagonEXTRACTU_riv I32:$src1, I64:$src2),
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def: Pat<(HexagonEXTRACTURP I32:$src1, I64:$src2),
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(S2_extractu_rp I32:$src1, I64:$src2)>;
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def: Pat<(HexagonEXTRACTU_rdv I64:$src1, I64:$src2),
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def: Pat<(HexagonEXTRACTURP I64:$src1, I64:$src2),
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(S2_extractup_rp I64:$src1, I64:$src2)>;
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// Change the sign of the immediate for Rd=-mpyi(Rs,#u8)
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@ -2325,10 +2325,24 @@ def S2_ct0p : T_COUNT_LEADING_64<"ct0", 0b111, 0b010>;
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def S2_ct1p : T_COUNT_LEADING_64<"ct1", 0b111, 0b100>;
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def S4_clbpnorm : T_COUNT_LEADING_64<"normamt", 0b011, 0b000>;
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def: Pat<(i32 (trunc (cttz (i64 DoubleRegs:$Rss)))),
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(S2_ct0p (i64 DoubleRegs:$Rss))>;
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def: Pat<(i32 (trunc (cttz (not (i64 DoubleRegs:$Rss))))),
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(S2_ct1p (i64 DoubleRegs:$Rss))>;
|
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// Count trailing zeros: 64-bit.
|
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def: Pat<(i32 (trunc (cttz I64:$Rss))), (S2_ct0p I64:$Rss)>;
|
||||
def: Pat<(i32 (trunc (cttz_zero_undef I64:$Rss))), (S2_ct0p I64:$Rss)>;
|
||||
|
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// Count trailing ones: 64-bit.
|
||||
def: Pat<(i32 (trunc (cttz (not I64:$Rss)))), (S2_ct1p I64:$Rss)>;
|
||||
def: Pat<(i32 (trunc (cttz_zero_undef (not I64:$Rss)))), (S2_ct1p I64:$Rss)>;
|
||||
|
||||
// Define leading/trailing patterns that require zero-extensions to 64 bits.
|
||||
def: Pat<(i64 (ctlz I64:$Rss)), (Zext64 (S2_cl0p I64:$Rss))>;
|
||||
def: Pat<(i64 (ctlz_zero_undef I64:$Rss)), (Zext64 (S2_cl0p I64:$Rss))>;
|
||||
def: Pat<(i64 (cttz I64:$Rss)), (Zext64 (S2_ct0p I64:$Rss))>;
|
||||
def: Pat<(i64 (cttz_zero_undef I64:$Rss)), (Zext64 (S2_ct0p I64:$Rss))>;
|
||||
def: Pat<(i64 (ctlz (not I64:$Rss))), (Zext64 (S2_cl1p I64:$Rss))>;
|
||||
def: Pat<(i64 (ctlz_zero_undef (not I64:$Rss))), (Zext64 (S2_cl1p I64:$Rss))>;
|
||||
def: Pat<(i64 (cttz (not I64:$Rss))), (Zext64 (S2_ct1p I64:$Rss))>;
|
||||
def: Pat<(i64 (cttz_zero_undef (not I64:$Rss))), (Zext64 (S2_ct1p I64:$Rss))>;
|
||||
|
||||
|
||||
let hasSideEffects = 0, hasNewValue = 1 in
|
||||
def S4_clbaddi : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s6Imm:$s6),
|
||||
|
|
@ -3784,9 +3798,6 @@ def: Pat<(HexagonCONST32 tglobaladdr:$Rs), (A2_tfrsi s16Ext:$Rs)>;
|
|||
def: Pat<(HexagonCONST32_GP tblockaddress:$Rs), (A2_tfrsi s16Ext:$Rs)>;
|
||||
def: Pat<(HexagonCONST32_GP tglobaladdr:$Rs), (A2_tfrsi s16Ext:$Rs)>;
|
||||
|
||||
def: Pat<(i64 (ctlz I64:$src1)), (Zext64 (S2_cl0p I64:$src1))>;
|
||||
def: Pat<(i64 (cttz I64:$src1)), (Zext64 (S2_ct0p I64:$src1))>;
|
||||
|
||||
let AddedComplexity = 30 in {
|
||||
def: Storea_pat<truncstorei8, I32, u32ImmPred, S2_storerbabs>;
|
||||
def: Storea_pat<truncstorei16, I32, u32ImmPred, S2_storerhabs>;
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
|
||||
; RUN: llc -march=hexagon -ifcvt-limit=0 < %s | FileCheck %s
|
||||
|
||||
; Check if the branch probabilities are reflected in the instructions:
|
||||
; The basic block placement pass should place the more probable successor
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
; RUN: llc -march=hexagon -hexagon-expand-condsets=0 < %s | FileCheck %s
|
||||
|
||||
; CHECK: r{{[0-9]+:[0-9]+}} = #0
|
||||
; CHECK: r{{[0-9]+:[0-9]+}} = #1
|
||||
; CHECK: r{{[0-9]+:[0-9]+}} = #0
|
||||
; CHECK: r{{[0-9]+:[0-9]+}} = add(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
|
||||
; CHECK: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
|
||||
; CHECK: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
|
||||
|
|
|
|||
|
|
@ -1,8 +1,10 @@
|
|||
; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
|
||||
|
||||
; CHECK: r{{[0-9]+}}:{{[0-9]+}} |= lsr(r{{[0-9]+}}:{{[0-9]+}}, #4)
|
||||
; CHECK: r{{[0-9]+}}:{{[0-9]+}} &= lsr(r{{[0-9]+}}:{{[0-9]+}}, #2)
|
||||
; CHECK: r{{[0-9]+}} += lsr(r{{[0-9]+}}, #4)
|
||||
; CHECK-DAG: ct0({{r[0-9]*:[0-9]*}})
|
||||
; CHECK-DAG: cl0({{r[0-9]*:[0-9]*}})
|
||||
; CHECK-DAG: ct0({{r[0-9]*}})
|
||||
; CHECK-DAG: cl0({{r[0-9]*}})
|
||||
; CHECK-DAG: r{{[0-9]+}} += lsr(r{{[0-9]+}}, #4)
|
||||
|
||||
define i32 @foo(i64 %a, i32 %b) nounwind {
|
||||
entry:
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
|
||||
; Check that we generate integer multiply accumulate.
|
||||
|
||||
; CHECK: r{{[0-9]+}} += mpyi(r{{[0-9]+}}, r{{[0-9]+}})
|
||||
; CHECK: r{{[0-9]+}} {{\+|\-}}= mpyi(r{{[0-9]+}},
|
||||
|
||||
define i32 @main(i32* %a, i32* %b) nounwind {
|
||||
entry:
|
||||
|
|
|
|||
|
|
@ -1,17 +1,16 @@
|
|||
; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
|
||||
; RUN: llc -march=hexagon -mcpu=hexagonv5 -disable-hexagon-misched < %s \
|
||||
; RUN: | FileCheck %s
|
||||
; Check that we generate new value jump, both registers, with one
|
||||
; of the registers as new.
|
||||
|
||||
@Reg = common global i8 0, align 1
|
||||
@Reg = common global i32 0, align 4
|
||||
define i32 @main() nounwind {
|
||||
entry:
|
||||
; CHECK: if (cmp.gt(r{{[0-9]+}}.new, r{{[0-9]+}})) jump:{{[t|nt]}} .LBB{{[0-9]+}}_{{[0-9]+}}
|
||||
%Reg2 = alloca i8, align 1
|
||||
%0 = load i8, i8* %Reg2, align 1
|
||||
%conv0 = zext i8 %0 to i32
|
||||
%1 = load i8, i8* @Reg, align 1
|
||||
%conv1 = zext i8 %1 to i32
|
||||
%tobool = icmp sle i32 %conv0, %conv1
|
||||
; CHECK: if (cmp.gt(r{{[0-9]+}}, r{{[0-9]+}}.new)) jump:{{[t|nt]}} .LBB{{[0-9]+}}_{{[0-9]+}}
|
||||
%Reg2 = alloca i32, align 4
|
||||
%0 = load i32, i32* %Reg2, align 4
|
||||
%1 = load i32, i32* @Reg, align 4
|
||||
%tobool = icmp sle i32 %0, %1
|
||||
br i1 %tobool, label %if.then, label %if.else
|
||||
|
||||
if.then:
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
; RUN: llc -march=hexagon -hexagon-expand-condsets=0 < %s | FileCheck %s
|
||||
|
||||
; CHECK: r{{[0-9]+:[0-9]+}} = #0
|
||||
; CHECK: r{{[0-9]+:[0-9]+}} = #1
|
||||
; CHECK: r{{[0-9]+:[0-9]+}} = #0
|
||||
; CHECK: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
|
||||
; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})
|
||||
; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})
|
||||
|
|
|
|||
Loading…
Reference in New Issue