[X86] Add addsub intrinsics to the intrinsic lowering table so we have a single set of isel patterns.
llvm-svn: 309502
This commit is contained in:
Craig Topper
parent
6e4d774b02
commit
951f0ca104
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@ -5098,7 +5098,7 @@ def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
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// SSE3 - Arithmetic
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//===---------------------------------------------------------------------===//
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multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
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multiclass sse3_addsub<string OpcodeStr, ValueType vt, RegisterClass RC,
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X86MemOperand x86memop, OpndItins itins,
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PatFrag ld_frag, bit Is2Addr = 1> {
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def rr : I<0xD0, MRMSrcReg,
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@ -5106,70 +5106,42 @@ multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>,
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[(set RC:$dst, (vt (X86Addsub RC:$src1, RC:$src2)))], itins.rr>,
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Sched<[itins.Sched]>;
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def rm : I<0xD0, MRMSrcMem,
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(outs RC:$dst), (ins RC:$src1, x86memop:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))], itins.rr>,
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Sched<[itins.Sched.Folded, ReadAfterLd]>;
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[(set RC:$dst, (vt (X86Addsub RC:$src1, (ld_frag addr:$src2))))],
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itins.rr>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
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}
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let Predicates = [HasAVX] in {
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let ExeDomain = SSEPackedSingle in {
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defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
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f128mem, SSE_ALU_F32P, loadv4f32, 0>, XD, VEX_4V, VEX_WIG;
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defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
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f256mem, SSE_ALU_F32P, loadv8f32, 0>, XD, VEX_4V, VEX_L, VEX_WIG;
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defm VADDSUBPS : sse3_addsub<"vaddsubps", v4f32, VR128, f128mem,
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SSE_ALU_F32P, loadv4f32, 0>, XD, VEX_4V,
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VEX_WIG;
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defm VADDSUBPSY : sse3_addsub<"vaddsubps", v8f32, VR256, f256mem,
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SSE_ALU_F32P, loadv8f32, 0>, XD, VEX_4V,
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VEX_L, VEX_WIG;
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}
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let ExeDomain = SSEPackedDouble in {
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defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
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f128mem, SSE_ALU_F64P, loadv2f64, 0>, PD, VEX_4V, VEX_WIG;
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defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
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f256mem, SSE_ALU_F64P, loadv4f64, 0>, PD, VEX_4V, VEX_L, VEX_WIG;
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defm VADDSUBPD : sse3_addsub<"vaddsubpd", v2f64, VR128, f128mem,
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SSE_ALU_F64P, loadv2f64, 0>, PD, VEX_4V,
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VEX_WIG;
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defm VADDSUBPDY : sse3_addsub<"vaddsubpd", v4f64, VR256, f256mem,
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SSE_ALU_F64P, loadv4f64, 0>, PD, VEX_4V,
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VEX_L, VEX_WIG;
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}
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}
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let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
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let ExeDomain = SSEPackedSingle in
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defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
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f128mem, SSE_ALU_F32P, memopv4f32>, XD;
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defm ADDSUBPS : sse3_addsub<"addsubps", v4f32, VR128, f128mem, SSE_ALU_F32P,
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memopv4f32>, XD;
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let ExeDomain = SSEPackedDouble in
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defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
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f128mem, SSE_ALU_F64P, memopv2f64>, PD;
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}
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// Patterns used to select 'addsub' instructions.
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let Predicates = [HasAVX] in {
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def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 VR128:$rhs))),
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(VADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
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def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (loadv4f32 addr:$rhs))),
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(VADDSUBPSrm VR128:$lhs, f128mem:$rhs)>;
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def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 VR128:$rhs))),
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(VADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
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def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (loadv2f64 addr:$rhs))),
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(VADDSUBPDrm VR128:$lhs, f128mem:$rhs)>;
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def : Pat<(v8f32 (X86Addsub (v8f32 VR256:$lhs), (v8f32 VR256:$rhs))),
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(VADDSUBPSYrr VR256:$lhs, VR256:$rhs)>;
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def : Pat<(v8f32 (X86Addsub (v8f32 VR256:$lhs), (loadv8f32 addr:$rhs))),
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(VADDSUBPSYrm VR256:$lhs, f256mem:$rhs)>;
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def : Pat<(v4f64 (X86Addsub (v4f64 VR256:$lhs), (v4f64 VR256:$rhs))),
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(VADDSUBPDYrr VR256:$lhs, VR256:$rhs)>;
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def : Pat<(v4f64 (X86Addsub (v4f64 VR256:$lhs), (loadv4f64 addr:$rhs))),
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(VADDSUBPDYrm VR256:$lhs, f256mem:$rhs)>;
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}
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let Predicates = [UseSSE3] in {
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def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 VR128:$rhs))),
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(ADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
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def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (memopv4f32 addr:$rhs))),
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(ADDSUBPSrm VR128:$lhs, f128mem:$rhs)>;
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def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 VR128:$rhs))),
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(ADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
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def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (memopv2f64 addr:$rhs))),
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(ADDSUBPDrm VR128:$lhs, f128mem:$rhs)>;
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defm ADDSUBPD : sse3_addsub<"addsubpd", v2f64, VR128, f128mem, SSE_ALU_F64P,
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memopv2f64>, PD;
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}
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//===---------------------------------------------------------------------===//
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@ -342,6 +342,8 @@ static const IntrinsicData* getIntrinsicWithChain(uint16_t IntNo) {
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* the alphabetical order.
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*/
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static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86_INTRINSIC_DATA(avx_addsub_pd_256, INTR_TYPE_2OP, X86ISD::ADDSUB, 0),
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X86_INTRINSIC_DATA(avx_addsub_ps_256, INTR_TYPE_2OP, X86ISD::ADDSUB, 0),
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X86_INTRINSIC_DATA(avx_cmp_pd_256, INTR_TYPE_3OP, X86ISD::CMPP, 0),
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X86_INTRINSIC_DATA(avx_cmp_ps_256, INTR_TYPE_3OP, X86ISD::CMPP, 0),
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X86_INTRINSIC_DATA(avx_cvt_pd2_ps_256,CVTPD2PS, ISD::FP_ROUND, 0),
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@ -1650,6 +1652,8 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86_INTRINSIC_DATA(sse2_ucomile_sd, COMI, X86ISD::UCOMI, ISD::SETLE),
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X86_INTRINSIC_DATA(sse2_ucomilt_sd, COMI, X86ISD::UCOMI, ISD::SETLT),
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X86_INTRINSIC_DATA(sse2_ucomineq_sd, COMI, X86ISD::UCOMI, ISD::SETNE),
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X86_INTRINSIC_DATA(sse3_addsub_pd, INTR_TYPE_2OP, X86ISD::ADDSUB, 0),
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X86_INTRINSIC_DATA(sse3_addsub_ps, INTR_TYPE_2OP, X86ISD::ADDSUB, 0),
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X86_INTRINSIC_DATA(sse3_hadd_pd, INTR_TYPE_2OP, X86ISD::FHADD, 0),
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X86_INTRINSIC_DATA(sse3_hadd_ps, INTR_TYPE_2OP, X86ISD::FHADD, 0),
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X86_INTRINSIC_DATA(sse3_hsub_pd, INTR_TYPE_2OP, X86ISD::FHSUB, 0),
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