[VE] Add vector load/store instructions
Add vector registers and vector load/store instructions. Add regression tests for vector load/store instructions too. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D89183
This commit is contained in:
Kazushi (Jam) Marukawa
parent
4cb4db11ee
commit
94c18d91d2
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@ -95,6 +95,25 @@ static const unsigned F128RegDecoderTable[] = {
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VE::Q16, VE::Q17, VE::Q18, VE::Q19, VE::Q20, VE::Q21, VE::Q22, VE::Q23,
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VE::Q24, VE::Q25, VE::Q26, VE::Q27, VE::Q28, VE::Q29, VE::Q30, VE::Q31};
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static const unsigned V64RegDecoderTable[] = {
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VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7,
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VE::V8, VE::V9, VE::V10, VE::V11, VE::V12, VE::V13, VE::V14, VE::V15,
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VE::V16, VE::V17, VE::V18, VE::V19, VE::V20, VE::V21, VE::V22, VE::V23,
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VE::V24, VE::V25, VE::V26, VE::V27, VE::V28, VE::V29, VE::V30, VE::V31,
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VE::V32, VE::V33, VE::V34, VE::V35, VE::V36, VE::V37, VE::V38, VE::V39,
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VE::V40, VE::V41, VE::V42, VE::V43, VE::V44, VE::V45, VE::V46, VE::V47,
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VE::V48, VE::V49, VE::V50, VE::V51, VE::V52, VE::V53, VE::V54, VE::V55,
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VE::V56, VE::V57, VE::V58, VE::V59, VE::V60, VE::V61, VE::V62, VE::V63};
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static const unsigned VMRegDecoderTable[] = {
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VE::VM0, VE::VM1, VE::VM2, VE::VM3, VE::VM4, VE::VM5,
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VE::VM6, VE::VM7, VE::VM8, VE::VM9, VE::VM10, VE::VM11,
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VE::VM12, VE::VM13, VE::VM14, VE::VM15};
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static const unsigned VM512RegDecoderTable[] = {VE::VMP0, VE::VMP1, VE::VMP2,
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VE::VMP3, VE::VMP4, VE::VMP5,
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VE::VMP6, VE::VMP7};
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static const unsigned MiscRegDecoderTable[] = {
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VE::USRCC, VE::PSW, VE::SAR, VE::NoRegister,
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VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::PMMR,
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@ -145,6 +164,40 @@ static DecodeStatus DecodeF128RegisterClass(MCInst &Inst, unsigned RegNo,
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeV64RegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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unsigned Reg = VE::NoRegister;
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if (RegNo == 255)
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Reg = VE::VIX;
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else if (RegNo > 63)
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return MCDisassembler::Fail;
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else
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Reg = V64RegDecoderTable[RegNo];
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeVMRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 15)
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return MCDisassembler::Fail;
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unsigned Reg = VMRegDecoderTable[RegNo];
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeVM512RegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo % 2 || RegNo > 15)
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return MCDisassembler::Fail;
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unsigned Reg = VM512RegDecoderTable[RegNo / 2];
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeMISCRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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@ -634,6 +634,47 @@ VETargetLowering::VETargetLowering(const TargetMachine &TM,
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addRegisterClass(MVT::f64, &VE::I64RegClass);
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addRegisterClass(MVT::f128, &VE::F128RegClass);
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addRegisterClass(MVT::v2i32, &VE::V64RegClass);
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addRegisterClass(MVT::v4i32, &VE::V64RegClass);
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addRegisterClass(MVT::v8i32, &VE::V64RegClass);
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addRegisterClass(MVT::v16i32, &VE::V64RegClass);
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addRegisterClass(MVT::v32i32, &VE::V64RegClass);
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addRegisterClass(MVT::v64i32, &VE::V64RegClass);
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addRegisterClass(MVT::v128i32, &VE::V64RegClass);
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addRegisterClass(MVT::v256i32, &VE::V64RegClass);
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addRegisterClass(MVT::v512i32, &VE::V64RegClass);
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addRegisterClass(MVT::v2i64, &VE::V64RegClass);
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addRegisterClass(MVT::v4i64, &VE::V64RegClass);
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addRegisterClass(MVT::v8i64, &VE::V64RegClass);
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addRegisterClass(MVT::v16i64, &VE::V64RegClass);
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addRegisterClass(MVT::v32i64, &VE::V64RegClass);
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addRegisterClass(MVT::v64i64, &VE::V64RegClass);
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addRegisterClass(MVT::v128i64, &VE::V64RegClass);
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addRegisterClass(MVT::v256i64, &VE::V64RegClass);
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addRegisterClass(MVT::v2f32, &VE::V64RegClass);
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addRegisterClass(MVT::v4f32, &VE::V64RegClass);
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addRegisterClass(MVT::v8f32, &VE::V64RegClass);
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addRegisterClass(MVT::v16f32, &VE::V64RegClass);
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addRegisterClass(MVT::v32f32, &VE::V64RegClass);
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addRegisterClass(MVT::v64f32, &VE::V64RegClass);
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addRegisterClass(MVT::v128f32, &VE::V64RegClass);
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addRegisterClass(MVT::v256f32, &VE::V64RegClass);
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addRegisterClass(MVT::v512f32, &VE::V64RegClass);
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addRegisterClass(MVT::v2f64, &VE::V64RegClass);
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addRegisterClass(MVT::v4f64, &VE::V64RegClass);
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addRegisterClass(MVT::v8f64, &VE::V64RegClass);
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addRegisterClass(MVT::v16f64, &VE::V64RegClass);
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addRegisterClass(MVT::v32f64, &VE::V64RegClass);
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addRegisterClass(MVT::v64f64, &VE::V64RegClass);
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addRegisterClass(MVT::v128f64, &VE::V64RegClass);
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addRegisterClass(MVT::v256f64, &VE::V64RegClass);
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addRegisterClass(MVT::v256i1, &VE::VMRegClass);
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addRegisterClass(MVT::v512i1, &VE::VM512RegClass);
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/// Load & Store {
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// VE doesn't have i1 sign extending load.
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@ -35,6 +35,25 @@ class InstVE<dag outs, dag ins, string asmstr, list<dag> pattern>
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let AsmString = asmstr;
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let Pattern = pattern;
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bits<1> VE_Vector = 0;
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bits<1> VE_VLInUse = 0;
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bits<3> VE_VLIndex = 0;
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bits<1> VE_VLWithMask = 0;
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/// These fields correspond to the fields in VEInstrInfo.h. Any changes to
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/// these must be reflected there! See comments there for what these are.
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///
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/// VLIndex is the index of VL register in MI's operands. The HW instruction
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/// doesn't have that field, but we add is in MI for the ease of optimization.
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/// For example, the index of VL of (VST $sy, $sz, $sx, $vl) is 3 (beginning
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/// from 0), and the index of VL of (VST $sy, $sz, $sx, $vm, $vl) is 4. We
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/// define vector instructions hierarchically, so use VE_VLIndex which is
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/// defined by the type of instruction and VE_VLWithMask which is defined
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/// whether the insturction use mask or not.
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let TSFlags{0} = VE_Vector;
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let TSFlags{1} = VE_VLInUse;
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let TSFlags{4-2} = !add(VE_VLIndex, VE_VLWithMask);
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let DecoderNamespace = "VE";
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field bits<64> SoftFail = 0;
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}
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@ -179,8 +198,43 @@ class RRFENCE<bits<8>opVal, dag outs, dag ins, string asmstr,
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//-----------------------------------------------------------------------------
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// Section 5.6 RVM Type
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//
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// RVM type is for vector transfer instructions.
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//-----------------------------------------------------------------------------
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class RVM<bits<8>opVal, dag outs, dag ins, string asmstr,
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list<dag> pattern = []>
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: InstVE<outs, ins, asmstr, pattern> {
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bits<1> cx = 0;
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bits<1> vc = 0;
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bits<1> cs = 0;
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bits<4> m = 0;
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bits<1> cy = 1;
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bits<7> sy;
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bits<1> cz = 1;
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bits<7> sz;
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bits<8> vx;
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bits<8> vy = 0;
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bits<7> sw = 0;
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let op = opVal;
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let Inst{55} = cx;
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let Inst{54} = vc;
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let Inst{53} = cs;
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let Inst{52} = 0;
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let Inst{51-48} = m;
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let Inst{47} = cy;
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let Inst{46-40} = sy;
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let Inst{39} = cz;
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let Inst{38-32} = sz;
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let Inst{31-24} = vx;
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let Inst{23-16} = vy;
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let Inst{15-8} = 0;
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let Inst{7} = 0;
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let Inst{6-0} = sw;
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let VE_Vector = 1;
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}
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//-----------------------------------------------------------------------------
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// Section 5.7 RV Type
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//-----------------------------------------------------------------------------
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@ -23,6 +23,31 @@ namespace llvm {
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class VESubtarget;
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/// VEII - This namespace holds all of the Aurora VE target-specific
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/// per-instruction flags. These must match the corresponding definitions in
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/// VEInstrFormats.td.
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namespace VEII {
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enum {
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// Aurora VE Instruction Flags. These flags describe the characteristics of
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// the Aurora VE instructions for vector handling.
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/// VE_Vector - This instruction is Vector Instruction.
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VE_Vector = 0x1,
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/// VE_VLInUse - This instruction has a vector register in its operands.
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VE_VLInUse = 0x2,
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/// VE_VLMask/Shift - This is a bitmask that selects the index number where
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/// an instruction holds vector length informatio (0 to 6, 7 means undef).n
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VE_VLShift = 2,
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VE_VLMask = 0x07 << VE_VLShift,
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};
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#define HAS_VLINDEX(TSF) ((TSF)&VEII::VE_VLInUse)
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#define GET_VLINDEX(TSF) \
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(HAS_VLINDEX(TSF) ? (int)(((TSF)&VEII::VE_VLMask) >> VEII::VE_VLShift) : -1)
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} // end namespace VEII
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class VEInstrInfo : public VEGenInstrInfo {
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const VERegisterInfo RI;
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virtual void anchor();
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@ -2035,3 +2035,6 @@ def : Pat<(i32 (and i32:$val, 0xffff)),
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!add(48, 64)), sub_i32)>;
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def : Pat<(i64 (and i64:$val, 0xffffffff)),
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(ANDrm $val, !add(32, 64))>;
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// Vector instructions.
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include "VEInstrVec.td"
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@ -0,0 +1,146 @@
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//===----------------------------------------------------------------------===//
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// Vector Instructions
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instructions
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//
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// Define all vector instructions defined in SX-Aurora TSUBASA Architecture
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// Guide here. As those mnemonics, we use mnemonics defined in Vector Engine
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// Assembly Language Reference Manual.
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//
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// Some instructions can update existing data by following instructions
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// sequence.
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//
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// lea %s0, 256
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// lea %s1, 128
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// lvl %s0
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// vbrd %v0, 2 # v0 = { 2, 2, 2, ..., 2, 2, 2 }
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// lvl %s1
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// vbrd %v0, 3 # v0 = { 3, 3, 3, ..., 3, 2, 2, 2, ..., 2, 2, 2 }
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//
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// In order to represent above with a virtual register, we defines instructions
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// with an additional base register and `_v` suffiex in mnemonic.
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//
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// lea t0, 256
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// lea t1, 128
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// lea t0
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// vbrd tv0, 2
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// lvl t1
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// vbrd_v tv1, 2, tv0
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//
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// We also have some instructions uses VL register with an pseudo VL value
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// with following suffixes in mnemonic.
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//
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// l: have an additional I32 register to represent the VL value.
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// L: have an additional VL register to represent the VL value.
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//===----------------------------------------------------------------------===//
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//-----------------------------------------------------------------------------
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// Section 8.9 - Vector Load/Store and Move Instructions
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//-----------------------------------------------------------------------------
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// Multiclass for VLD instructions
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let mayLoad = 1, hasSideEffects = 0, Uses = [VL] in
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multiclass VLDbm<string opcStr, bits<8>opc, RegisterClass RC, dag dag_in,
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string disEnc = ""> {
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let DisableEncoding = disEnc in
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def "" : RVM<opc, (outs RC:$vx), dag_in,
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!strconcat(opcStr, " $vx, $sy, $sz")>;
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let Constraints = "$vx = $base", DisableEncoding = disEnc#"$base",
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isCodeGenOnly = 1 in
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def _v : RVM<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),
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!strconcat(opcStr, " $vx, $sy, $sz")>;
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}
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multiclass VLDlm<string opcStr, bits<8>opc, RegisterClass RC, dag dag_in> {
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defm "" : VLDbm<opcStr, opc, RC, dag_in>;
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let isCodeGenOnly = 1, VE_VLInUse = 1 in {
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defm l : VLDbm<opcStr, opc, RC, !con(dag_in, (ins I32:$vl)), "$vl,">;
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defm L : VLDbm<opcStr, opc, RC, !con(dag_in, (ins VLS:$vl)), "$vl,">;
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}
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}
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let VE_VLIndex = 3 in
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multiclass VLDtgm<string opcStr, bits<8>opc, RegisterClass RC> {
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defm rr : VLDlm<opcStr, opc, RC, (ins I64:$sy, I64:$sz)>;
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let cy = 0 in
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defm ir : VLDlm<opcStr, opc, RC, (ins simm7:$sy, I64:$sz)>;
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let cz = 0 in
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defm rz : VLDlm<opcStr, opc, RC, (ins I64:$sy, zero:$sz)>;
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let cy = 0, cz = 0 in
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defm iz : VLDlm<opcStr, opc, RC, (ins simm7:$sy, zero:$sz)>;
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}
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multiclass VLDm<string opcStr, bits<8>opc, RegisterClass RC> {
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let vc = 1 in defm "" : VLDtgm<opcStr, opc, RC>;
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let vc = 0 in defm NC : VLDtgm<opcStr#".nc", opc, RC>;
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}
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// Section 8.9.1 - VLD (Vector Load)
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defm VLD : VLDm<"vld", 0x81, V64>;
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// Section 8.9.2 - VLDU (Vector Load Upper)
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defm VLDU : VLDm<"vldu", 0x82, V64>;
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// Section 8.9.3 - VLDL (Vector Load Lower)
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defm VLDLSX : VLDm<"vldl.sx", 0x83, V64>;
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let cx = 1 in defm VLDLZX : VLDm<"vldl.zx", 0x83, V64>;
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// Section 8.9.4 - VLD2D (Vector Load 2D)
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defm VLD2D : VLDm<"vld2d", 0xc1, V64>;
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// Section 8.9.5 - VLDU2D (Vector Load Upper 2D)
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defm VLDU2D : VLDm<"vldu2d", 0xc2, V64>;
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// Section 8.9.6 - VLDL2D (Vector Load Lower 2D)
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defm VLDL2DSX : VLDm<"vldl2d.sx", 0xc3, V64>;
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let cx = 1 in defm VLDL2DZX : VLDm<"vldl2d.zx", 0xc3, V64>;
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// Multiclass for VST instructions
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let mayStore = 1, hasSideEffects = 0, Uses = [VL] in
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multiclass VSTbm<string opcStr, string argStr, bits<8>opc, dag dag_in> {
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def "" : RVM<opc, (outs), dag_in, !strconcat(opcStr, argStr)>;
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let DisableEncoding = "$vl", isCodeGenOnly = 1, VE_VLInUse = 1 in {
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def l : RVM<opc, (outs), !con(dag_in, (ins I32:$vl)),
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!strconcat(opcStr, argStr)>;
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def L : RVM<opc, (outs), !con(dag_in, (ins VLS:$vl)),
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!strconcat(opcStr, argStr)>;
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}
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}
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multiclass VSTmm<string opcStr, bits<8>opc, dag dag_in> {
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defm "" : VSTbm<opcStr, " $vx, $sy, $sz", opc, dag_in>;
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let m = ?, VE_VLWithMask = 1 in
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defm m : VSTbm<opcStr, " $vx, $sy, $sz, $m", opc, !con(dag_in, (ins VM:$m))>;
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}
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let VE_VLIndex = 3 in
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multiclass VSTtgm<string opcStr, bits<8>opc, RegisterClass RC> {
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defm rrv : VSTmm<opcStr, opc, (ins I64:$sy, I64:$sz, RC:$vx)>;
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let cy = 0 in
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defm irv : VSTmm<opcStr, opc, (ins simm7:$sy, I64:$sz, RC:$vx)>;
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let cz = 0 in
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defm rzv : VSTmm<opcStr, opc, (ins I64:$sy, zero:$sz, RC:$vx)>;
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let cy = 0, cz = 0 in
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defm izv : VSTmm<opcStr, opc, (ins simm7:$sy, zero:$sz, RC:$vx)>;
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}
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multiclass VSTm<string opcStr, bits<8>opc, RegisterClass RC> {
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let vc = 1, cx = 0 in defm "" : VSTtgm<opcStr, opc, RC>;
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let vc = 0, cx = 0 in defm NC : VSTtgm<opcStr#".nc", opc, RC>;
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let vc = 1, cx = 1 in defm OT : VSTtgm<opcStr#".ot", opc, RC>;
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let vc = 0, cx = 1 in defm NCOT : VSTtgm<opcStr#".nc.ot", opc, RC>;
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}
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// Section 8.9.7 - VST (Vector Store)
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defm VST : VSTm<"vst", 0x91, V64>;
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// Section 8.9.8 - VST (Vector Store Upper)
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defm VSTU : VSTm<"vstu", 0x92, V64>;
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// Section 8.9.9 - VSTL (Vector Store Lower)
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defm VSTL : VSTm<"vstl", 0x93, V64>;
|
||||
|
||||
// Section 8.9.10 - VST2D (Vector Store 2D)
|
||||
defm VST2D : VSTm<"vst2d", 0xd1, V64>;
|
||||
|
||||
// Section 8.9.11 - VSTU2D (Vector Store Upper 2D)
|
||||
defm VSTU2D : VSTm<"vstu2d", 0xd2, V64>;
|
||||
|
||||
// Section 8.9.12 - VSTL2D (Vector Store Lower 2D)
|
||||
defm VSTL2D : VSTm<"vstl2d", 0xd3, V64>;
|
||||
|
|
@ -26,11 +26,33 @@ class VEMiscReg<bits<6> enc, string n>: Register<n> {
|
|||
let Namespace = "VE";
|
||||
}
|
||||
|
||||
class VEVecReg<bits<8> enc, string n, list<Register> subregs = [],
|
||||
list<string> altNames = [], list<Register> aliases = []>
|
||||
: Register<n, altNames> {
|
||||
let HWEncoding{15-8} = 0;
|
||||
let HWEncoding{7-0} = enc;
|
||||
let Namespace = "VE";
|
||||
let SubRegs = subregs;
|
||||
let Aliases = aliases;
|
||||
}
|
||||
|
||||
class VEMaskReg<bits<4> enc, string n, list<Register> subregs = [],
|
||||
list<string> altNames = [], list<Register> aliases = []>
|
||||
: Register<n, altNames> {
|
||||
let HWEncoding{15-4} = 0;
|
||||
let HWEncoding{3-0} = enc;
|
||||
let Namespace = "VE";
|
||||
let SubRegs = subregs;
|
||||
let Aliases = aliases;
|
||||
}
|
||||
|
||||
let Namespace = "VE" in {
|
||||
def sub_i32 : SubRegIndex<32, 32>; // Low 32 bit (32..63)
|
||||
def sub_f32 : SubRegIndex<32>; // High 32 bit (0..31)
|
||||
def sub_even : SubRegIndex<64>; // High 64 bit (0..63)
|
||||
def sub_odd : SubRegIndex<64, 64>; // Low 64 bit (64..127)
|
||||
def sub_vm_even : SubRegIndex<256>; // High 256 bit (0..255)
|
||||
def sub_vm_odd : SubRegIndex<256, 256>; // Low 256 bit (256..511)
|
||||
def AsmName : RegAltNameIndex;
|
||||
}
|
||||
|
||||
|
|
@ -63,6 +85,15 @@ def MISC : RegisterClass<"VE", [i64], 64,
|
|||
|
||||
def IC : VEMiscReg<62, "ic">;
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Vector Length Register
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
def VL : VEMiscReg<63, "vl">;
|
||||
|
||||
// Register classes.
|
||||
def VLS : RegisterClass<"VE", [i32], 64, (add VL)>;
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Generic Registers
|
||||
//-----------------------------------------------------------------------------
|
||||
|
|
@ -98,6 +129,25 @@ foreach I = 0-31 in
|
|||
!cast<VEReg>("SX"#!add(!shl(I,1),1))],
|
||||
["s"#!shl(I,1)]>;
|
||||
|
||||
// Vector registers - 64 bits wide 256 elements
|
||||
foreach I = 0-63 in
|
||||
def V#I : VEVecReg<I, "v"#I, [], ["v"#I]>, DwarfRegNum<[!add(64,I)]>;
|
||||
|
||||
// Vector Index Register
|
||||
def VIX : VEVecReg<255, "vix", [], ["vix"]>;
|
||||
|
||||
// Vector mask registers - 256 bits wide
|
||||
foreach I = 0-15 in
|
||||
def VM#I : VEMaskReg<I, "vm"#I, [], ["vm"#I]>, DwarfRegNum<[!add(128,I)]>;
|
||||
|
||||
// Aliases of VMs to use as a pair of two VM for packed instructions
|
||||
let SubRegIndices = [sub_vm_even, sub_vm_odd], CoveredBySubRegs = 1 in
|
||||
foreach I = 0-7 in
|
||||
def VMP#I : VEMaskReg<!shl(I,1), "vmp"#I,
|
||||
[!cast<VEMaskReg>("VM"#!shl(I,1)),
|
||||
!cast<VEMaskReg>("VM"#!add(!shl(I,1),1))],
|
||||
["vm"#!shl(I,1)]>;
|
||||
|
||||
} // RegAltNameIndices = [AsmName]
|
||||
|
||||
// Register classes.
|
||||
|
|
@ -120,3 +170,20 @@ def F128 : RegisterClass<"VE", [f128], 128,
|
|||
(add (sequence "Q%u", 0, 3),
|
||||
(sequence "Q%u", 17, 31),
|
||||
(sequence "Q%u", 4, 16))>;
|
||||
|
||||
def V64 : RegisterClass<"VE",
|
||||
[v512i32, v512f32,
|
||||
v256i64, v256i32, v256f32, v256f64,
|
||||
v128i64, v128i32, v128f32, v128f64,
|
||||
v64i64, v64i32, v64f32, v64f64,
|
||||
v32i64, v32i32, v32f32, v32f64,
|
||||
v16i64, v16i32, v16f32, v16f64,
|
||||
v8i64, v8i32, v8f32, v8f64,
|
||||
v4i64, v4i32, v4f32, v4f64,
|
||||
v2i64, v2i32, v2f32, v2f64], 64,
|
||||
(add (sequence "V%u", 0, 63),
|
||||
VIX)>;
|
||||
|
||||
// vm0 is reserved for always true
|
||||
def VM : RegisterClass<"VE", [v256i1], 64, (sequence "VM%u", 0, 15)>;
|
||||
def VM512 : RegisterClass<"VE", [v512i1], 64, (sequence "VMP%u", 0, 7)>;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,68 @@
|
|||
# RUN: llvm-mc -triple=ve --show-encoding < %s \
|
||||
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
|
||||
# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
|
||||
# RUN: | FileCheck %s --check-prefixes=CHECK-INST
|
||||
|
||||
# CHECK-INST: vld %v11, 23, %s12
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x0b,0x8c,0x17,0x40,0x81]
|
||||
vld %v11, 23, %s12
|
||||
|
||||
# CHECK-INST: vld.nc %vix, 63, %s22
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0xff,0x96,0x3f,0x00,0x81]
|
||||
vld.nc %vix, 63, %s22
|
||||
|
||||
# CHECK-INST: vldu %v63, -64, %s63
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x3f,0xbf,0x40,0x40,0x82]
|
||||
vldu %v63, -64, %s63
|
||||
|
||||
# CHECK-INST: vldu.nc %v12, %s12, 0
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x0c,0x00,0x8c,0x00,0x82]
|
||||
vldu.nc %v12, %s12, 0
|
||||
|
||||
# CHECK-INST: vldl.sx %v11, 23, %s12
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x0b,0x8c,0x17,0x40,0x83]
|
||||
vldl.sx %v11, 23, %s12
|
||||
|
||||
# CHECK-INST: vldl.sx.nc %vix, 63, %s22
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0xff,0x96,0x3f,0x00,0x83]
|
||||
vldl.sx.nc %vix, 63, %s22
|
||||
|
||||
# CHECK-INST: vldl.zx %v63, -64, 0
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x3f,0x00,0x40,0xc0,0x83]
|
||||
vldl.zx %v63, -64, 0
|
||||
|
||||
# CHECK-INST: vldl.zx.nc %v12, %s12, %s63
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x0c,0xbf,0x8c,0x80,0x83]
|
||||
vldl.zx.nc %v12, %s12, %s63
|
||||
|
||||
# CHECK-INST: vld2d %v11, 23, %s12
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x0b,0x8c,0x17,0x40,0xc1]
|
||||
vld2d %v11, 23, %s12
|
||||
|
||||
# CHECK-INST: vld2d.nc %vix, 63, %s22
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0xff,0x96,0x3f,0x00,0xc1]
|
||||
vld2d.nc %vix, 63, %s22
|
||||
|
||||
# CHECK-INST: vldu2d %v63, -64, %s63
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x3f,0xbf,0x40,0x40,0xc2]
|
||||
vldu2d %v63, -64, %s63
|
||||
|
||||
# CHECK-INST: vldu2d.nc %v12, %s12, 0
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x0c,0x00,0x8c,0x00,0xc2]
|
||||
vldu2d.nc %v12, %s12, 0
|
||||
|
||||
# CHECK-INST: vldl2d.sx %v11, 23, %s12
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x0b,0x8c,0x17,0x40,0xc3]
|
||||
vldl2d.sx %v11, 23, %s12
|
||||
|
||||
# CHECK-INST: vldl2d.sx.nc %vix, 63, %s22
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0xff,0x96,0x3f,0x00,0xc3]
|
||||
vldl2d.sx.nc %vix, 63, %s22
|
||||
|
||||
# CHECK-INST: vldl2d.zx %v63, -64, 0
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x3f,0x00,0x40,0xc0,0xc3]
|
||||
vldl2d.zx %v63, -64, 0
|
||||
|
||||
# CHECK-INST: vldl2d.zx.nc %v12, %s12, %s63
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x0c,0xbf,0x8c,0x80,0xc3]
|
||||
vldl2d.zx.nc %v12, %s12, %s63
|
||||
|
|
@ -0,0 +1,196 @@
|
|||
# RUN: llvm-mc -triple=ve --show-encoding < %s \
|
||||
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
|
||||
# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
|
||||
# RUN: | FileCheck %s --check-prefixes=CHECK-INST
|
||||
|
||||
# CHECK-INST: vst %v11, 23, %s12
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x0b,0x8c,0x17,0x40,0x91]
|
||||
vst %v11, 23, %s12
|
||||
|
||||
# CHECK-INST: vst.nc %vix, 63, %s22
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0xff,0x96,0x3f,0x00,0x91]
|
||||
vst.nc %vix, 63, %s22
|
||||
|
||||
# CHECK-INST: vst.ot %v63, -64, %s63
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x3f,0xbf,0x40,0xc0,0x91]
|
||||
vst.ot %v63, -64, %s63
|
||||
|
||||
# CHECK-INST: vst.nc.ot %v12, %s12, 0
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x0c,0x00,0x8c,0x80,0x91]
|
||||
vst.nc.ot %v12, %s12, 0
|
||||
|
||||
# CHECK-INST: vst %v11, 23, %s12
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x0b,0x8c,0x17,0x40,0x91]
|
||||
vst %v11, 23, %s12, %vm0
|
||||
|
||||
# CHECK-INST: vst.nc %vix, 63, %s22, %vm1
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0xff,0x96,0x3f,0x01,0x91]
|
||||
vst.nc %vix, 63, %s22, %vm1
|
||||
|
||||
# CHECK-INST: vst.ot %v63, -64, %s63, %vm15
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x3f,0xbf,0x40,0xcf,0x91]
|
||||
vst.ot %v63, -64, %s63, %vm15
|
||||
|
||||
# CHECK-INST: vst.nc.ot %v12, %s12, 0, %vm8
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x0c,0x00,0x8c,0x88,0x91]
|
||||
vst.nc.ot %v12, %s12, 0, %vm8
|
||||
|
||||
# CHECK-INST: vstu %v11, 23, %s12
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x0b,0x8c,0x17,0x40,0x92]
|
||||
vstu %v11, 23, %s12
|
||||
|
||||
# CHECK-INST: vstu.nc %vix, 63, %s22
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0xff,0x96,0x3f,0x00,0x92]
|
||||
vstu.nc %vix, 63, %s22
|
||||
|
||||
# CHECK-INST: vstu.ot %v63, -64, %s63
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x3f,0xbf,0x40,0xc0,0x92]
|
||||
vstu.ot %v63, -64, %s63
|
||||
|
||||
# CHECK-INST: vstu.nc.ot %v12, %s12, 0
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x0c,0x00,0x8c,0x80,0x92]
|
||||
vstu.nc.ot %v12, %s12, 0
|
||||
|
||||
# CHECK-INST: vstu %v11, 23, %s12
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x0b,0x8c,0x17,0x40,0x92]
|
||||
vstu %v11, 23, %s12, %vm0
|
||||
|
||||
# CHECK-INST: vstu.nc %vix, 63, %s22, %vm1
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0xff,0x96,0x3f,0x01,0x92]
|
||||
vstu.nc %vix, 63, %s22, %vm1
|
||||
|
||||
# CHECK-INST: vstu.ot %v63, -64, %s63, %vm15
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x3f,0xbf,0x40,0xcf,0x92]
|
||||
vstu.ot %v63, -64, %s63, %vm15
|
||||
|
||||
# CHECK-INST: vstu.nc.ot %v12, %s12, 0, %vm8
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x0c,0x00,0x8c,0x88,0x92]
|
||||
vstu.nc.ot %v12, %s12, 0, %vm8
|
||||
|
||||
# CHECK-INST: vstl %v11, 23, %s12
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x0b,0x8c,0x17,0x40,0x93]
|
||||
vstl %v11, 23, %s12
|
||||
|
||||
# CHECK-INST: vstl.nc %vix, 63, %s22
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0xff,0x96,0x3f,0x00,0x93]
|
||||
vstl.nc %vix, 63, %s22
|
||||
|
||||
# CHECK-INST: vstl.ot %v63, -64, %s63
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x3f,0xbf,0x40,0xc0,0x93]
|
||||
vstl.ot %v63, -64, %s63
|
||||
|
||||
# CHECK-INST: vstl.nc.ot %v12, %s12, 0
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x0c,0x00,0x8c,0x80,0x93]
|
||||
vstl.nc.ot %v12, %s12, 0
|
||||
|
||||
# CHECK-INST: vstl %v11, 23, %s12
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x0b,0x8c,0x17,0x40,0x93]
|
||||
vstl %v11, 23, %s12, %vm0
|
||||
|
||||
# CHECK-INST: vstl.nc %vix, 63, %s22, %vm1
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0xff,0x96,0x3f,0x01,0x93]
|
||||
vstl.nc %vix, 63, %s22, %vm1
|
||||
|
||||
# CHECK-INST: vstl.ot %v63, -64, %s63, %vm15
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x3f,0xbf,0x40,0xcf,0x93]
|
||||
vstl.ot %v63, -64, %s63, %vm15
|
||||
|
||||
# CHECK-INST: vstl.nc.ot %v12, %s12, 0, %vm8
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x0c,0x00,0x8c,0x88,0x93]
|
||||
vstl.nc.ot %v12, %s12, 0, %vm8
|
||||
|
||||
# CHECK-INST: vst2d %v11, 23, %s12
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x0b,0x8c,0x17,0x40,0xd1]
|
||||
vst2d %v11, 23, %s12
|
||||
|
||||
# CHECK-INST: vst2d.nc %vix, 63, %s22
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0xff,0x96,0x3f,0x00,0xd1]
|
||||
vst2d.nc %vix, 63, %s22
|
||||
|
||||
# CHECK-INST: vst2d.ot %v63, -64, %s63
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x3f,0xbf,0x40,0xc0,0xd1]
|
||||
vst2d.ot %v63, -64, %s63
|
||||
|
||||
# CHECK-INST: vst2d.nc.ot %v12, %s12, 0
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x0c,0x00,0x8c,0x80,0xd1]
|
||||
vst2d.nc.ot %v12, %s12, 0
|
||||
|
||||
# CHECK-INST: vst2d %v11, 23, %s12
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x0b,0x8c,0x17,0x40,0xd1]
|
||||
vst2d %v11, 23, %s12, %vm0
|
||||
|
||||
# CHECK-INST: vst2d.nc %vix, 63, %s22, %vm1
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0xff,0x96,0x3f,0x01,0xd1]
|
||||
vst2d.nc %vix, 63, %s22, %vm1
|
||||
|
||||
# CHECK-INST: vst2d.ot %v63, -64, %s63, %vm15
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x3f,0xbf,0x40,0xcf,0xd1]
|
||||
vst2d.ot %v63, -64, %s63, %vm15
|
||||
|
||||
# CHECK-INST: vst2d.nc.ot %v12, %s12, 0, %vm8
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x0c,0x00,0x8c,0x88,0xd1]
|
||||
vst2d.nc.ot %v12, %s12, 0, %vm8
|
||||
|
||||
# CHECK-INST: vstu2d %v11, 23, %s12
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x0b,0x8c,0x17,0x40,0xd2]
|
||||
vstu2d %v11, 23, %s12
|
||||
|
||||
# CHECK-INST: vstu2d.nc %vix, 63, %s22
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0xff,0x96,0x3f,0x00,0xd2]
|
||||
vstu2d.nc %vix, 63, %s22
|
||||
|
||||
# CHECK-INST: vstu2d.ot %v63, -64, %s63
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x3f,0xbf,0x40,0xc0,0xd2]
|
||||
vstu2d.ot %v63, -64, %s63
|
||||
|
||||
# CHECK-INST: vstu2d.nc.ot %v12, %s12, 0
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x0c,0x00,0x8c,0x80,0xd2]
|
||||
vstu2d.nc.ot %v12, %s12, 0
|
||||
|
||||
# CHECK-INST: vstu2d %v11, 23, %s12
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x0b,0x8c,0x17,0x40,0xd2]
|
||||
vstu2d %v11, 23, %s12, %vm0
|
||||
|
||||
# CHECK-INST: vstu2d.nc %vix, 63, %s22, %vm1
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0xff,0x96,0x3f,0x01,0xd2]
|
||||
vstu2d.nc %vix, 63, %s22, %vm1
|
||||
|
||||
# CHECK-INST: vstu2d.ot %v63, -64, %s63, %vm15
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x3f,0xbf,0x40,0xcf,0xd2]
|
||||
vstu2d.ot %v63, -64, %s63, %vm15
|
||||
|
||||
# CHECK-INST: vstu2d.nc.ot %v12, %s12, 0, %vm8
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x0c,0x00,0x8c,0x88,0xd2]
|
||||
vstu2d.nc.ot %v12, %s12, 0, %vm8
|
||||
|
||||
# CHECK-INST: vstl2d %v11, 23, %s12
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x0b,0x8c,0x17,0x40,0xd3]
|
||||
vstl2d %v11, 23, %s12
|
||||
|
||||
# CHECK-INST: vstl2d.nc %vix, 63, %s22
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0xff,0x96,0x3f,0x00,0xd3]
|
||||
vstl2d.nc %vix, 63, %s22
|
||||
|
||||
# CHECK-INST: vstl2d.ot %v63, -64, %s63
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x3f,0xbf,0x40,0xc0,0xd3]
|
||||
vstl2d.ot %v63, -64, %s63
|
||||
|
||||
# CHECK-INST: vstl2d.nc.ot %v12, %s12, 0
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x0c,0x00,0x8c,0x80,0xd3]
|
||||
vstl2d.nc.ot %v12, %s12, 0
|
||||
|
||||
# CHECK-INST: vstl2d %v11, 23, %s12
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x0b,0x8c,0x17,0x40,0xd3]
|
||||
vstl2d %v11, 23, %s12, %vm0
|
||||
|
||||
# CHECK-INST: vstl2d.nc %vix, 63, %s22, %vm1
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0xff,0x96,0x3f,0x01,0xd3]
|
||||
vstl2d.nc %vix, 63, %s22, %vm1
|
||||
|
||||
# CHECK-INST: vstl2d.ot %v63, -64, %s63, %vm15
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x3f,0xbf,0x40,0xcf,0xd3]
|
||||
vstl2d.ot %v63, -64, %s63, %vm15
|
||||
|
||||
# CHECK-INST: vstl2d.nc.ot %v12, %s12, 0, %vm8
|
||||
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x0c,0x00,0x8c,0x88,0xd3]
|
||||
vstl2d.nc.ot %v12, %s12, 0, %vm8
|
||||
Loading…
Reference in New Issue