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[PM] Switch the TargetMachine interface from accepting a pass manager 

base which it adds a single analysis pass to, to instead return the type
erased TargetTransformInfo object constructed for that TargetMachine.

This removes all of the pass variants for TTI. There is now a single TTI
*pass* in the Analysis layer. All of the Analysis <-> Target
communication is through the TTI's type erased interface itself. While
the diff is large here, it is nothing more that code motion to make
types available in a header file for use in a different source file
within each target.

I've tried to keep all the doxygen comments and file boilerplate in line
with this move, but let me know if I missed anything.

With this in place, the next step to making TTI work with the new pass
manager is to introduce a really simple new-style analysis that produces
a TTI object via a callback into this routine on the target machine.
Once we have that, we'll have the building blocks necessary to accept
a function argument as well.

llvm-svn: 227685
This commit is contained in:
Chandler Carruth 2015-01-31 11:17:59 +00:00
parent 9559a5c05e
commit 93dcdc47db
40 changed files with 761 additions and 665 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
llvm/include/llvm/Analysis/TargetTransformInfo.h
View File

@ -61,6 +61,13 @@ public:
/// implementaion that encodes appropriate costs for their target.
template <typename T> TargetTransformInfo(T Impl);
/// \brief Construct a baseline TTI object using a minimal implementation of
/// the \c Concept API below.
///
/// The TTI implementation will reflect the information in the DataLayout
/// provided if non-null.
explicit TargetTransformInfo(const DataLayout *DL);
// Provide move semantics.
TargetTransformInfo(TargetTransformInfo &&Arg);
TargetTransformInfo &operator=(TargetTransformInfo &&RHS);
@ -723,12 +730,11 @@ public:
const TargetTransformInfo &getTTI() const { return TTI; }
};
/// \brief Create the base case instance of a pass in the TTI analysis group.
/// \brief Create an analysis pass wrapper around a TTI object.
///
/// This class provides the base case for the stack of TTI analyzes. It doesn't
/// delegate to anything and uses the STTI and VTTI objects passed in to
/// satisfy the queries.
ImmutablePass *createNoTargetTransformInfoPass(const DataLayout *DL);
/// This analysis pass just holds the TTI instance and makes it available to
/// clients.
ImmutablePass *createTargetTransformInfoWrapperPass(TargetTransformInfo TTI);
} // End llvm namespace

24
llvm/include/llvm/CodeGen/BasicTTIImpl.h
View File

@ -621,6 +621,30 @@ public:
/// @}
};
/// \brief Concrete BasicTTIImpl that can be used if no further customization
/// is needed.
class BasicTTIImpl : public BasicTTIImplBase<BasicTTIImpl> {
typedef BasicTTIImplBase<BasicTTIImpl> BaseT;
public:
explicit BasicTTIImpl(const TargetMachine *TM = nullptr);
// Provide value semantics. MSVC requires that we spell all of these out.
BasicTTIImpl(const BasicTTIImpl &Arg)
: BaseT(static_cast<const BaseT &>(Arg)) {}
BasicTTIImpl(BasicTTIImpl &&Arg)
: BaseT(std::move(static_cast<BaseT &>(Arg))) {}
BasicTTIImpl &operator=(const BasicTTIImpl &RHS) {
BaseT::operator=(static_cast<const BaseT &>(RHS));
return *this;
}
BasicTTIImpl &operator=(BasicTTIImpl &&RHS) {
BaseT::operator=(std::move(static_cast<BaseT &>(RHS)));
return *this;
}
};
}
#endif

17
llvm/include/llvm/Target/TargetMachine.h
View File

@ -40,6 +40,7 @@ class TargetPassConfig;
class TargetRegisterInfo;
class TargetSelectionDAGInfo;
class TargetSubtargetInfo;
class TargetTransformInfo;
class formatted_raw_ostream;
class raw_ostream;
class TargetLoweringObjectFile;
@ -186,8 +187,12 @@ public:
/// sections.
void setFunctionSections(bool);
/// \brief Register analysis passes for this target with a pass manager.
virtual void addAnalysisPasses(PassManagerBase &);
/// \brief Get a TTI implementation for the target.
///
/// Targets should override this method to provide target-accurate
/// information to the mid-level optimizer. If left with the baseline only
/// a very conservative set of heuristics will be used.
virtual TargetTransformInfo getTTI();
/// CodeGenFileType - These enums are meant to be passed into
/// addPassesToEmitFile to indicate what type of file to emit, and returned by
@ -240,10 +245,12 @@ protected: // Can only create subclasses.
void initAsmInfo();
public:
/// \brief Register analysis passes for this target with a pass manager.
/// \brief Get a TTI implementation for the target.
///
/// This registers target independent analysis passes.
void addAnalysisPasses(PassManagerBase &PM) override;
/// This uses the common code generator to produce a TTI implementation.
/// Targets may override it to provide more customized TTI implementation
/// instead.
TargetTransformInfo getTTI() override;
/// createPassConfig - Create a pass configuration object to be used by
/// addPassToEmitX methods for generating a pipeline of CodeGen passes.

30
llvm/lib/Analysis/TargetTransformInfo.cpp
View File

@ -21,6 +21,20 @@ using namespace llvm;
#define DEBUG_TYPE "tti"
namespace {
/// \brief No-op implementation of the TTI interface using the utility base
/// classes.
///
/// This is used when no target specific information is available.
struct NoTTIImpl : TargetTransformInfoImplCRTPBase<NoTTIImpl> {
explicit NoTTIImpl(const DataLayout *DL)
: TargetTransformInfoImplCRTPBase<NoTTIImpl>(DL) {}
};
}
TargetTransformInfo::TargetTransformInfo(const DataLayout *DL)
: TTIImpl(new Model<NoTTIImpl>(NoTTIImpl(DL))) {}
TargetTransformInfo::~TargetTransformInfo() {}
TargetTransformInfo::TargetTransformInfo(TargetTransformInfo &&Arg)
@ -241,17 +255,6 @@ Value *TargetTransformInfo::getOrCreateResultFromMemIntrinsic(
TargetTransformInfo::Concept::~Concept() {}
namespace {
/// \brief No-op implementation of the TTI interface using the utility base
/// classes.
///
/// This is used when no target specific information is available.
struct NoTTIImpl : TargetTransformInfoImplCRTPBase<NoTTIImpl> {
explicit NoTTIImpl(const DataLayout *DL)
: TargetTransformInfoImplCRTPBase<NoTTIImpl>(DL) {}
};
}
// Register the basic pass.
INITIALIZE_PASS(TargetTransformInfoWrapperPass, "tti",
"Target Transform Information", false, true)
@ -272,6 +275,7 @@ TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass(
*PassRegistry::getPassRegistry());
}
ImmutablePass *llvm::createNoTargetTransformInfoPass(const DataLayout *DL) {
return new TargetTransformInfoWrapperPass(NoTTIImpl(DL));
ImmutablePass *
llvm::createTargetTransformInfoWrapperPass(TargetTransformInfo TTI) {
return new TargetTransformInfoWrapperPass(std::move(TTI));
}

42
llvm/lib/CodeGen/BasicTargetTransformInfo.cpp
View File

@ -24,45 +24,13 @@
#include <utility>
using namespace llvm;
#define DEBUG_TYPE "basictti"
// This flag is used by the template base class for BasicTTIImpl, and here to
// provide a definition.
cl::opt<unsigned>
llvm::PartialUnrollingThreshold("partial-unrolling-threshold", cl::init(0),
cl::desc("Threshold for partial unrolling"),
cl::Hidden);
#define DEBUG_TYPE "basictti"
namespace {
class BasicTTIImpl : public BasicTTIImplBase<BasicTTIImpl> {
typedef BasicTTIImplBase<BasicTTIImpl> BaseT;
public:
explicit BasicTTIImpl(const TargetMachine *TM = nullptr) : BaseT(TM) {}
// Provide value semantics. MSVC requires that we spell all of these out.
BasicTTIImpl(const BasicTTIImpl &Arg)
: BaseT(static_cast<const BaseT &>(Arg)) {}
BasicTTIImpl(BasicTTIImpl &&Arg)
: BaseT(std::move(static_cast<BaseT &>(Arg))) {}
BasicTTIImpl &operator=(const BasicTTIImpl &RHS) {
BaseT::operator=(static_cast<const BaseT &>(RHS));
return *this;
}
BasicTTIImpl &operator=(BasicTTIImpl &&RHS) {
BaseT::operator=(std::move(static_cast<BaseT &>(RHS)));
return *this;
}
};
}
ImmutablePass *
llvm::createBasicTargetTransformInfoPass(const TargetMachine *TM) {
return new TargetTransformInfoWrapperPass(BasicTTIImpl(TM));
}
//===----------------------------------------------------------------------===//
//
// Calls used by the vectorizers.
//
//===----------------------------------------------------------------------===//
BasicTTIImpl::BasicTTIImpl(const TargetMachine *TM) : BaseT(TM) {}

7
llvm/lib/CodeGen/LLVMTargetMachine.cpp
View File

@ -15,6 +15,7 @@
#include "llvm/Analysis/JumpInstrTableInfo.h"
#include "llvm/Analysis/Passes.h"
#include "llvm/CodeGen/AsmPrinter.h"
#include "llvm/CodeGen/BasicTTIImpl.h"
#include "llvm/CodeGen/ForwardControlFlowIntegrity.h"
#include "llvm/CodeGen/JumpInstrTables.h"
#include "llvm/CodeGen/MachineFunctionAnalysis.h"
@ -77,8 +78,8 @@ LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple,
CodeGenInfo = T.createMCCodeGenInfo(Triple, RM, CM, OL);
}
void LLVMTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
PM.add(createBasicTargetTransformInfoPass(this));
TargetTransformInfo LLVMTargetMachine::getTTI() {
return TargetTransformInfo(BasicTTIImpl(this));
}
/// addPassesToX helper drives creation and initialization of TargetPassConfig.
@ -89,7 +90,7 @@ static MCContext *addPassesToGenerateCode(LLVMTargetMachine *TM,
AnalysisID StopAfter) {
// Add internal analysis passes from the target machine.
TM->addAnalysisPasses(PM);
PM.add(createTargetTransformInfoWrapperPass(TM->getTTI()));
// Targets may override createPassConfig to provide a target-specific
// subclass.

3
llvm/lib/LTO/LTOCodeGenerator.cpp
View File

@ -16,6 +16,7 @@
#include "llvm/ADT/StringExtras.h"
#include "llvm/Analysis/Passes.h"
#include "llvm/Analysis/TargetLibraryInfo.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/Bitcode/ReaderWriter.h"
#include "llvm/CodeGen/RuntimeLibcalls.h"
#include "llvm/Config/config.h"
@ -489,7 +490,7 @@ bool LTOCodeGenerator::generateObjectFile(raw_ostream &out,
mergedModule->setDataLayout(TargetMach->getDataLayout());
passes.add(new DataLayoutPass());
TargetMach->addAnalysisPasses(passes);
passes.add(createTargetTransformInfoWrapperPass(TargetMach->getTTI()));
Triple TargetTriple(TargetMach->getTargetTriple());
PassManagerBuilder PMB;

5
llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
View File

@ -13,6 +13,7 @@
#include "AArch64.h"
#include "AArch64TargetMachine.h"
#include "AArch64TargetObjectFile.h"
#include "AArch64TargetTransformInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/IR/Function.h"
@ -195,8 +196,8 @@ public:
};
} // namespace
void AArch64TargetMachine::addAnalysisPasses(PassManagerBase &PM) {
PM.add(createAArch64TargetTransformInfoPass(this));
TargetTransformInfo AArch64TargetMachine::getTTI() {
return TargetTransformInfo(AArch64TTIImpl(this));
}
TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {

2
llvm/lib/Target/AArch64/AArch64TargetMachine.h
View File

@ -46,7 +46,7 @@ public:
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
/// \brief Register AArch64 analysis passes with a pass manager.
void addAnalysisPasses(PassManagerBase &PM) override;
TargetTransformInfo getTTI() override;
TargetLoweringObjectFile* getObjFileLowering() const override {
return TLOF.get();

130
llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
View File

@ -1,4 +1,4 @@
//===-- AArch64TargetTransformInfo.cpp - AArch64 specific TTI pass --------===//
//===-- AArch64TargetTransformInfo.cpp - AArch64 specific TTI -------------===//
//
// The LLVM Compiler Infrastructure
//
@ -6,16 +6,8 @@
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
/// \file
/// This file implements a TargetTransformInfo analysis pass specific to the
/// AArch64 target machine. It uses the target's detailed information to provide
/// more precise answers to certain TTI queries, while letting the target
/// independent and default TTI implementations handle the rest.
///
//===----------------------------------------------------------------------===//
#include "AArch64.h"
#include "AArch64TargetMachine.h"
#include "AArch64TargetTransformInfo.h"
#include "MCTargetDesc/AArch64AddressingModes.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/BasicTTIImpl.h"
@ -27,124 +19,6 @@ using namespace llvm;
#define DEBUG_TYPE "aarch64tti"
namespace {
class AArch64TTIImpl : public BasicTTIImplBase<AArch64TTIImpl> {
typedef BasicTTIImplBase<AArch64TTIImpl> BaseT;
typedef TargetTransformInfo TTI;
const AArch64Subtarget *ST;
const AArch64TargetLowering *TLI;
/// Estimate the overhead of scalarizing an instruction. Insert and Extract
/// are set if the result needs to be inserted and/or extracted from vectors.
unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract);
enum MemIntrinsicType {
VECTOR_LDST_TWO_ELEMENTS,
VECTOR_LDST_THREE_ELEMENTS,
VECTOR_LDST_FOUR_ELEMENTS
};
public:
explicit AArch64TTIImpl(const AArch64TargetMachine *TM = nullptr)
: BaseT(TM), ST(TM ? TM->getSubtargetImpl() : nullptr),
TLI(ST ? ST->getTargetLowering() : nullptr) {}
// Provide value semantics. MSVC requires that we spell all of these out.
AArch64TTIImpl(const AArch64TTIImpl &Arg)
: BaseT(static_cast<const BaseT &>(Arg)), ST(Arg.ST), TLI(Arg.TLI) {}
AArch64TTIImpl(AArch64TTIImpl &&Arg)
: BaseT(std::move(static_cast<BaseT &>(Arg))), ST(std::move(Arg.ST)),
TLI(std::move(Arg.TLI)) {}
AArch64TTIImpl &operator=(const AArch64TTIImpl &RHS) {
BaseT::operator=(static_cast<const BaseT &>(RHS));
ST = RHS.ST;
TLI = RHS.TLI;
return *this;
}
AArch64TTIImpl &operator=(AArch64TTIImpl &&RHS) {
BaseT::operator=(std::move(static_cast<BaseT &>(RHS)));
ST = std::move(RHS.ST);
TLI = std::move(RHS.TLI);
return *this;
}
/// \name Scalar TTI Implementations
/// @{
using BaseT::getIntImmCost;
unsigned getIntImmCost(int64_t Val);
unsigned getIntImmCost(const APInt &Imm, Type *Ty);
unsigned getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
Type *Ty);
unsigned getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
Type *Ty);
TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth);
/// @}
/// \name Vector TTI Implementations
/// @{
unsigned getNumberOfRegisters(bool Vector) {
if (Vector) {
if (ST->hasNEON())
return 32;
return 0;
}
return 31;
}
unsigned getRegisterBitWidth(bool Vector) {
if (Vector) {
if (ST->hasNEON())
return 128;
return 0;
}
return 64;
}
unsigned getMaxInterleaveFactor();
unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src);
unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index);
unsigned getArithmeticInstrCost(
unsigned Opcode, Type *Ty,
TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue,
TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,
TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None);
unsigned getAddressComputationCost(Type *Ty, bool IsComplex);
unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy);
unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
unsigned AddressSpace);
unsigned getCostOfKeepingLiveOverCall(ArrayRef<Type *> Tys);
void getUnrollingPreferences(const Function *F, Loop *L,
TTI::UnrollingPreferences &UP);
Value *getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst,
Type *ExpectedType);
bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info);
/// @}
};
} // end anonymous namespace
ImmutablePass *
llvm::createAArch64TargetTransformInfoPass(const AArch64TargetMachine *TM) {
return new TargetTransformInfoWrapperPass(AArch64TTIImpl(TM));
}
/// \brief Calculate the cost of materializing a 64-bit value. This helper
/// method might only calculate a fraction of a larger immediate. Therefore it
/// is valid to return a cost of ZERO.

140
llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h Normal file
View File

@ -0,0 +1,140 @@
//===-- AArch64TargetTransformInfo.h - AArch64 specific TTI -----*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
/// \file
/// This file a TargetTransformInfo::Concept conforming object specific to the
/// AArch64 target machine. It uses the target's detailed information to
/// provide more precise answers to certain TTI queries, while letting the
/// target independent and default TTI implementations handle the rest.
///
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H
#define LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H
#include "AArch64.h"
#include "AArch64TargetMachine.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/BasicTTIImpl.h"
#include "llvm/Target/TargetLowering.h"
#include <algorithm>
namespace llvm {
class AArch64TTIImpl : public BasicTTIImplBase<AArch64TTIImpl> {
typedef BasicTTIImplBase<AArch64TTIImpl> BaseT;
typedef TargetTransformInfo TTI;
const AArch64Subtarget *ST;
const AArch64TargetLowering *TLI;
/// Estimate the overhead of scalarizing an instruction. Insert and Extract
/// are set if the result needs to be inserted and/or extracted from vectors.
unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract);
enum MemIntrinsicType {
VECTOR_LDST_TWO_ELEMENTS,
VECTOR_LDST_THREE_ELEMENTS,
VECTOR_LDST_FOUR_ELEMENTS
};
public:
explicit AArch64TTIImpl(const AArch64TargetMachine *TM = nullptr)
: BaseT(TM), ST(TM ? TM->getSubtargetImpl() : nullptr),
TLI(ST ? ST->getTargetLowering() : nullptr) {}
// Provide value semantics. MSVC requires that we spell all of these out.
AArch64TTIImpl(const AArch64TTIImpl &Arg)
: BaseT(static_cast<const BaseT &>(Arg)), ST(Arg.ST), TLI(Arg.TLI) {}
AArch64TTIImpl(AArch64TTIImpl &&Arg)
: BaseT(std::move(static_cast<BaseT &>(Arg))), ST(std::move(Arg.ST)),
TLI(std::move(Arg.TLI)) {}
AArch64TTIImpl &operator=(const AArch64TTIImpl &RHS) {
BaseT::operator=(static_cast<const BaseT &>(RHS));
ST = RHS.ST;
TLI = RHS.TLI;
return *this;
}
AArch64TTIImpl &operator=(AArch64TTIImpl &&RHS) {
BaseT::operator=(std::move(static_cast<BaseT &>(RHS)));
ST = std::move(RHS.ST);
TLI = std::move(RHS.TLI);
return *this;
}
/// \name Scalar TTI Implementations
/// @{
using BaseT::getIntImmCost;
unsigned getIntImmCost(int64_t Val);
unsigned getIntImmCost(const APInt &Imm, Type *Ty);
unsigned getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
Type *Ty);
unsigned getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
Type *Ty);
TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth);
/// @}
/// \name Vector TTI Implementations
/// @{
unsigned getNumberOfRegisters(bool Vector) {
if (Vector) {
if (ST->hasNEON())
return 32;
return 0;
}
return 31;
}
unsigned getRegisterBitWidth(bool Vector) {
if (Vector) {
if (ST->hasNEON())
return 128;
return 0;
}
return 64;
}
unsigned getMaxInterleaveFactor();
unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src);
unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index);
unsigned getArithmeticInstrCost(
unsigned Opcode, Type *Ty,
TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue,
TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,
TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None);
unsigned getAddressComputationCost(Type *Ty, bool IsComplex);
unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy);
unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
unsigned AddressSpace);
unsigned getCostOfKeepingLiveOverCall(ArrayRef<Type *> Tys);
void getUnrollingPreferences(const Function *F, Loop *L,
TTI::UnrollingPreferences &UP);
Value *getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst,
Type *ExpectedType);
bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info);
/// @}
};
} // end namespace llvm
#endif

5
llvm/lib/Target/ARM/ARMTargetMachine.cpp
View File

@ -14,6 +14,7 @@
#include "ARMFrameLowering.h"
#include "ARMTargetMachine.h"
#include "ARMTargetObjectFile.h"
#include "ARMTargetTransformInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/IR/Function.h"
#include "llvm/MC/MCAsmInfo.h"
@ -215,8 +216,8 @@ ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const {
return I.get();
}
void ARMBaseTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
PM.add(createARMTargetTransformInfoPass(this));
TargetTransformInfo ARMBaseTargetMachine::getTTI() {
return TargetTransformInfo(ARMTTIImpl(this));
}

2
llvm/lib/Target/ARM/ARMTargetMachine.h
View File

@ -50,7 +50,7 @@ public:
const DataLayout *getDataLayout() const override { return &DL; }
/// \brief Register ARM analysis passes with a pass manager.
void addAnalysisPasses(PassManagerBase &PM) override;
TargetTransformInfo getTTI() override;
// Pass Pipeline Configuration
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;

123
llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
View File

@ -1,4 +1,4 @@
//===-- ARMTargetTransformInfo.cpp - ARM specific TTI pass ----------------===//
//===-- ARMTargetTransformInfo.cpp - ARM specific TTI ---------------------===//
//
// The LLVM Compiler Infrastructure
//
@ -6,18 +6,8 @@
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
/// \file
/// This file implements a TargetTransformInfo analysis pass specific to the
/// ARM target machine. It uses the target's detailed information to provide
/// more precise answers to certain TTI queries, while letting the target
/// independent and default TTI implementations handle the rest.
///
//===----------------------------------------------------------------------===//
#include "ARM.h"
#include "ARMTargetMachine.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/BasicTTIImpl.h"
#include "ARMTargetTransformInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Target/CostTable.h"
#include "llvm/Target/TargetLowering.h"
@ -25,115 +15,6 @@ using namespace llvm;
#define DEBUG_TYPE "armtti"
namespace {
class ARMTTIImpl : public BasicTTIImplBase<ARMTTIImpl> {
typedef BasicTTIImplBase<ARMTTIImpl> BaseT;
typedef TargetTransformInfo TTI;
const ARMSubtarget *ST;
const ARMTargetLowering *TLI;
/// Estimate the overhead of scalarizing an instruction. Insert and Extract
/// are set if the result needs to be inserted and/or extracted from vectors.
unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract);
public:
explicit ARMTTIImpl(const ARMBaseTargetMachine *TM = nullptr)
: BaseT(TM), ST(TM ? TM->getSubtargetImpl() : nullptr),
TLI(ST ? ST->getTargetLowering() : nullptr) {}
// Provide value semantics. MSVC requires that we spell all of these out.
ARMTTIImpl(const ARMTTIImpl &Arg)
: BaseT(static_cast<const BaseT &>(Arg)), ST(Arg.ST), TLI(Arg.TLI) {}
ARMTTIImpl(ARMTTIImpl &&Arg)
: BaseT(std::move(static_cast<BaseT &>(Arg))), ST(std::move(Arg.ST)),
TLI(std::move(Arg.TLI)) {}
ARMTTIImpl &operator=(const ARMTTIImpl &RHS) {
BaseT::operator=(static_cast<const BaseT &>(RHS));
ST = RHS.ST;
TLI = RHS.TLI;
return *this;
}
ARMTTIImpl &operator=(ARMTTIImpl &&RHS) {
BaseT::operator=(std::move(static_cast<BaseT &>(RHS)));
ST = std::move(RHS.ST);
TLI = std::move(RHS.TLI);
return *this;
}
/// \name Scalar TTI Implementations
/// @{
using BaseT::getIntImmCost;
unsigned getIntImmCost(const APInt &Imm, Type *Ty);
/// @}
/// \name Vector TTI Implementations
/// @{
unsigned getNumberOfRegisters(bool Vector) {
if (Vector) {
if (ST->hasNEON())
return 16;
return 0;
}
if (ST->isThumb1Only())
return 8;
return 13;
}
unsigned getRegisterBitWidth(bool Vector) {
if (Vector) {
if (ST->hasNEON())
return 128;
return 0;
}
return 32;
}
unsigned getMaxInterleaveFactor() {
// These are out of order CPUs:
if (ST->isCortexA15() || ST->isSwift())
return 2;
return 1;
}
unsigned getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index,
Type *SubTp);
unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src);
unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy);
unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index);
unsigned getAddressComputationCost(Type *Val, bool IsComplex);
unsigned getArithmeticInstrCost(
unsigned Opcode, Type *Ty,
TTI::OperandValueKind Op1Info = TTI::OK_AnyValue,
TTI::OperandValueKind Op2Info = TTI::OK_AnyValue,
TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None);
unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
unsigned AddressSpace);
/// @}
};
} // end anonymous namespace
ImmutablePass *
llvm::createARMTargetTransformInfoPass(const ARMBaseTargetMachine *TM) {
return new TargetTransformInfoWrapperPass(ARMTTIImpl(TM));
}
unsigned ARMTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) {
assert(Ty->isIntegerTy());

129
llvm/lib/Target/ARM/ARMTargetTransformInfo.h Normal file
View File

@ -0,0 +1,129 @@
//===-- ARMTargetTransformInfo.h - ARM specific TTI -------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
/// \file
/// This file a TargetTransformInfo::Concept conforming object specific to the
/// ARM target machine. It uses the target's detailed information to
/// provide more precise answers to certain TTI queries, while letting the
/// target independent and default TTI implementations handle the rest.
///
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
#define LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
#include "ARM.h"
#include "ARMTargetMachine.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/BasicTTIImpl.h"
#include "llvm/Target/TargetLowering.h"
namespace llvm {
class ARMTTIImpl : public BasicTTIImplBase<ARMTTIImpl> {
typedef BasicTTIImplBase<ARMTTIImpl> BaseT;
typedef TargetTransformInfo TTI;
const ARMSubtarget *ST;
const ARMTargetLowering *TLI;
/// Estimate the overhead of scalarizing an instruction. Insert and Extract
/// are set if the result needs to be inserted and/or extracted from vectors.
unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract);
public:
explicit ARMTTIImpl(const ARMBaseTargetMachine *TM = nullptr)
: BaseT(TM), ST(TM ? TM->getSubtargetImpl() : nullptr),
TLI(ST ? ST->getTargetLowering() : nullptr) {}
// Provide value semantics. MSVC requires that we spell all of these out.
ARMTTIImpl(const ARMTTIImpl &Arg)
: BaseT(static_cast<const BaseT &>(Arg)), ST(Arg.ST), TLI(Arg.TLI) {}
ARMTTIImpl(ARMTTIImpl &&Arg)
: BaseT(std::move(static_cast<BaseT &>(Arg))), ST(std::move(Arg.ST)),
TLI(std::move(Arg.TLI)) {}
ARMTTIImpl &operator=(const ARMTTIImpl &RHS) {
BaseT::operator=(static_cast<const BaseT &>(RHS));
ST = RHS.ST;
TLI = RHS.TLI;
return *this;
}
ARMTTIImpl &operator=(ARMTTIImpl &&RHS) {
BaseT::operator=(std::move(static_cast<BaseT &>(RHS)));
ST = std::move(RHS.ST);
TLI = std::move(RHS.TLI);
return *this;
}
/// \name Scalar TTI Implementations
/// @{
using BaseT::getIntImmCost;
unsigned getIntImmCost(const APInt &Imm, Type *Ty);
/// @}
/// \name Vector TTI Implementations
/// @{
unsigned getNumberOfRegisters(bool Vector) {
if (Vector) {
if (ST->hasNEON())
return 16;
return 0;
}
if (ST->isThumb1Only())
return 8;
return 13;
}
unsigned getRegisterBitWidth(bool Vector) {
if (Vector) {
if (ST->hasNEON())
return 128;
return 0;
}
return 32;
}
unsigned getMaxInterleaveFactor() {
// These are out of order CPUs:
if (ST->isCortexA15() || ST->isSwift())
return 2;
return 1;
}
unsigned getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index,
Type *SubTp);
unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src);
unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy);
unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index);
unsigned getAddressComputationCost(Type *Val, bool IsComplex);
unsigned getArithmeticInstrCost(
unsigned Opcode, Type *Ty,
TTI::OperandValueKind Op1Info = TTI::OK_AnyValue,
TTI::OperandValueKind Op2Info = TTI::OK_AnyValue,
TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None);
unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
unsigned AddressSpace);
/// @}
};
} // end namespace llvm
#endif

11
llvm/lib/Target/Mips/MipsTargetMachine.cpp
View File

@ -238,17 +238,18 @@ void MipsPassConfig::addPreRegAlloc() {
addPass(createMipsOptimizePICCallPass(getMipsTargetMachine()));
}
void MipsTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
TargetTransformInfo MipsTargetMachine::getTTI() {
if (Subtarget->allowMixed16_32()) {
DEBUG(errs() << "No ");
DEBUG(errs() << "No Target Transform Info Pass Added\n");
//FIXME: The Basic Target Transform Info
// pass needs to become a function pass instead of
// being an immutable pass and then this method as it exists now
// would be unnecessary.
PM.add(createNoTargetTransformInfoPass(getDataLayout()));
} else
LLVMTargetMachine::addAnalysisPasses(PM);
return TargetTransformInfo(getDataLayout());
}
DEBUG(errs() << "Target Transform Info Pass Added\n");
return LLVMTargetMachine::getTTI();
}
// Implemented by targets that want to run passes immediately before

2
llvm/lib/Target/Mips/MipsTargetMachine.h
View File

@ -44,7 +44,7 @@ public:
CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
~MipsTargetMachine() override;
void addAnalysisPasses(PassManagerBase &PM) override;
TargetTransformInfo getTTI() override;
const DataLayout *getDataLayout() const override { return &DL; }
const MipsSubtarget *getSubtargetImpl() const override {

5
llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
View File

@ -17,6 +17,7 @@
#include "NVPTXAllocaHoisting.h"
#include "NVPTXLowerAggrCopies.h"
#include "NVPTXTargetObjectFile.h"
#include "NVPTXTargetTransformInfo.h"
#include "llvm/Analysis/Passes.h"
#include "llvm/CodeGen/AsmPrinter.h"
#include "llvm/CodeGen/MachineFunctionAnalysis.h"
@ -136,8 +137,8 @@ TargetPassConfig *NVPTXTargetMachine::createPassConfig(PassManagerBase &PM) {
return PassConfig;
}
void NVPTXTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
PM.add(createNVPTXTargetTransformInfoPass(this));
TargetTransformInfo NVPTXTargetMachine::getTTI() {
return TargetTransformInfo(NVPTXTTIImpl(this));
}
void NVPTXPassConfig::addIRPasses() {

3
llvm/lib/Target/NVPTX/NVPTXTargetMachine.h
View File

@ -56,8 +56,7 @@ public:
return TLOF.get();
}
/// \brief Register NVPTX analysis passes with a pass manager.
void addAnalysisPasses(PassManagerBase &PM) override;
TargetTransformInfo getTTI() override;
}; // NVPTXTargetMachine.

58
llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
View File

@ -1,4 +1,4 @@
//===-- NVPTXTargetTransformInfo.cpp - NVPTX specific TTI pass ---------===//
//===-- NVPTXTargetTransformInfo.cpp - NVPTX specific TTI -----------------===//
//
// The LLVM Compiler Infrastructure
//
@ -6,16 +6,8 @@
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// \file
// This file implements a TargetTransformInfo analysis pass specific to the
// NVPTX target machine. It uses the target's detailed information to provide
// more precise answers to certain TTI queries, while letting the target
// independent and default TTI implementations handle the rest.
//
//===----------------------------------------------------------------------===//
#include "NVPTXTargetMachine.h"
#include "NVPTXTargetTransformInfo.h"
#include "llvm/Analysis/LoopInfo.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/Analysis/ValueTracking.h"
@ -27,52 +19,6 @@ using namespace llvm;
#define DEBUG_TYPE "NVPTXtti"
namespace {
class NVPTXTTIImpl : public BasicTTIImplBase<NVPTXTTIImpl> {
typedef BasicTTIImplBase<NVPTXTTIImpl> BaseT;
typedef TargetTransformInfo TTI;
const NVPTXTargetLowering *TLI;
public:
explicit NVPTXTTIImpl(const NVPTXTargetMachine *TM = nullptr)
: BaseT(TM),
TLI(TM ? TM->getSubtargetImpl()->getTargetLowering() : nullptr) {}
// Provide value semantics. MSVC requires that we spell all of these out.
NVPTXTTIImpl(const NVPTXTTIImpl &Arg)
: BaseT(static_cast<const BaseT &>(Arg)), TLI(Arg.TLI) {}
NVPTXTTIImpl(NVPTXTTIImpl &&Arg)
: BaseT(std::move(static_cast<BaseT &>(Arg))), TLI(std::move(Arg.TLI)) {}
NVPTXTTIImpl &operator=(const NVPTXTTIImpl &RHS) {
BaseT::operator=(static_cast<const BaseT &>(RHS));
TLI = RHS.TLI;
return *this;
}
NVPTXTTIImpl &operator=(NVPTXTTIImpl &&RHS) {
BaseT::operator=(std::move(static_cast<BaseT &>(RHS)));
TLI = std::move(RHS.TLI);
return *this;
}
bool hasBranchDivergence() { return true; }
unsigned getArithmeticInstrCost(
unsigned Opcode, Type *Ty,
TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue,
TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,
TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None);
};
} // end anonymous namespace
ImmutablePass *
llvm::createNVPTXTargetTransformInfoPass(const NVPTXTargetMachine *TM) {
return new TargetTransformInfoWrapperPass(NVPTXTTIImpl(TM));
}
unsigned NVPTXTTIImpl::getArithmeticInstrCost(
unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info,
TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo,

67
llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h Normal file
View File

@ -0,0 +1,67 @@
//===-- NVPTXTargetTransformInfo.h - NVPTX specific TTI ---------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
/// \file
/// This file a TargetTransformInfo::Concept conforming object specific to the
/// NVPTX target machine. It uses the target's detailed information to
/// provide more precise answers to certain TTI queries, while letting the
/// target independent and default TTI implementations handle the rest.
///
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_NVPTX_NVPTXTARGETTRANSFORMINFO_H
#define LLVM_LIB_TARGET_NVPTX_NVPTXTARGETTRANSFORMINFO_H
#include "NVPTX.h"
#include "NVPTXTargetMachine.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/BasicTTIImpl.h"
#include "llvm/Target/TargetLowering.h"
namespace llvm {
class NVPTXTTIImpl : public BasicTTIImplBase<NVPTXTTIImpl> {
typedef BasicTTIImplBase<NVPTXTTIImpl> BaseT;
typedef TargetTransformInfo TTI;
const NVPTXTargetLowering *TLI;
public:
explicit NVPTXTTIImpl(const NVPTXTargetMachine *TM = nullptr)
: BaseT(TM),
TLI(TM ? TM->getSubtargetImpl()->getTargetLowering() : nullptr) {}
// Provide value semantics. MSVC requires that we spell all of these out.
NVPTXTTIImpl(const NVPTXTTIImpl &Arg)
: BaseT(static_cast<const BaseT &>(Arg)), TLI(Arg.TLI) {}
NVPTXTTIImpl(NVPTXTTIImpl &&Arg)
: BaseT(std::move(static_cast<BaseT &>(Arg))), TLI(std::move(Arg.TLI)) {}
NVPTXTTIImpl &operator=(const NVPTXTTIImpl &RHS) {
BaseT::operator=(static_cast<const BaseT &>(RHS));
TLI = RHS.TLI;
return *this;
}
NVPTXTTIImpl &operator=(NVPTXTTIImpl &&RHS) {
BaseT::operator=(std::move(static_cast<BaseT &>(RHS)));
TLI = std::move(RHS.TLI);
return *this;
}
bool hasBranchDivergence() { return true; }
unsigned getArithmeticInstrCost(
unsigned Opcode, Type *Ty,
TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue,
TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,
TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None);
};
} // end namespace llvm
#endif

5
llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
View File

@ -14,6 +14,7 @@
#include "PPCTargetMachine.h"
#include "PPC.h"
#include "PPCTargetObjectFile.h"
#include "PPCTargetTransformInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/IR/Function.h"
#include "llvm/MC/MCStreamer.h"
@ -274,6 +275,6 @@ void PPCPassConfig::addPreEmitPass() {
addPass(createPPCBranchSelectionPass(), false);
}
void PPCTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
PM.add(createPPCTargetTransformInfoPass(this));
TargetTransformInfo PPCTargetMachine::getTTI() {
return TargetTransformInfo(PPCTTIImpl(this));
}

4
llvm/lib/Target/PowerPC/PPCTargetMachine.h
View File

@ -45,8 +45,8 @@ public:
// Pass Pipeline Configuration
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
/// \brief Register PPC analysis passes with a pass manager.
void addAnalysisPasses(PassManagerBase &PM) override;
TargetTransformInfo getTTI() override;
TargetLoweringObjectFile *getObjFileLowering() const override {
return TLOF.get();
}

92
llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
View File

@ -1,4 +1,4 @@
//===-- PPCTargetTransformInfo.cpp - PPC specific TTI pass ----------------===//
//===-- PPCTargetTransformInfo.cpp - PPC specific TTI ---------------------===//
//
// The LLVM Compiler Infrastructure
//
@ -6,16 +6,8 @@
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
/// \file
/// This file implements a TargetTransformInfo analysis pass specific to the
/// PPC target machine. It uses the target's detailed information to provide
/// more precise answers to certain TTI queries, while letting the target
/// independent and default TTI implementations handle the rest.
///
//===----------------------------------------------------------------------===//
#include "PPC.h"
#include "PPCTargetMachine.h"
#include "PPCTargetTransformInfo.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/BasicTTIImpl.h"
#include "llvm/Support/CommandLine.h"
@ -29,86 +21,6 @@ using namespace llvm;
static cl::opt<bool> DisablePPCConstHoist("disable-ppc-constant-hoisting",
cl::desc("disable constant hoisting on PPC"), cl::init(false), cl::Hidden);
namespace {
class PPCTTIImpl : public BasicTTIImplBase<PPCTTIImpl> {
typedef BasicTTIImplBase<PPCTTIImpl> BaseT;
typedef TargetTransformInfo TTI;
const PPCSubtarget *ST;
const PPCTargetLowering *TLI;
public:
explicit PPCTTIImpl(const PPCTargetMachine *TM = nullptr)
: BaseT(TM), ST(TM->getSubtargetImpl()), TLI(ST->getTargetLowering()) {}
// Provide value semantics. MSVC requires that we spell all of these out.
PPCTTIImpl(const PPCTTIImpl &Arg)
: BaseT(static_cast<const BaseT &>(Arg)), ST(Arg.ST), TLI(Arg.TLI) {}
PPCTTIImpl(PPCTTIImpl &&Arg)
: BaseT(std::move(static_cast<BaseT &>(Arg))), ST(std::move(Arg.ST)),
TLI(std::move(Arg.TLI)) {}
PPCTTIImpl &operator=(const PPCTTIImpl &RHS) {
BaseT::operator=(static_cast<const BaseT &>(RHS));
ST = RHS.ST;
TLI = RHS.TLI;
return *this;
}
PPCTTIImpl &operator=(PPCTTIImpl &&RHS) {
BaseT::operator=(std::move(static_cast<BaseT &>(RHS)));
ST = std::move(RHS.ST);
TLI = std::move(RHS.TLI);
return *this;
}
/// \name Scalar TTI Implementations
/// @{
using BaseT::getIntImmCost;
unsigned getIntImmCost(const APInt &Imm, Type *Ty);
unsigned getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
Type *Ty);
unsigned getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
Type *Ty);
TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth);
void getUnrollingPreferences(const Function *F, Loop *L,
TTI::UnrollingPreferences &UP);
/// @}
/// \name Vector TTI Implementations
/// @{
unsigned getNumberOfRegisters(bool Vector);
unsigned getRegisterBitWidth(bool Vector);
unsigned getMaxInterleaveFactor();
unsigned getArithmeticInstrCost(
unsigned Opcode, Type *Ty,
TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue,
TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,
TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None);
unsigned getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index,
Type *SubTp);
unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src);
unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy);
unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index);
unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
unsigned AddressSpace);
/// @}
};
} // end anonymous namespace
ImmutablePass *
llvm::createPPCTargetTransformInfoPass(const PPCTargetMachine *TM) {
return new TargetTransformInfoWrapperPass(PPCTTIImpl(TM));
}
//===----------------------------------------------------------------------===//
//
// PPC cost model.

100
llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h Normal file
View File

@ -0,0 +1,100 @@
//===-- PPCTargetTransformInfo.h - PPC specific TTI -------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
/// \file
/// This file a TargetTransformInfo::Concept conforming object specific to the
/// PPC target machine. It uses the target's detailed information to
/// provide more precise answers to certain TTI queries, while letting the
/// target independent and default TTI implementations handle the rest.
///
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_POWERPC_PPCTARGETTRANSFORMINFO_H
#define LLVM_LIB_TARGET_POWERPC_PPCTARGETTRANSFORMINFO_H
#include "PPC.h"
#include "PPCTargetMachine.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/BasicTTIImpl.h"
#include "llvm/Target/TargetLowering.h"
namespace llvm {
class PPCTTIImpl : public BasicTTIImplBase<PPCTTIImpl> {
typedef BasicTTIImplBase<PPCTTIImpl> BaseT;
typedef TargetTransformInfo TTI;
const PPCSubtarget *ST;
const PPCTargetLowering *TLI;
public:
explicit PPCTTIImpl(const PPCTargetMachine *TM = nullptr)
: BaseT(TM), ST(TM->getSubtargetImpl()), TLI(ST->getTargetLowering()) {}
// Provide value semantics. MSVC requires that we spell all of these out.
PPCTTIImpl(const PPCTTIImpl &Arg)
: BaseT(static_cast<const BaseT &>(Arg)), ST(Arg.ST), TLI(Arg.TLI) {}
PPCTTIImpl(PPCTTIImpl &&Arg)
: BaseT(std::move(static_cast<BaseT &>(Arg))), ST(std::move(Arg.ST)),
TLI(std::move(Arg.TLI)) {}
PPCTTIImpl &operator=(const PPCTTIImpl &RHS) {
BaseT::operator=(static_cast<const BaseT &>(RHS));
ST = RHS.ST;
TLI = RHS.TLI;
return *this;
}
PPCTTIImpl &operator=(PPCTTIImpl &&RHS) {
BaseT::operator=(std::move(static_cast<BaseT &>(RHS)));
ST = std::move(RHS.ST);
TLI = std::move(RHS.TLI);
return *this;
}
/// \name Scalar TTI Implementations
/// @{
using BaseT::getIntImmCost;
unsigned getIntImmCost(const APInt &Imm, Type *Ty);
unsigned getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
Type *Ty);
unsigned getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
Type *Ty);
TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth);
void getUnrollingPreferences(const Function *F, Loop *L,
TTI::UnrollingPreferences &UP);
/// @}
/// \name Vector TTI Implementations
/// @{
unsigned getNumberOfRegisters(bool Vector);
unsigned getRegisterBitWidth(bool Vector);
unsigned getMaxInterleaveFactor();
unsigned getArithmeticInstrCost(
unsigned Opcode, Type *Ty,
TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue,
TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,
TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None);
unsigned getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index,
Type *SubTp);
unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src);
unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy);
unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index);
unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
unsigned AddressSpace);
/// @}
};
} // end namespace llvm
#endif

7
llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
View File

@ -15,6 +15,7 @@
#include "AMDGPUTargetMachine.h"
#include "AMDGPU.h"
#include "AMDGPUTargetTransformInfo.h"
#include "R600ISelLowering.h"
#include "R600InstrInfo.h"
#include "R600MachineScheduler.h"
@ -116,11 +117,11 @@ TargetPassConfig *AMDGPUTargetMachine::createPassConfig(PassManagerBase &PM) {
}
//===----------------------------------------------------------------------===//
// AMDGPU Analysis Pass Setup
// AMDGPU Pass Setup
//===----------------------------------------------------------------------===//
void AMDGPUTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
PM.add(createAMDGPUTargetTransformInfoPass(this));
TargetTransformInfo AMDGPUTargetMachine::getTTI() {
return TargetTransformInfo(AMDGPUTTIImpl(this));
}
void AMDGPUPassConfig::addIRPasses() {

4
llvm/lib/Target/R600/AMDGPUTargetMachine.h
View File

@ -55,8 +55,8 @@ public:
}
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
/// \brief Register R600 analysis passes with a pass manager.
void addAnalysisPasses(PassManagerBase &PM) override;
TargetTransformInfo getTTI() override;
TargetLoweringObjectFile *getObjFileLowering() const override {
return TLOF;
}

53
llvm/lib/Target/R600/AMDGPUTargetTransformInfo.cpp
View File

@ -15,8 +15,7 @@
//
//===----------------------------------------------------------------------===//
#include "AMDGPU.h"
#include "AMDGPUTargetMachine.h"
#include "AMDGPUTargetTransformInfo.h"
#include "llvm/Analysis/LoopInfo.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/Analysis/ValueTracking.h"
@ -28,56 +27,6 @@ using namespace llvm;
#define DEBUG_TYPE "AMDGPUtti"
namespace {
class AMDGPUTTIImpl : public BasicTTIImplBase<AMDGPUTTIImpl> {
typedef BasicTTIImplBase<AMDGPUTTIImpl> BaseT;
typedef TargetTransformInfo TTI;
const AMDGPUSubtarget *ST;
public:
explicit AMDGPUTTIImpl(const AMDGPUTargetMachine *TM = nullptr)
: BaseT(TM), ST(TM->getSubtargetImpl()) {}
// Provide value semantics. MSVC requires that we spell all of these out.
AMDGPUTTIImpl(const AMDGPUTTIImpl &Arg)
: BaseT(static_cast<const BaseT &>(Arg)), ST(Arg.ST) {}
AMDGPUTTIImpl(AMDGPUTTIImpl &&Arg)
: BaseT(std::move(static_cast<BaseT &>(Arg))), ST(std::move(Arg.ST)) {}
AMDGPUTTIImpl &operator=(const AMDGPUTTIImpl &RHS) {
BaseT::operator=(static_cast<const BaseT &>(RHS));
ST = RHS.ST;
return *this;
}
AMDGPUTTIImpl &operator=(AMDGPUTTIImpl &&RHS) {
BaseT::operator=(std::move(static_cast<BaseT &>(RHS)));
ST = std::move(RHS.ST);
return *this;
}
bool hasBranchDivergence() { return true; }
void getUnrollingPreferences(const Function *F, Loop *L,
TTI::UnrollingPreferences &UP);
TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) {
assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
return ST->hasBCNT(TyWidth) ? TTI::PSK_FastHardware : TTI::PSK_Software;
}
unsigned getNumberOfRegisters(bool Vector);
unsigned getRegisterBitWidth(bool Vector);
unsigned getMaxInterleaveFactor();
};
} // end anonymous namespace
ImmutablePass *
llvm::createAMDGPUTargetTransformInfoPass(const AMDGPUTargetMachine *TM) {
return new TargetTransformInfoWrapperPass(AMDGPUTTIImpl(TM));
}
void AMDGPUTTIImpl::getUnrollingPreferences(const Function *, Loop *L,
TTI::UnrollingPreferences &UP) {
UP.Threshold = 300; // Twice the default.

71
llvm/lib/Target/R600/AMDGPUTargetTransformInfo.h Normal file
View File

@ -0,0 +1,71 @@
//===-- AMDGPUTargetTransformInfo.h - AMDGPU specific TTI -------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
/// \file
/// This file a TargetTransformInfo::Concept conforming object specific to the
/// AMDGPU target machine. It uses the target's detailed information to
/// provide more precise answers to certain TTI queries, while letting the
/// target independent and default TTI implementations handle the rest.
///
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_R600_AMDGPUTARGETTRANSFORMINFO_H
#define LLVM_LIB_TARGET_R600_AMDGPUTARGETTRANSFORMINFO_H
#include "AMDGPU.h"
#include "AMDGPUTargetMachine.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/BasicTTIImpl.h"
#include "llvm/Target/TargetLowering.h"
namespace llvm {
class AMDGPUTTIImpl : public BasicTTIImplBase<AMDGPUTTIImpl> {
typedef BasicTTIImplBase<AMDGPUTTIImpl> BaseT;
typedef TargetTransformInfo TTI;
const AMDGPUSubtarget *ST;
public:
explicit AMDGPUTTIImpl(const AMDGPUTargetMachine *TM = nullptr)
: BaseT(TM), ST(TM->getSubtargetImpl()) {}
// Provide value semantics. MSVC requires that we spell all of these out.
AMDGPUTTIImpl(const AMDGPUTTIImpl &Arg)
: BaseT(static_cast<const BaseT &>(Arg)), ST(Arg.ST) {}
AMDGPUTTIImpl(AMDGPUTTIImpl &&Arg)
: BaseT(std::move(static_cast<BaseT &>(Arg))), ST(std::move(Arg.ST)) {}
AMDGPUTTIImpl &operator=(const AMDGPUTTIImpl &RHS) {
BaseT::operator=(static_cast<const BaseT &>(RHS));
ST = RHS.ST;
return *this;
}
AMDGPUTTIImpl &operator=(AMDGPUTTIImpl &&RHS) {
BaseT::operator=(std::move(static_cast<BaseT &>(RHS)));
ST = std::move(RHS.ST);
return *this;
}
bool hasBranchDivergence() { return true; }
void getUnrollingPreferences(const Function *F, Loop *L,
TTI::UnrollingPreferences &UP);
TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) {
assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
return ST->hasBCNT(TyWidth) ? TTI::PSK_FastHardware : TTI::PSK_Software;
}
unsigned getNumberOfRegisters(bool Vector);
unsigned getRegisterBitWidth(bool Vector);
unsigned getMaxInterleaveFactor();
};
} // end namespace llvm
#endif

4
llvm/lib/Target/TargetMachine.cpp
View File

@ -172,8 +172,8 @@ void TargetMachine::setDataSections(bool V) {
Options.DataSections = V;
}
void TargetMachine::addAnalysisPasses(PassManagerBase &PM) {
PM.add(createNoTargetTransformInfoPass(getDataLayout()));
TargetTransformInfo TargetMachine::getTTI() {
return TargetTransformInfo(getDataLayout());
}
static bool canUsePrivateLabel(const MCAsmInfo &AsmInfo,

3
llvm/lib/Target/TargetMachineC.cpp
View File

@ -14,6 +14,7 @@
#include "llvm-c/TargetMachine.h"
#include "llvm-c/Core.h"
#include "llvm-c/Target.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/Module.h"
#include "llvm/PassManager.h"
@ -255,5 +256,5 @@ char *LLVMGetDefaultTargetTriple(void) {
}
void LLVMAddAnalysisPasses(LLVMTargetMachineRef T, LLVMPassManagerRef PM) {
unwrap(T)->addAnalysisPasses(*unwrap(PM));
unwrap(PM)->add(createTargetTransformInfoWrapperPass(unwrap(T)->getTTI()));
}

7
llvm/lib/Target/X86/X86TargetMachine.cpp
View File

@ -14,6 +14,7 @@
#include "X86TargetMachine.h"
#include "X86.h"
#include "X86TargetObjectFile.h"
#include "X86TargetTransformInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/IR/Function.h"
#include "llvm/PassManager.h"
@ -161,11 +162,11 @@ UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
cl::init(true));
//===----------------------------------------------------------------------===//
// X86 Analysis Pass Setup
// X86 TTI query.
//===----------------------------------------------------------------------===//
void X86TargetMachine::addAnalysisPasses(PassManagerBase &PM) {
PM.add(createX86TargetTransformInfoPass(this));
TargetTransformInfo X86TargetMachine::getTTI() {
return TargetTransformInfo(X86TTIImpl(this));
}

3
llvm/lib/Target/X86/X86TargetMachine.h
View File

@ -39,8 +39,7 @@ public:
const X86Subtarget *getSubtargetImpl() const override { return &Subtarget; }
const X86Subtarget *getSubtargetImpl(const Function &F) const override;
/// \brief Register X86 analysis passes with a pass manager.
void addAnalysisPasses(PassManagerBase &PM) override;
TargetTransformInfo getTTI() override;
// Set up the pass pipeline.
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;

92
llvm/lib/Target/X86/X86TargetTransformInfo.cpp
View File

@ -14,8 +14,7 @@
///
//===----------------------------------------------------------------------===//
#include "X86.h"
#include "X86TargetMachine.h"
#include "X86TargetTransformInfo.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/BasicTTIImpl.h"
#include "llvm/IR/IntrinsicInst.h"
@ -26,95 +25,6 @@ using namespace llvm;
#define DEBUG_TYPE "x86tti"
namespace {
class X86TTIImpl : public BasicTTIImplBase<X86TTIImpl> {
typedef BasicTTIImplBase<X86TTIImpl> BaseT;
typedef TargetTransformInfo TTI;
const X86Subtarget *ST;
const X86TargetLowering *TLI;
unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract);
public:
explicit X86TTIImpl(const X86TargetMachine *TM = nullptr)
: BaseT(TM), ST(TM ? TM->getSubtargetImpl() : nullptr),
TLI(ST ? ST->getTargetLowering() : nullptr) {}
// Provide value semantics. MSVC requires that we spell all of these out.
X86TTIImpl(const X86TTIImpl &Arg)
: BaseT(static_cast<const BaseT &>(Arg)), ST(Arg.ST), TLI(Arg.TLI) {}
X86TTIImpl(X86TTIImpl &&Arg)
: BaseT(std::move(static_cast<BaseT &>(Arg))), ST(std::move(Arg.ST)),
TLI(std::move(Arg.TLI)) {}
X86TTIImpl &operator=(const X86TTIImpl &RHS) {
BaseT::operator=(static_cast<const BaseT &>(RHS));
ST = RHS.ST;
TLI = RHS.TLI;
return *this;
}
X86TTIImpl &operator=(X86TTIImpl &&RHS) {
BaseT::operator=(std::move(static_cast<BaseT &>(RHS)));
ST = std::move(RHS.ST);
TLI = std::move(RHS.TLI);
return *this;
}
/// \name Scalar TTI Implementations
/// @{
TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth);
/// @}
/// \name Vector TTI Implementations
/// @{
unsigned getNumberOfRegisters(bool Vector);
unsigned getRegisterBitWidth(bool Vector);
unsigned getMaxInterleaveFactor();
unsigned getArithmeticInstrCost(
unsigned Opcode, Type *Ty,
TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue,
TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,
TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None);
unsigned getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index,
Type *SubTp);
unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src);
unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy);
unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index);
unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
unsigned AddressSpace);
unsigned getMaskedMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
unsigned AddressSpace);
unsigned getAddressComputationCost(Type *PtrTy, bool IsComplex);
unsigned getReductionCost(unsigned Opcode, Type *Ty, bool IsPairwiseForm);
unsigned getIntImmCost(int64_t);
unsigned getIntImmCost(const APInt &Imm, Type *Ty);
unsigned getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
Type *Ty);
unsigned getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
Type *Ty);
bool isLegalMaskedLoad(Type *DataType, int Consecutive);
bool isLegalMaskedStore(Type *DataType, int Consecutive);
/// @}
};
} // end anonymous namespace
ImmutablePass *
llvm::createX86TargetTransformInfoPass(const X86TargetMachine *TM) {
return new TargetTransformInfoWrapperPass(X86TTIImpl(TM));
}
//===----------------------------------------------------------------------===//
//
// X86 cost model.

110
llvm/lib/Target/X86/X86TargetTransformInfo.h Normal file
View File

@ -0,0 +1,110 @@
//===-- X86TargetTransformInfo.h - X86 specific TTI -------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
/// \file
/// This file a TargetTransformInfo::Concept conforming object specific to the
/// X86 target machine. It uses the target's detailed information to
/// provide more precise answers to certain TTI queries, while letting the
/// target independent and default TTI implementations handle the rest.
///
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_X86_X86TARGETTRANSFORMINFO_H
#define LLVM_LIB_TARGET_X86_X86TARGETTRANSFORMINFO_H
#include "X86.h"
#include "X86TargetMachine.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/BasicTTIImpl.h"
#include "llvm/Target/TargetLowering.h"
namespace llvm {
class X86TTIImpl : public BasicTTIImplBase<X86TTIImpl> {
typedef BasicTTIImplBase<X86TTIImpl> BaseT;
typedef TargetTransformInfo TTI;
const X86Subtarget *ST;
const X86TargetLowering *TLI;
unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract);
public:
explicit X86TTIImpl(const X86TargetMachine *TM = nullptr)
: BaseT(TM), ST(TM ? TM->getSubtargetImpl() : nullptr),
TLI(ST ? ST->getTargetLowering() : nullptr) {}
// Provide value semantics. MSVC requires that we spell all of these out.
X86TTIImpl(const X86TTIImpl &Arg)
: BaseT(static_cast<const BaseT &>(Arg)), ST(Arg.ST), TLI(Arg.TLI) {}
X86TTIImpl(X86TTIImpl &&Arg)
: BaseT(std::move(static_cast<BaseT &>(Arg))), ST(std::move(Arg.ST)),
TLI(std::move(Arg.TLI)) {}
X86TTIImpl &operator=(const X86TTIImpl &RHS) {
BaseT::operator=(static_cast<const BaseT &>(RHS));
ST = RHS.ST;
TLI = RHS.TLI;
return *this;
}
X86TTIImpl &operator=(X86TTIImpl &&RHS) {
BaseT::operator=(std::move(static_cast<BaseT &>(RHS)));
ST = std::move(RHS.ST);
TLI = std::move(RHS.TLI);
return *this;
}
/// \name Scalar TTI Implementations
/// @{
TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth);
/// @}
/// \name Vector TTI Implementations
/// @{
unsigned getNumberOfRegisters(bool Vector);
unsigned getRegisterBitWidth(bool Vector);
unsigned getMaxInterleaveFactor();
unsigned getArithmeticInstrCost(
unsigned Opcode, Type *Ty,
TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue,
TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,
TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None);
unsigned getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index,
Type *SubTp);
unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src);
unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy);
unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index);
unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
unsigned AddressSpace);
unsigned getMaskedMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
unsigned AddressSpace);
unsigned getAddressComputationCost(Type *PtrTy, bool IsComplex);
unsigned getReductionCost(unsigned Opcode, Type *Ty, bool IsPairwiseForm);
unsigned getIntImmCost(int64_t);
unsigned getIntImmCost(const APInt &Imm, Type *Ty);
unsigned getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
Type *Ty);
unsigned getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
Type *Ty);
bool isLegalMaskedLoad(Type *DataType, int Consecutive);
bool isLegalMaskedStore(Type *DataType, int Consecutive);
/// @}
};
;
} // end namespace llvm
#endif

1
llvm/lib/Target/XCore/CMakeLists.txt
View File

@ -22,7 +22,6 @@ add_llvm_target(XCoreCodeGen
XCoreSubtarget.cpp
XCoreTargetMachine.cpp
XCoreTargetObjectFile.cpp
XCoreTargetTransformInfo.cpp
XCoreSelectionDAGInfo.cpp
XCoreFrameToArgsOffsetElim.cpp
)

5
llvm/lib/Target/XCore/XCoreTargetMachine.cpp
View File

@ -12,6 +12,7 @@
#include "XCoreTargetMachine.h"
#include "XCoreTargetObjectFile.h"
#include "XCoreTargetTransformInfo.h"
#include "XCore.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/IR/Module.h"
@ -82,6 +83,6 @@ extern "C" void LLVMInitializeXCoreTarget() {
RegisterTargetMachine<XCoreTargetMachine> X(TheXCoreTarget);
}
void XCoreTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
PM.add(createXCoreTargetTransformInfoPass(this));
TargetTransformInfo XCoreTargetMachine::getTTI() {
return TargetTransformInfo(XCoreTTIImpl(this));
}

2
llvm/lib/Target/XCore/XCoreTargetMachine.h
View File

@ -36,7 +36,7 @@ public:
// Pass Pipeline Configuration
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
void addAnalysisPasses(PassManagerBase &PM) override;
TargetTransformInfo getTTI() override;
TargetLoweringObjectFile *getObjFileLowering() const override {
return TLOF.get();
}

29
llvm/lib/Target/XCore/XCoreTargetTransformInfo.cpp → llvm/lib/Target/XCore/XCoreTargetTransformInfo.h
View File

@ -1,4 +1,4 @@
//===-- XCoreTargetTransformInfo.cpp - XCore specific TTI pass ----------------===//
//===-- XCoreTargetTransformInfo.h - XCore specific TTI ---------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -7,25 +7,23 @@
//
//===----------------------------------------------------------------------===//
/// \file
/// This file implements a TargetTransformInfo analysis pass specific to the
/// XCore target machine. It uses the target's detailed information to provide
/// more precise answers to certain TTI queries, while letting the target
/// independent and default TTI implementations handle the rest.
/// This file a TargetTransformInfo::Concept conforming object specific to the
/// XCore target machine. It uses the target's detailed information to
/// provide more precise answers to certain TTI queries, while letting the
/// target independent and default TTI implementations handle the rest.
///
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_XCORE_XCORETARGETTRANSFORMINFO_H
#define LLVM_LIB_TARGET_XCORE_XCORETARGETTRANSFORMINFO_H
#include "XCore.h"
#include "XCoreTargetMachine.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/BasicTTIImpl.h"
#include "llvm/Support/Debug.h"
#include "llvm/Target/CostTable.h"
#include "llvm/Target/TargetLowering.h"
using namespace llvm;
#define DEBUG_TYPE "xcoretti"
namespace {
namespace llvm {
class XCoreTTIImpl : public BasicTTIImplBase<XCoreTTIImpl> {
typedef BasicTTIImplBase<XCoreTTIImpl> BaseT;
@ -50,15 +48,12 @@ public:
unsigned getNumberOfRegisters(bool Vector) {
if (Vector) {
return 0;
return 0;
}
return 12;
}
};
} // end anonymous namespace
} // end namespace llvm
ImmutablePass *
llvm::createXCoreTargetTransformInfoPass(const XCoreTargetMachine *TM) {
return new TargetTransformInfoWrapperPass(XCoreTTIImpl(TM));
}
#endif

13
llvm/tools/opt/opt.cpp
View File

@ -427,21 +427,16 @@ int main(int argc, char **argv) {
std::unique_ptr<TargetMachine> TM(Machine);
// Add internal analysis passes from the target machine.
if (TM)
TM->addAnalysisPasses(Passes);
else
Passes.add(createNoTargetTransformInfoPass(DL));
Passes.add(createTargetTransformInfoWrapperPass(
TM ? TM->getTTI() : TargetTransformInfo(DL)));
std::unique_ptr<FunctionPassManager> FPasses;
if (OptLevelO1 || OptLevelO2 || OptLevelOs || OptLevelOz || OptLevelO3) {
FPasses.reset(new FunctionPassManager(M.get()));
if (DL)
FPasses->add(new DataLayoutPass());
if (TM)
TM->addAnalysisPasses(*FPasses);
else
FPasses->add(createNoTargetTransformInfoPass(DL));
FPasses->add(createTargetTransformInfoWrapperPass(
TM ? TM->getTTI() : TargetTransformInfo(DL)));
}
if (PrintBreakpoints) {