Power9] Implement new vsx instructions: compare and conversion
This change implements the following vsx instructions: Quad/Double-Precision Compare: xscmpoqp xscmpuqp xscmpexpdp xscmpexpqp xscmpeqdp xscmpgedp xscmpgtdp xscmpnedp xvcmpnedp(.) xvcmpnesp(.) Quad-Precision Floating-Point Conversion xscvqpdp(o) xscvdpqp xscvqpsdz xscvqpswz xscvqpudz xscvqpuwz xscvsdqp xscvudqp xscvdphp xscvhpdp xvcvhpsp xvcvsphp xsrqpi xsrqpix xsrqpxp 28 instructions Phabricator: http://reviews.llvm.org/D16709 llvm-svn: 262068
This commit is contained in:
Kit Barton
parent
e50f744743
commit
93612ec5f2
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@ -124,6 +124,12 @@ def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true",
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def FeatureP8Vector : SubtargetFeature<"power8-vector", "HasP8Vector", "true",
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"Enable POWER8 vector instructions",
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[FeatureVSX, FeatureP8Altivec]>;
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def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true",
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"Enable POWER9 Altivec instructions",
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[FeatureP8Altivec]>;
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def FeatureP9Vector : SubtargetFeature<"power9-vector", "HasP9Vector", "true",
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"Enable POWER9 vector instructions",
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[FeatureP8Vector, FeatureP9Altivec]>;
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def FeatureDirectMove :
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SubtargetFeature<"direct-move", "HasDirectMove", "true",
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"Enable Power8 direct move instructions",
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@ -747,6 +747,13 @@ class XForm_htm3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
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let Inst{31} = RC;
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}
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// e.g. [PO VRT XO VRB XO /] or [PO VRT XO VRB XO RO]
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class X_RD5_XO5_RS5<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL,
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string asmstr, InstrItinClass itin, list<dag> pattern>
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: XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
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let A = xo2;
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}
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// XX*-Form (VSX)
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class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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@ -820,6 +827,22 @@ class XX2Form_2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
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let Inst{31} = XT{5};
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}
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class XX2_RD6_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL,
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string asmstr, InstrItinClass itin, list<dag> pattern>
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: I<opcode, OOL, IOL, asmstr, itin> {
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bits<6> XT;
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bits<6> XB;
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let Pattern = pattern;
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let Inst{6-10} = XT{4-0};
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let Inst{11-15} = xo2;
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let Inst{16-20} = XB{4-0};
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let Inst{21-29} = xo;
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let Inst{30} = XB{5};
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let Inst{31} = XT{5};
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}
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class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: I<opcode, OOL, IOL, asmstr, itin> {
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@ -1783,3 +1783,138 @@ def : Pat<(i64 (bitconvert f64:$S)),
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def : Pat<(f64 (bitconvert i64:$S)),
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(f64 (MTVSRD $S))>;
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}
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// The following VSX instructions were introduced in Power ISA 3.0
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def HasP9Vector : Predicate<"PPCSubTarget->hasP9Vector()">;
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let Predicates = [HasP9Vector] in {
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// [PO VRT XO VRB XO /]
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class X_VT5_XO5_VB5<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc,
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list<dag> pattern>
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: X_RD5_XO5_RS5<opcode, xo2, xo, (outs vrrc:$vT), (ins vrrc:$vB),
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!strconcat(opc, " $vT, $vB"), IIC_VecFP, pattern>;
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// [PO VRT XO VRB XO RO], Round to Odd version of [PO VRT XO VRB XO /]
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class X_VT5_XO5_VB5_Ro<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc,
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list<dag> pattern>
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: X_VT5_XO5_VB5<opcode, xo2, xo, opc, pattern>, isDOT;
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// [PO VRT XO VRB XO /], but the VRB is only used the left 64 bits (or less),
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// So we use different operand class for VRB
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class X_VT5_XO5_VB5_TyVB<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc,
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RegisterOperand vbtype, list<dag> pattern>
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: X_RD5_XO5_RS5<opcode, xo2, xo, (outs vrrc:$vT), (ins vbtype:$vB),
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!strconcat(opc, " $vT, $vB"), IIC_VecFP, pattern>;
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// [PO T XO B XO BX TX]
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class XX2_XT6_XO5_XB6<bits<6> opcode, bits<5> xo2, bits<9> xo, string opc,
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RegisterOperand vtype, list<dag> pattern>
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: XX2_RD6_XO5_RS6<opcode, xo2, xo, (outs vtype:$XT), (ins vtype:$XB),
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!strconcat(opc, " $XT, $XB"), IIC_VecFP, pattern>;
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// [PO T A B XO AX BX TX], src and dest register use different operand class
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class XX3_XT5_XA5_XB5<bits<6> opcode, bits<8> xo, string opc,
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RegisterOperand xty, RegisterOperand aty, RegisterOperand bty,
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InstrItinClass itin, list<dag> pattern>
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: XX3Form<opcode, xo, (outs xty:$XT), (ins aty:$XA, bty:$XB),
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!strconcat(opc, " $XT, $XA, $XB"), itin, pattern>;
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//===--------------------------------------------------------------------===//
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// Quad/Double-Precision Compare Instructions:
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// [PO BF // VRA VRB XO /]
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class X_BF3_VA5_VB5<bits<6> opcode, bits<10> xo, string opc,
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list<dag> pattern>
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: XForm_17<opcode, xo, (outs crrc:$crD), (ins vrrc:$VA, vrrc:$VB),
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!strconcat(opc, " $crD, $VA, $VB"), IIC_FPCompare> {
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let Pattern = pattern;
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}
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// QP Compare Ordered/Unordered
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def XSCMPOQP : X_BF3_VA5_VB5<63, 132, "xscmpoqp", []>;
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def XSCMPUQP : X_BF3_VA5_VB5<63, 644, "xscmpuqp", []>;
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// DP/QP Compare Exponents
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def XSCMPEXPDP : XX3Form_1<60, 59,
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(outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB),
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"xscmpexpdp $crD, $XA, $XB", IIC_FPCompare, []>;
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def XSCMPEXPQP : X_BF3_VA5_VB5<63, 164, "xscmpexpqp", []>;
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// DP Compare ==, >=, >, !=
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// Use vsrc for XT, because the entire register of XT is set.
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// XT.dword[1] = 0x0000_0000_0000_0000
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def XSCMPEQDP : XX3_XT5_XA5_XB5<60, 3, "xscmpeqdp", vsrc, vsfrc, vsfrc,
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IIC_FPCompare, []>;
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def XSCMPGEDP : XX3_XT5_XA5_XB5<60, 19, "xscmpgedp", vsrc, vsfrc, vsfrc,
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IIC_FPCompare, []>;
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def XSCMPGTDP : XX3_XT5_XA5_XB5<60, 11, "xscmpgtdp", vsrc, vsfrc, vsfrc,
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IIC_FPCompare, []>;
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def XSCMPNEDP : XX3_XT5_XA5_XB5<60, 27, "xscmpnedp", vsrc, vsfrc, vsfrc,
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IIC_FPCompare, []>;
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// Vector Compare Not Equal
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def XVCMPNEDP : XX3Form_Rc<60, 123,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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"xvcmpnedp $XT, $XA, $XB", IIC_VecFPCompare, []>;
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let Defs = [CR6] in
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def XVCMPNEDPo : XX3Form_Rc<60, 123,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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"xvcmpnedp. $XT, $XA, $XB", IIC_VecFPCompare, []>,
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isDOT;
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def XVCMPNESP : XX3Form_Rc<60, 91,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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"xvcmpnesp $XT, $XA, $XB", IIC_VecFPCompare, []>;
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let Defs = [CR6] in
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def XVCMPNESPo : XX3Form_Rc<60, 91,
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(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
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"xvcmpnesp. $XT, $XA, $XB", IIC_VecFPCompare, []>,
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isDOT;
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//===--------------------------------------------------------------------===//
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// Quad-Precision Floating-Point Conversion Instructions:
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// Convert DP -> QP
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def XSCVDPQP : X_VT5_XO5_VB5_TyVB<63, 22, 836, "xscvdpqp", vsfrc, []>;
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// Round & Convert QP -> DP (dword[1] is set to zero)
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def XSCVQPDP : X_VT5_XO5_VB5 <63, 20, 836, "xscvqpdp" , []>;
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def XSCVQPDPO : X_VT5_XO5_VB5_Ro<63, 20, 836, "xscvqpdpo", []>;
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// Truncate & Convert QP -> (Un)Signed (D)Word (dword[1] is set to zero)
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def XSCVQPSDZ : X_VT5_XO5_VB5<63, 25, 836, "xscvqpsdz", []>;
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def XSCVQPSWZ : X_VT5_XO5_VB5<63, 9, 836, "xscvqpswz", []>;
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def XSCVQPUDZ : X_VT5_XO5_VB5<63, 17, 836, "xscvqpudz", []>;
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def XSCVQPUWZ : X_VT5_XO5_VB5<63, 1, 836, "xscvqpuwz", []>;
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// Convert (Un)Signed DWord -> QP
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def XSCVSDQP : X_VT5_XO5_VB5_TyVB<63, 10, 836, "xscvsdqp", vsfrc, []>;
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def XSCVUDQP : X_VT5_XO5_VB5_TyVB<63, 2, 836, "xscvudqp", vsfrc, []>;
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//===--------------------------------------------------------------------===//
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// Round to Floating-Point Integer Instructions
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// (Round &) Convert DP <-> HP
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// Note! xscvdphp's src and dest register both use the left 64 bits, so we use
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// vsfrc for src and dest register. xscvhpdp's src only use the left 16 bits,
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// but we still use vsfrc for it.
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def XSCVDPHP : XX2_XT6_XO5_XB6<60, 17, 347, "xscvdphp", vsfrc, []>;
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def XSCVHPDP : XX2_XT6_XO5_XB6<60, 16, 347, "xscvhpdp", vsfrc, []>;
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// Vector HP -> SP
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def XVCVHPSP : XX2_XT6_XO5_XB6<60, 24, 475, "xvcvhpsp", vsrc, []>;
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def XVCVSPHP : XX2_XT6_XO5_XB6<60, 25, 475, "xvcvsphp", vsrc, []>;
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class Z23_VT5_R1_VB5_RMC2_EX1<bits<6> opcode, bits<8> xo, bit ex, string opc,
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list<dag> pattern>
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: Z23Form_1<opcode, xo,
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(outs vrrc:$vT), (ins u1imm:$r, vrrc:$vB, u2imm:$rmc),
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!strconcat(opc, " $r, $vT, $vB, $rmc"), IIC_VecFP, pattern> {
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let RC = ex;
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}
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// Round to Quad-Precision Integer [with Inexact]
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def XSRQPI : Z23_VT5_R1_VB5_RMC2_EX1<63, 5, 0, "xsrqpi" , []>;
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def XSRQPIX : Z23_VT5_R1_VB5_RMC2_EX1<63, 5, 1, "xsrqpix", []>;
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// Round Quad-Precision to Double-Extended Precision (fp80)
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def XSRQPXP : Z23_VT5_R1_VB5_RMC2_EX1<63, 37, 0, "xsrqpxp", []>;
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} // end HasP9Vector
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@ -70,6 +70,8 @@ void PPCSubtarget::initializeEnvironment() {
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HasP8Vector = false;
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HasP8Altivec = false;
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HasP8Crypto = false;
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HasP9Vector = false;
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HasP9Altivec = false;
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HasFCPSGN = false;
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HasFSQRT = false;
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HasFRE = false;
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@ -92,6 +92,8 @@ protected:
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bool HasP8Vector;
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bool HasP8Altivec;
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bool HasP8Crypto;
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bool HasP9Vector;
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bool HasP9Altivec;
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bool HasFCPSGN;
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bool HasFSQRT;
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bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
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@ -230,6 +232,8 @@ public:
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bool hasP8Vector() const { return HasP8Vector; }
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bool hasP8Altivec() const { return HasP8Altivec; }
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bool hasP8Crypto() const { return HasP8Crypto; }
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bool hasP9Vector() const { return HasP9Vector; }
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bool hasP9Altivec() const { return HasP9Altivec; }
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bool hasMFOCRF() const { return HasMFOCRF; }
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bool hasISEL() const { return HasISEL; }
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bool hasPOPCNTD() const { return HasPOPCNTD; }
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@ -0,0 +1,87 @@
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//===- README_P9.txt - Notes for improving Power9 code gen ----------------===//
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TODO: Instructions Need Implement Instrinstics or Map to LLVM IR
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Altivec:
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VSX:
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- QP Compare Ordered/Unordered: xscmpoqp xscmpuqp
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. ref: XSCMPUDP
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def XSCMPUDP : XX3Form_1<60, 35,
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(outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB),
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"xscmpudp $crD, $XA, $XB", IIC_FPCompare, []>;
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. No SDAG, intrinsic, builtin are required??
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Or llvm fcmp order/unorder compare??
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- DP/QP Compare Exponents: xscmpexpdp xscmpexpqp
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. No SDAG, intrinsic, builtin are required?
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- DP Compare ==, >=, >, !=: xscmpeqdp xscmpgedp xscmpgtdp xscmpnedp
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. I checked existing instruction "XSCMPUDP". They are different in target
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register. "XSCMPUDP" write to CR field, xscmp*dp write to VSX register
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. Use instrinsic:
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(set i128:$XT, (int_ppc_vsx_xscmpeqdp f64:$XA, f64:$XB))
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(set i128:$XT, (int_ppc_vsx_xscmpgedp f64:$XA, f64:$XB))
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(set i128:$XT, (int_ppc_vsx_xscmpgtdp f64:$XA, f64:$XB))
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(set i128:$XT, (int_ppc_vsx_xscmpnedp f64:$XA, f64:$XB))
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- Vector Compare Not Equal: xvcmpnedp xvcmpnedp. xvcmpnesp xvcmpnesp.
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. Similar to xvcmpeqdp:
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defm XVCMPEQDP : XX3Form_Rcr<60, 99,
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"xvcmpeqdp", "$XT, $XA, $XB", IIC_VecFPCompare,
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int_ppc_vsx_xvcmpeqdp, v2i64, v2f64>;
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. So we should use "XX3Form_Rcr" to implement instrinsic
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- Convert DP -> QP: xscvdpqp
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. Similar to XSCVDPSP:
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def XSCVDPSP : XX2Form<60, 265,
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(outs vsfrc:$XT), (ins vsfrc:$XB),
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"xscvdpsp $XT, $XB", IIC_VecFP, []>;
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. So, No SDAG, intrinsic, builtin are required??
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- Round & Convert QP -> DP (dword[1] is set to zero): xscvqpdp xscvqpdpo
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. Similar to XSCVDPSP
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. No SDAG, intrinsic, builtin are required??
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- Truncate & Convert QP -> (Un)Signed (D)Word (dword[1] is set to zero):
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xscvqpsdz xscvqpswz xscvqpudz xscvqpuwz
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. According to PowerISA_V3.0, these are similar to "XSCVDPSXDS", "XSCVDPSXWS",
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"XSCVDPUXDS", "XSCVDPUXWS"
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. DAG patterns:
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(set f128:$XT, (PPCfctidz f128:$XB)) // xscvqpsdz
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(set f128:$XT, (PPCfctiwz f128:$XB)) // xscvqpswz
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(set f128:$XT, (PPCfctiduz f128:$XB)) // xscvqpudz
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(set f128:$XT, (PPCfctiwuz f128:$XB)) // xscvqpuwz
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- Convert (Un)Signed DWord -> QP: xscvsdqp xscvudqp
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. Similar to XSCVSXDSP
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. (set f128:$XT, (PPCfcfids f64:$XB)) // xscvsdqp
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(set f128:$XT, (PPCfcfidus f64:$XB)) // xscvudqp
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- (Round &) Convert DP <-> HP: xscvdphp xscvhpdp
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. Similar to XSCVDPSP
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. No SDAG, intrinsic, builtin are required??
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- Vector HP -> SP: xvcvhpsp xvcvsphp
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. Similar to XVCVDPSP:
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def XVCVDPSP : XX2Form<60, 393,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvdpsp $XT, $XB", IIC_VecFP, []>;
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. No SDAG, intrinsic, builtin are required??
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- Round to Quad-Precision Integer: xsrqpi xsrqpix
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. These are combination of "XSRDPI", "XSRDPIC", "XSRDPIM", .., because you
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need to assign rounding mode in instruction
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. Provide builtin?
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(set f128:$vT, (int_ppc_vsx_xsrqpi f128:$vB))
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(set f128:$vT, (int_ppc_vsx_xsrqpix f128:$vB))
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- Round Quad-Precision to Double-Extended Precision (fp80): xsrqpxp
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. Provide builtin?
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(set f128:$vT, (int_ppc_vsx_xsrqpxp f128:$vB))
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@ -539,3 +539,89 @@
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# CHECK: mtvsrwz 0, 3
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0x7c 0x03 0x01 0xe6
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# Power9 Instructions:
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# CHECK: xscmpoqp 6, 31, 27
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0xff 0x1f 0xd9 0x08
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# CHECK: xscmpuqp 6, 31, 27
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0xff 0x1f 0xdd 0x08
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# CHECK: xscmpexpdp 6, 63, 27
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0xf3 0x1f 0xd9 0xdc
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# CHECK: xscmpexpqp 6, 31, 27
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0xff 0x1f 0xd9 0x48
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|
||||
# CHECK: xscmpeqdp 7, 63, 27
|
||||
0xf0 0xff 0xd8 0x1c
|
||||
|
||||
# CHECK: xscmpgedp 7, 63, 27
|
||||
0xf0 0xff 0xd8 0x9c
|
||||
|
||||
# CHECK: xscmpgtdp 7, 63, 27
|
||||
0xf0 0xff 0xd8 0x5c
|
||||
|
||||
# CHECK: xscmpnedp 7, 63, 27
|
||||
0xf0 0xff 0xd8 0xdc
|
||||
|
||||
# CHECK: xvcmpnedp 7, 63, 27
|
||||
0xf0 0xff 0xdb 0xdc
|
||||
|
||||
# CHECK: xvcmpnedp. 7, 63, 27
|
||||
0xf0 0xff 0xdf 0xdc
|
||||
|
||||
# CHECK: xvcmpnesp 7, 63, 27
|
||||
0xf0 0xff 0xda 0xdc
|
||||
|
||||
# CHECK: xvcmpnesp. 7, 63, 27
|
||||
0xf0 0xff 0xde 0xdc
|
||||
|
||||
# CHECK: xscvdpqp 7, 27
|
||||
0xfc 0xf6 0xde 0x88
|
||||
|
||||
# CHECK: xscvqpdp 7, 27
|
||||
0xfc 0xf4 0xde 0x88
|
||||
|
||||
# CHECK: xscvqpdpo 7, 27
|
||||
0xfc 0xf4 0xde 0x89
|
||||
|
||||
# CHECK: xscvqpsdz 7, 27
|
||||
0xfc 0xf9 0xde 0x88
|
||||
|
||||
# CHECK: xscvqpswz 7, 27
|
||||
0xfc 0xe9 0xde 0x88
|
||||
|
||||
# CHECK: xscvqpudz 7, 27
|
||||
0xfc 0xf1 0xde 0x88
|
||||
|
||||
# CHECK: xscvqpuwz 7, 27
|
||||
0xfc 0xe1 0xde 0x88
|
||||
|
||||
# CHECK: xscvsdqp 7, 27
|
||||
0xfc 0xea 0xde 0x88
|
||||
|
||||
# CHECK: xscvudqp 7, 27
|
||||
0xfc 0xe2 0xde 0x88
|
||||
|
||||
# CHECK: xscvdphp 7, 63
|
||||
0xf0 0xf1 0xfd 0x6e
|
||||
|
||||
# CHECK: xscvhpdp 7, 63
|
||||
0xf0 0xf0 0xfd 0x6e
|
||||
|
||||
# CHECK: xvcvhpsp 7, 63
|
||||
0xf0 0xf8 0xff 0x6e
|
||||
|
||||
# CHECK: xvcvsphp 7, 63
|
||||
0xf0 0xf9 0xff 0x6e
|
||||
|
||||
# CHECK: xsrqpi 1, 7, 27, 2
|
||||
0xfc 0xe1 0xdc 0x0a
|
||||
|
||||
# CHECK: xsrqpix 1, 7, 27, 2
|
||||
0xfc 0xe1 0xdc 0x0b
|
||||
|
||||
# CHECK: xsrqpxp 1, 7, 27, 2
|
||||
0xfc 0xe1 0xdc 0x4a
|
||||
|
|
|
|||
|
|
@ -547,3 +547,113 @@
|
|||
# CHECK-BE: mtvsrwz 0, 3 # encoding: [0x7c,0x03,0x01,0xe6]
|
||||
# CHECK-LE: mtvsrwz 0, 3 # encoding: [0xe6,0x01,0x03,0x7c]
|
||||
mtvsrwz 0, 3
|
||||
|
||||
# Power9 Instructions:
|
||||
|
||||
# Compare Ordered/Unordered
|
||||
# CHECK-BE: xscmpoqp 6, 31, 27 # encoding: [0xff,0x1f,0xd9,0x08]
|
||||
# CHECK-LE: xscmpoqp 6, 31, 27 # encoding: [0x08,0xd9,0x1f,0xff]
|
||||
xscmpoqp 6, 31, 27
|
||||
# CHECK-BE: xscmpuqp 6, 31, 27 # encoding: [0xff,0x1f,0xdd,0x08]
|
||||
# CHECK-LE: xscmpuqp 6, 31, 27 # encoding: [0x08,0xdd,0x1f,0xff]
|
||||
xscmpuqp 6, 31, 27
|
||||
|
||||
# Compare Exponents
|
||||
# CHECK-BE: xscmpexpdp 6, 63, 27 # encoding: [0xf3,0x1f,0xd9,0xdc]
|
||||
# CHECK-LE: xscmpexpdp 6, 63, 27 # encoding: [0xdc,0xd9,0x1f,0xf3]
|
||||
xscmpexpdp 6, 63, 27
|
||||
# CHECK-BE: xscmpexpqp 6, 31, 27 # encoding: [0xff,0x1f,0xd9,0x48]
|
||||
# CHECK-LE: xscmpexpqp 6, 31, 27 # encoding: [0x48,0xd9,0x1f,0xff]
|
||||
xscmpexpqp 6, 31, 27
|
||||
|
||||
# Compare ==, >=, >, !=
|
||||
# CHECK-BE: xscmpeqdp 7, 63, 27 # encoding: [0xf0,0xff,0xd8,0x1c]
|
||||
# CHECK-LE: xscmpeqdp 7, 63, 27 # encoding: [0x1c,0xd8,0xff,0xf0]
|
||||
xscmpeqdp 7, 63, 27
|
||||
# CHECK-BE: xscmpgedp 7, 63, 27 # encoding: [0xf0,0xff,0xd8,0x9c]
|
||||
# CHECK-LE: xscmpgedp 7, 63, 27 # encoding: [0x9c,0xd8,0xff,0xf0]
|
||||
xscmpgedp 7, 63, 27
|
||||
# CHECK-BE: xscmpgtdp 7, 63, 27 # encoding: [0xf0,0xff,0xd8,0x5c]
|
||||
# CHECK-LE: xscmpgtdp 7, 63, 27 # encoding: [0x5c,0xd8,0xff,0xf0]
|
||||
xscmpgtdp 7, 63, 27
|
||||
# CHECK-BE: xscmpnedp 7, 63, 27 # encoding: [0xf0,0xff,0xd8,0xdc]
|
||||
# CHECK-LE: xscmpnedp 7, 63, 27 # encoding: [0xdc,0xd8,0xff,0xf0]
|
||||
xscmpnedp 7, 63, 27
|
||||
|
||||
# Vector Compare Not Equal
|
||||
# CHECK-BE: xvcmpnedp 7, 63, 27 # encoding: [0xf0,0xff,0xdb,0xdc]
|
||||
# CHECK-LE: xvcmpnedp 7, 63, 27 # encoding: [0xdc,0xdb,0xff,0xf0]
|
||||
xvcmpnedp 7, 63, 27
|
||||
# CHECK-BE: xvcmpnedp. 7, 63, 27 # encoding: [0xf0,0xff,0xdf,0xdc]
|
||||
# CHECK-LE: xvcmpnedp. 7, 63, 27 # encoding: [0xdc,0xdf,0xff,0xf0]
|
||||
xvcmpnedp. 7, 63, 27
|
||||
# CHECK-BE: xvcmpnesp 7, 63, 27 # encoding: [0xf0,0xff,0xda,0xdc]
|
||||
# CHECK-LE: xvcmpnesp 7, 63, 27 # encoding: [0xdc,0xda,0xff,0xf0]
|
||||
xvcmpnesp 7, 63, 27
|
||||
# CHECK-BE: xvcmpnesp. 7, 63, 27 # encoding: [0xf0,0xff,0xde,0xdc]
|
||||
# CHECK-LE: xvcmpnesp. 7, 63, 27 # encoding: [0xdc,0xde,0xff,0xf0]
|
||||
xvcmpnesp. 7, 63, 27
|
||||
|
||||
# Convert DP -> QP
|
||||
# CHECK-BE: xscvdpqp 7, 27 # encoding: [0xfc,0xf6,0xde,0x88]
|
||||
# CHECK-LE: xscvdpqp 7, 27 # encoding: [0x88,0xde,0xf6,0xfc]
|
||||
xscvdpqp 7, 27
|
||||
|
||||
# Round & Convert QP -> DP
|
||||
# CHECK-BE: xscvqpdp 7, 27 # encoding: [0xfc,0xf4,0xde,0x88]
|
||||
# CHECK-LE: xscvqpdp 7, 27 # encoding: [0x88,0xde,0xf4,0xfc]
|
||||
xscvqpdp 7, 27
|
||||
# CHECK-BE: xscvqpdpo 7, 27 # encoding: [0xfc,0xf4,0xde,0x89]
|
||||
# CHECK-LE: xscvqpdpo 7, 27 # encoding: [0x89,0xde,0xf4,0xfc]
|
||||
xscvqpdpo 7, 27
|
||||
|
||||
# Truncate & Convert QP -> (Un)Signed (D)Word
|
||||
# CHECK-BE: xscvqpsdz 7, 27 # encoding: [0xfc,0xf9,0xde,0x88]
|
||||
# CHECK-LE: xscvqpsdz 7, 27 # encoding: [0x88,0xde,0xf9,0xfc]
|
||||
xscvqpsdz 7, 27
|
||||
# CHECK-BE: xscvqpswz 7, 27 # encoding: [0xfc,0xe9,0xde,0x88]
|
||||
# CHECK-LE: xscvqpswz 7, 27 # encoding: [0x88,0xde,0xe9,0xfc]
|
||||
xscvqpswz 7, 27
|
||||
# CHECK-BE: xscvqpudz 7, 27 # encoding: [0xfc,0xf1,0xde,0x88]
|
||||
# CHECK-LE: xscvqpudz 7, 27 # encoding: [0x88,0xde,0xf1,0xfc]
|
||||
xscvqpudz 7, 27
|
||||
# CHECK-BE: xscvqpuwz 7, 27 # encoding: [0xfc,0xe1,0xde,0x88]
|
||||
# CHECK-LE: xscvqpuwz 7, 27 # encoding: [0x88,0xde,0xe1,0xfc]
|
||||
xscvqpuwz 7, 27
|
||||
|
||||
# Convert (Un)Signed DWord -> QP
|
||||
# CHECK-BE: xscvsdqp 7, 27 # encoding: [0xfc,0xea,0xde,0x88]
|
||||
# CHECK-LE: xscvsdqp 7, 27 # encoding: [0x88,0xde,0xea,0xfc]
|
||||
xscvsdqp 7, 27
|
||||
# CHECK-BE: xscvudqp 7, 27 # encoding: [0xfc,0xe2,0xde,0x88]
|
||||
# CHECK-LE: xscvudqp 7, 27 # encoding: [0x88,0xde,0xe2,0xfc]
|
||||
xscvudqp 7, 27
|
||||
|
||||
# (Round &) Convert DP <-> HP
|
||||
# CHECK-BE: xscvdphp 7, 63 # encoding: [0xf0,0xf1,0xfd,0x6e]
|
||||
# CHECK-LE: xscvdphp 7, 63 # encoding: [0x6e,0xfd,0xf1,0xf0]
|
||||
xscvdphp 7, 63
|
||||
# CHECK-BE: xscvhpdp 7, 63 # encoding: [0xf0,0xf0,0xfd,0x6e]
|
||||
# CHECK-LE: xscvhpdp 7, 63 # encoding: [0x6e,0xfd,0xf0,0xf0]
|
||||
xscvhpdp 7, 63
|
||||
|
||||
# HP -> SP
|
||||
# CHECK-BE: xvcvhpsp 7, 63 # encoding: [0xf0,0xf8,0xff,0x6e]
|
||||
# CHECK-LE: xvcvhpsp 7, 63 # encoding: [0x6e,0xff,0xf8,0xf0]
|
||||
xvcvhpsp 7, 63
|
||||
# CHECK-BE: xvcvsphp 7, 63 # encoding: [0xf0,0xf9,0xff,0x6e]
|
||||
# CHECK-LE: xvcvsphp 7, 63 # encoding: [0x6e,0xff,0xf9,0xf0]
|
||||
xvcvsphp 7, 63
|
||||
|
||||
# Round to Quad-Precision Integer [with Inexact]
|
||||
# CHECK-BE: xsrqpi 1, 7, 27, 2 # encoding: [0xfc,0xe1,0xdc,0x0a]
|
||||
# CHECK-LE: xsrqpi 1, 7, 27, 2 # encoding: [0x0a,0xdc,0xe1,0xfc]
|
||||
xsrqpi 1, 7, 27, 2
|
||||
# CHECK-BE: xsrqpix 1, 7, 27, 2 # encoding: [0xfc,0xe1,0xdc,0x0b]
|
||||
# CHECK-LE: xsrqpix 1, 7, 27, 2 # encoding: [0x0b,0xdc,0xe1,0xfc]
|
||||
xsrqpix 1, 7, 27, 2
|
||||
|
||||
# Round Quad-Precision to Double-Extended Precision
|
||||
# CHECK-BE: xsrqpxp 1, 7, 27, 2 # encoding: [0xfc,0xe1,0xdc,0x4a]
|
||||
# CHECK-LE: xsrqpxp 1, 7, 27, 2 # encoding: [0x4a,0xdc,0xe1,0xfc]
|
||||
xsrqpxp 1, 7, 27, 2
|
||||
|
|
|
|||
Loading…
Reference in New Issue