From 933b5b7e6274bfb79725e9158ba47fd5d3a7ca47 Mon Sep 17 00:00:00 2001 From: Owen Anderson Date: Mon, 12 Nov 2007 07:39:39 +0000 Subject: [PATCH] Add a flag for indirect branch instructions. Target maintainers: please check that the instructions for your target are correctly marked. llvm-svn: 44012 --- llvm/include/llvm/Target/TargetInstrInfo.h | 5 +++++ llvm/lib/Target/ARM/ARMInstrInfo.td | 2 +- llvm/lib/Target/Alpha/AlphaInstrInfo.td | 3 +-- llvm/lib/Target/PowerPC/PPCInstrInfo.td | 3 ++- llvm/lib/Target/Target.td | 1 + llvm/lib/Target/X86/X86InstrInfo.td | 4 ++-- llvm/lib/Target/X86/X86InstrX86-64.td | 2 +- llvm/utils/TableGen/CodeGenInstruction.h | 1 + llvm/utils/TableGen/CodeGenTarget.cpp | 1 + llvm/utils/TableGen/InstrInfoEmitter.cpp | 1 + 10 files changed, 16 insertions(+), 7 deletions(-) diff --git a/llvm/include/llvm/Target/TargetInstrInfo.h b/llvm/include/llvm/Target/TargetInstrInfo.h index 1432b5f21592..a0596e47c6e2 100644 --- a/llvm/include/llvm/Target/TargetInstrInfo.h +++ b/llvm/include/llvm/Target/TargetInstrInfo.h @@ -48,6 +48,7 @@ const unsigned M_BARRIER_FLAG = 1 << 3; const unsigned M_DELAY_SLOT_FLAG = 1 << 4; const unsigned M_LOAD_FLAG = 1 << 5; const unsigned M_STORE_FLAG = 1 << 6; +const unsigned M_INDIRECT_FLAG = 1 << 7; // M_CONVERTIBLE_TO_3_ADDR - This is a 2-address instruction which can be // changed into a 3-address instruction if the first two operands cannot be @@ -237,6 +238,10 @@ public: return get(Opcode).Flags & M_BRANCH_FLAG; } + bool isIndirectBranch(MachineOpCode Opcode) const { + return get(Opcode).Flags & M_INDIRECT_FLAG; + } + /// isBarrier - Returns true if the specified instruction stops control flow /// from executing the instruction immediately following it. Examples include /// unconditional branches and return instructions. diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td index 8e59848611f3..8ff610eec55a 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.td +++ b/llvm/lib/Target/ARM/ARMInstrInfo.td @@ -773,7 +773,7 @@ let isBranch = 1, isTerminator = 1 in { def B : AXI<0xA, (outs), (ins brtarget:$target), Branch, "b $target", [(br bb:$target)]>; - let isNotDuplicable = 1 in { + let isNotDuplicable = 1, isIndirectBranch = 1 in { def BR_JTr : JTI<0x0, (outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id), "mov pc, $target \n$jt", [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>; diff --git a/llvm/lib/Target/Alpha/AlphaInstrInfo.td b/llvm/lib/Target/Alpha/AlphaInstrInfo.td index 602ab7aa8a00..f73875062ab7 100644 --- a/llvm/lib/Target/Alpha/AlphaInstrInfo.td +++ b/llvm/lib/Target/Alpha/AlphaInstrInfo.td @@ -374,8 +374,7 @@ let isReturn = 1, isTerminator = 1, Ra = 31, Rb = 26, disp = 1, Uses = [R26] in def RETDAGp : MbrpForm< 0x1A, 0x02, (ops), "ret $$31,($$26),1", [(retflag)], s_jsr>; //Return from subroutine } -let isBranch = 1, isTerminator = 1, isBarrier = 1, -Ra = 31, disp = 0 in +let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1, Ra = 31, disp = 0 in def JMP : MbrpForm< 0x1A, 0x00, (ops GPRC:$RS), "jmp $$31,($RS),0", [(brind GPRC:$RS)], s_jsr>; //Jump diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td index 6a08cea512e0..77e00e577613 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td @@ -369,7 +369,8 @@ let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p), "b${p:cc}lr ${p:reg}", BrB, [(retflag)]>; - def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>; + let isBranch = 1, isIndirectBranch = 1 in + def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>; } diff --git a/llvm/lib/Target/Target.td b/llvm/lib/Target/Target.td index 169953f0eaff..4c28f99b6f24 100644 --- a/llvm/lib/Target/Target.td +++ b/llvm/lib/Target/Target.td @@ -187,6 +187,7 @@ class Instruction { // instruction. bit isReturn = 0; // Is this instruction a return instruction? bit isBranch = 0; // Is this instruction a branch instruction? + bit isIndirectBranch = 0; // Is this instruction an indirect branch? bit isBarrier = 0; // Can control flow fall through this instruction? bit isCall = 0; // Is this instruction a call instruction? bit isLoad = 0; // Is this instruction a load instruction? diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td index e9f9bd6c1c4a..43ad9b047288 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.td +++ b/llvm/lib/Target/X86/X86InstrInfo.td @@ -294,11 +294,11 @@ let isBranch = 1, isTerminator = 1 in class IBr opcode, dag ins, string asm, list pattern> : I; -// Indirect branches let isBranch = 1, isBarrier = 1 in def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>; -let isBranch = 1, isTerminator = 1, isBarrier = 1 in { +// Indirect branches +let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst", [(brind GR32:$dst)]>; def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst", diff --git a/llvm/lib/Target/X86/X86InstrX86-64.td b/llvm/lib/Target/X86/X86InstrX86-64.td index 42863d49309c..2d9ca97e2147 100644 --- a/llvm/lib/Target/X86/X86InstrX86-64.td +++ b/llvm/lib/Target/X86/X86InstrX86-64.td @@ -120,7 +120,7 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in []>; // Branches -let isBranch = 1, isTerminator = 1, isBarrier = 1 in { +let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst", [(brind GR64:$dst)]>; def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst", diff --git a/llvm/utils/TableGen/CodeGenInstruction.h b/llvm/utils/TableGen/CodeGenInstruction.h index 6abe972880d3..245b38e0493c 100644 --- a/llvm/utils/TableGen/CodeGenInstruction.h +++ b/llvm/utils/TableGen/CodeGenInstruction.h @@ -87,6 +87,7 @@ namespace llvm { // Various boolean values we track for the instruction. bool isReturn; bool isBranch; + bool isIndirectBranch; bool isBarrier; bool isCall; bool isLoad; diff --git a/llvm/utils/TableGen/CodeGenTarget.cpp b/llvm/utils/TableGen/CodeGenTarget.cpp index ea96cf4bd279..4de05b2f83d3 100644 --- a/llvm/utils/TableGen/CodeGenTarget.cpp +++ b/llvm/utils/TableGen/CodeGenTarget.cpp @@ -379,6 +379,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr) isReturn = R->getValueAsBit("isReturn"); isBranch = R->getValueAsBit("isBranch"); + isIndirectBranch = R->getValueAsBit("isIndirectBranch"); isBarrier = R->getValueAsBit("isBarrier"); isCall = R->getValueAsBit("isCall"); isLoad = R->getValueAsBit("isLoad"); diff --git a/llvm/utils/TableGen/InstrInfoEmitter.cpp b/llvm/utils/TableGen/InstrInfoEmitter.cpp index ca8d30f0c05a..d371934bbbe6 100644 --- a/llvm/utils/TableGen/InstrInfoEmitter.cpp +++ b/llvm/utils/TableGen/InstrInfoEmitter.cpp @@ -237,6 +237,7 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, // Emit all of the target indepedent flags... if (Inst.isReturn) OS << "|M_RET_FLAG"; if (Inst.isBranch) OS << "|M_BRANCH_FLAG"; + if (Inst.isIndirectBranch) OS << "|M_INDIRECT_FLAG"; if (Inst.isBarrier) OS << "|M_BARRIER_FLAG"; if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG"; if (Inst.isCall) OS << "|M_CALL_FLAG";