[mips] Instruction selection patterns for carry-setting and using add
instructions. llvm-svn: 179421
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@ -548,10 +548,10 @@ class ADDQ_S_W_DESC : ADDU_QB_DESC_BASE<"addq_s.w", int_mips_addq_s_w,
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class SUBQ_S_W_DESC : ADDU_QB_DESC_BASE<"subq_s.w", int_mips_subq_s_w,
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class SUBQ_S_W_DESC : ADDU_QB_DESC_BASE<"subq_s.w", int_mips_subq_s_w,
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NoItinerary, CPURegs, CPURegs>;
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NoItinerary, CPURegs, CPURegs>;
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class ADDSC_DESC : ADDU_QB_DESC_BASE<"addsc", int_mips_addsc, NoItinerary,
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class ADDSC_DESC : ADDU_QB_DESC_BASE<"addsc", null_frag, NoItinerary,
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CPURegs, CPURegs>, IsCommutable;
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CPURegs, CPURegs>, IsCommutable;
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class ADDWC_DESC : ADDU_QB_DESC_BASE<"addwc", int_mips_addwc, NoItinerary,
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class ADDWC_DESC : ADDU_QB_DESC_BASE<"addwc", null_frag, NoItinerary,
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CPURegs, CPURegs>,
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CPURegs, CPURegs>,
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IsCommutable, UseDSPCtrl;
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IsCommutable, UseDSPCtrl;
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@ -1247,6 +1247,10 @@ def : DSPBinPat<ADDU_QB, v4i8, int_mips_addu_qb>;
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def : DSPBinPat<ADDU_QB, v4i8, add>;
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def : DSPBinPat<ADDU_QB, v4i8, add>;
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def : DSPBinPat<SUBU_QB, v4i8, int_mips_subu_qb>;
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def : DSPBinPat<SUBU_QB, v4i8, int_mips_subu_qb>;
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def : DSPBinPat<SUBU_QB, v4i8, sub>;
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def : DSPBinPat<SUBU_QB, v4i8, sub>;
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def : DSPBinPat<ADDSC, i32, int_mips_addsc>;
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def : DSPBinPat<ADDSC, i32, addc>;
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def : DSPBinPat<ADDWC, i32, int_mips_addwc>;
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def : DSPBinPat<ADDWC, i32, adde>;
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// Extr patterns.
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// Extr patterns.
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class EXTR_W_TY1_R2_Pat<SDPatternOperator OpNode, Instruction Instr> :
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class EXTR_W_TY1_R2_Pat<SDPatternOperator OpNode, Instruction Instr> :
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@ -179,6 +179,7 @@ def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
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AssemblerPredicate<"FeatureMips32">;
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AssemblerPredicate<"FeatureMips32">;
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def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
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def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
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AssemblerPredicate<"!FeatureMips16">;
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AssemblerPredicate<"!FeatureMips16">;
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def NotDSP : Predicate<"!Subtarget.hasDSP()">;
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class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
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class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
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let Predicates = [HasStdEnc];
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let Predicates = [HasStdEnc];
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@ -1128,10 +1129,12 @@ def : MipsPat<(i32 imm:$imm),
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// Carry MipsPatterns
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// Carry MipsPatterns
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def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs),
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def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs),
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(SUBu CPURegs:$lhs, CPURegs:$rhs)>;
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(SUBu CPURegs:$lhs, CPURegs:$rhs)>;
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def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs),
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let Predicates = [HasStdEnc, NotDSP] in {
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(ADDu CPURegs:$lhs, CPURegs:$rhs)>;
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def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs),
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def : MipsPat<(addc CPURegs:$src, immSExt16:$imm),
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(ADDu CPURegs:$lhs, CPURegs:$rhs)>;
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(ADDiu CPURegs:$src, imm:$imm)>;
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def : MipsPat<(addc CPURegs:$src, immSExt16:$imm),
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(ADDiu CPURegs:$src, imm:$imm)>;
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}
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// Call
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// Call
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def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
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def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
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@ -303,6 +303,8 @@ std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
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}
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}
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case ISD::ADDE: {
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case ISD::ADDE: {
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if (Subtarget.hasDSP()) // Select DSP instructions, ADDSC and ADDWC.
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break;
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SDValue InFlag = Node->getOperand(2);
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SDValue InFlag = Node->getOperand(2);
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Result = selectAddESubE(Mips::ADDu, InFlag, InFlag.getValue(0), DL, Node);
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Result = selectAddESubE(Mips::ADDu, InFlag, InFlag.getValue(0), DL, Node);
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return std::make_pair(true, Result);
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return std::make_pair(true, Result);
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@ -117,3 +117,14 @@ entry:
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%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
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%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
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ret { i32 } %.fca.0.insert
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ret { i32 } %.fca.0.insert
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}
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}
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; R1: test_addsc:
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; R1: addsc ${{[0-9]+}}
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; R1: addwc ${{[0-9]+}}
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define i64 @test_addsc(i64 %a, i64 %b) #1 {
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entry:
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%add = add nsw i64 %b, %a
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ret i64 %add
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}
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