parent
2c499f6561
commit
92d57cee61
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@ -137,7 +137,7 @@ SelectAddr(SDNode *Op, SDValue Addr, SDValue &Offset, SDValue &Base)
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// Operand is a result from an ADD.
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if (Addr.getOpcode() == ISD::ADD) {
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
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if (Predicate_immSExt16(CN)) {
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if (isInt<16>(CN->getSExtValue())) {
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// If the first operand is a FI, get the TargetFI Node
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
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@ -248,8 +248,8 @@ SDNode *MipsDAGToDAGISel::SelectStoreFp64(SDNode *N) {
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SDValue Chain = N->getOperand(0);
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if (!Predicate_unindexedstore(N) ||
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!Predicate_store(N))
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StoreSDNode *SN = cast<StoreSDNode>(N);
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if (SN->isTruncatingStore() || SN->getAddressingMode() != ISD::UNINDEXED)
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return NULL;
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SDValue N1 = N->getOperand(1);
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@ -96,12 +96,7 @@ def HI16 : SDNodeXForm<imm, [{
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// Node immediate fits as 16-bit sign extended on target immediate.
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// e.g. addi, andi
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def immSExt16 : PatLeaf<(imm), [{
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if (N->getValueType(0) == MVT::i32)
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return (int32_t)N->getZExtValue() == (short)N->getZExtValue();
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else
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return (int64_t)N->getZExtValue() == (short)N->getZExtValue();
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}]>;
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def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
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// Node immediate fits as 16-bit zero extended on target immediate.
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// The LO16 param means that only the lower 16 bits of the node
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