XCore target: Refactor the loading of constants into a register

This common functionality will be used to lower FRAME_TO_ARGS_OFFSET.

llvm-svn: 198610

llvm/lib/Target/XCore/XCoreInstrInfo.cpp

@@ -15,8 +15,11 @@
 #include "XCore.h"
 #include "XCoreMachineFunctionInfo.h"
 #include "llvm/ADT/STLExtras.h"
+#include "llvm/CodeGen/MachineConstantPool.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/IR/Constants.h"
+#include "llvm/IR/Function.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
@@ -399,3 +402,33 @@ ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
   Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm()));
   return false;
 }
+
+static inline bool isImmU6(unsigned val) {
+  return val < (1 << 6);
+}
+
+static inline bool isImmU16(unsigned val) {
+  return val < (1 << 16);
+}
+
+MachineBasicBlock::iterator XCoreInstrInfo::loadImmediate(
+                                              MachineBasicBlock &MBB,
+                                              MachineBasicBlock::iterator MI,
+                                              unsigned Reg, uint64_t Value) const {
+  DebugLoc dl;
+  if (MI != MBB.end()) dl = MI->getDebugLoc();
+  if (isMask_32(Value)) {
+    int N = Log2_32(Value) + 1;
+    return BuildMI(MBB, MI, dl, get(XCore::MKMSK_rus), Reg).addImm(N);
+  }
+  if (isImmU16(Value)) {
+    int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
+    return BuildMI(MBB, MI, dl, get(Opcode), Reg).addImm(Value);
+  }
+  MachineConstantPool *ConstantPool = MBB.getParent()->getConstantPool();
+  const Constant *C = ConstantInt::get(
+        Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Value);
+  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
+  return BuildMI(MBB, MI, dl, get(XCore::LDWCP_lru6), Reg)
+            .addConstantPoolIndex(Idx);
+}

llvm/lib/Target/XCore/XCoreInstrInfo.h

@@ -81,6 +81,12 @@ public:
 
   virtual bool ReverseBranchCondition(
                             SmallVectorImpl<MachineOperand> &Cond) const;
+
+  // Emit code before MBBI to load immediate value into physical register Reg.
+  // Returns an iterator to the new instruction.
+  MachineBasicBlock::iterator loadImmediate(MachineBasicBlock &MBB,
+                                            MachineBasicBlock::iterator MI,
+                                            unsigned Reg, uint64_t Value) const;
 };
 
 }

llvm/lib/Target/XCore/XCoreRegisterInfo.cpp

@@ -13,17 +13,16 @@
 
 #include "XCoreRegisterInfo.h"
 #include "XCore.h"
+#include "XCoreInstrInfo.h"
 #include "XCoreMachineFunctionInfo.h"
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/STLExtras.h"
-#include "llvm/CodeGen/MachineConstantPool.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineModuleInfo.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/RegisterScavenging.h"
-#include "llvm/IR/Constants.h"
 #include "llvm/IR/Function.h"
 #include "llvm/IR/Type.h"
 #include "llvm/Support/Debug.h"
@@ -31,7 +30,6 @@
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Target/TargetFrameLowering.h"
-#include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetOptions.h"
 
@@ -57,31 +55,9 @@ static inline bool isImmU16(unsigned val) {
   return val < (1 << 16);
 }
 
-static void loadConstant(MachineBasicBlock::iterator II,
-                         const TargetInstrInfo &TII,
-                         unsigned DstReg, int64_t Value) {
-  MachineInstr &MI = *II;
-  MachineBasicBlock &MBB = *MI.getParent();
-  DebugLoc dl = MI.getDebugLoc();
-
-  if (isMask_32(Value)) {
-    int N = Log2_32(Value) + 1;
-    BuildMI(MBB, II, dl, TII.get(XCore::MKMSK_rus), DstReg).addImm(N);
-  } else if (isImmU16(Value)) {
-    int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
-    BuildMI(MBB, II, dl, TII.get(Opcode), DstReg).addImm(Value);
-  } else {
-    MachineConstantPool *ConstantPool = MBB.getParent()->getConstantPool();
-    const Constant *C = ConstantInt::get(
-        Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Value);
-    unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
-    BuildMI(MBB, II, dl, TII.get(XCore::LDWCP_lru6), DstReg)
-        .addConstantPoolIndex(Idx);
-  }
-}
 
 static void InsertFPImmInst(MachineBasicBlock::iterator II,
-                            const TargetInstrInfo &TII,
+                            const XCoreInstrInfo &TII,
                             unsigned Reg, unsigned FrameReg, int Offset ) {
   MachineInstr &MI = *II;
   MachineBasicBlock &MBB = *MI.getParent();
@@ -110,7 +86,7 @@ static void InsertFPImmInst(MachineBasicBlock::iterator II,
 }
 
 static void InsertFPConstInst(MachineBasicBlock::iterator II,
-                              const TargetInstrInfo &TII,
+                              const XCoreInstrInfo &TII,
                               unsigned Reg, unsigned FrameReg,
                               int Offset, RegScavenger *RS ) {
   assert(RS && "requiresRegisterScavenging failed");
@@ -120,7 +96,7 @@ static void InsertFPConstInst(MachineBasicBlock::iterator II,
 
   unsigned ScratchOffset = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0);
   RS->setUsed(ScratchOffset);
-  loadConstant(II, TII, ScratchOffset, Offset);
+  TII.loadImmediate(MBB, II, ScratchOffset, Offset);
 
   switch (MI.getOpcode()) {
   case XCore::LDWFI:
@@ -145,7 +121,7 @@ static void InsertFPConstInst(MachineBasicBlock::iterator II,
 }
 
 static void InsertSPImmInst(MachineBasicBlock::iterator II,
-                            const TargetInstrInfo &TII,
+                            const XCoreInstrInfo &TII,
                             unsigned Reg, int Offset) {
   MachineInstr &MI = *II;
   MachineBasicBlock &MBB = *MI.getParent();
@@ -175,7 +151,7 @@ static void InsertSPImmInst(MachineBasicBlock::iterator II,
 }
 
 static void InsertSPConstInst(MachineBasicBlock::iterator II,
-                                const TargetInstrInfo &TII,
+                                const XCoreInstrInfo &TII,
                                 unsigned Reg, int Offset, RegScavenger *RS ) {
   assert(RS && "requiresRegisterScavenging failed");
   MachineInstr &MI = *II;
@@ -192,7 +168,7 @@ static void InsertSPConstInst(MachineBasicBlock::iterator II,
   BuildMI(MBB, II, dl, TII.get(XCore::LDAWSP_ru6), ScratchBase).addImm(0);
   unsigned ScratchOffset = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0);
   RS->setUsed(ScratchOffset);
-  loadConstant(II, TII, ScratchOffset, Offset);
+  TII.loadImmediate(MBB, II, ScratchOffset, Offset);
 
   switch (OpCode) {
   case XCore::LDWFI:
@@ -270,7 +246,9 @@ XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
   int FrameIndex = FrameOp.getIndex();
 
   MachineFunction &MF = *MI.getParent()->getParent();
-  const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
+  const XCoreInstrInfo &TII =
+          *static_cast<const XCoreInstrInfo*>(MF.getTarget().getInstrInfo());
+
   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
   int StackSize = MF.getFrameInfo()->getStackSize();