More consts on TargetLowering references.
llvm-svn: 62262
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@ -736,7 +736,7 @@ SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
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/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
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/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
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static
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static
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SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
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SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
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TargetLowering &TLI) {
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const TargetLowering &TLI) {
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int SVOffset = LD->getSrcValueOffset();
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int SVOffset = LD->getSrcValueOffset();
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SDValue Chain = LD->getChain();
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SDValue Chain = LD->getChain();
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SDValue Ptr = LD->getBasePtr();
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SDValue Ptr = LD->getBasePtr();
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@ -4982,7 +4982,7 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
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return "<<Unknown Machine Node>>";
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return "<<Unknown Machine Node>>";
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}
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}
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if (G) {
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if (G) {
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TargetLowering &TLI = G->getTargetLoweringInfo();
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const TargetLowering &TLI = G->getTargetLoweringInfo();
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const char *Name = TLI.getTargetNodeName(getOpcode());
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const char *Name = TLI.getTargetNodeName(getOpcode());
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if (Name) return Name;
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if (Name) return Name;
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return "<<Unknown Target Node>>";
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return "<<Unknown Target Node>>";
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@ -380,7 +380,7 @@ static SDValue getCopyFromParts(SelectionDAG &DAG,
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MVT ValueVT,
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MVT ValueVT,
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ISD::NodeType AssertOp = ISD::DELETED_NODE) {
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ISD::NodeType AssertOp = ISD::DELETED_NODE) {
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assert(NumParts > 0 && "No parts to assemble!");
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assert(NumParts > 0 && "No parts to assemble!");
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TargetLowering &TLI = DAG.getTargetLoweringInfo();
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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SDValue Val = Parts[0];
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SDValue Val = Parts[0];
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if (NumParts > 1) {
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if (NumParts > 1) {
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@ -525,7 +525,7 @@ static SDValue getCopyFromParts(SelectionDAG &DAG,
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static void getCopyToParts(SelectionDAG &DAG, SDValue Val,
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static void getCopyToParts(SelectionDAG &DAG, SDValue Val,
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SDValue *Parts, unsigned NumParts, MVT PartVT,
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SDValue *Parts, unsigned NumParts, MVT PartVT,
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ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
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ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
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TargetLowering &TLI = DAG.getTargetLoweringInfo();
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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MVT PtrVT = TLI.getPointerTy();
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MVT PtrVT = TLI.getPointerTy();
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MVT ValueVT = Val.getValueType();
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MVT ValueVT = Val.getValueType();
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unsigned PartBits = PartVT.getSizeInBits();
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unsigned PartBits = PartVT.getSizeInBits();
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@ -648,8 +648,7 @@ static void getCopyToParts(SelectionDAG &DAG, SDValue Val,
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// Handle a multi-element vector.
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// Handle a multi-element vector.
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MVT IntermediateVT, RegisterVT;
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MVT IntermediateVT, RegisterVT;
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unsigned NumIntermediates;
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unsigned NumIntermediates;
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unsigned NumRegs =
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unsigned NumRegs = TLI
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DAG.getTargetLoweringInfo()
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.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
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.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
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RegisterVT);
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RegisterVT);
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unsigned NumElements = ValueVT.getVectorNumElements();
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unsigned NumElements = ValueVT.getVectorNumElements();
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@ -4819,7 +4818,7 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
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/// processed uses a memory 'm' constraint.
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/// processed uses a memory 'm' constraint.
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static bool
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static bool
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hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
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hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
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TargetLowering &TLI) {
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const TargetLowering &TLI) {
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for (unsigned i = 0, e = CInfos.size(); i != e; ++i) {
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for (unsigned i = 0, e = CInfos.size(); i != e; ++i) {
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InlineAsm::ConstraintInfo &CI = CInfos[i];
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InlineAsm::ConstraintInfo &CI = CInfos[i];
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for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) {
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for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) {
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@ -141,8 +141,8 @@ namespace llvm {
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const TargetMachine *TM,
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const TargetMachine *TM,
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MachineBasicBlock *BB,
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MachineBasicBlock *BB,
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bool Fast) {
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bool Fast) {
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TargetLowering &TLI = IS->getTargetLowering();
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const TargetLowering &TLI = IS->getTargetLowering();
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if (Fast)
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if (Fast)
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return createFastDAGScheduler(IS, DAG, TM, BB, Fast);
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return createFastDAGScheduler(IS, DAG, TM, BB, Fast);
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if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
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if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
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@ -399,7 +399,7 @@ static bool IsPossiblyOverwrittenArgumentOfTailCall(SDValue Op,
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/// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the
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/// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the
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/// DAG and fixes their tailcall attribute operand.
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/// DAG and fixes their tailcall attribute operand.
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static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
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static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
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TargetLowering& TLI) {
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const TargetLowering& TLI) {
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SDNode * Ret = NULL;
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SDNode * Ret = NULL;
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SDValue Terminator = DAG.getRoot();
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SDValue Terminator = DAG.getRoot();
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