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More consts on TargetLowering references. 

llvm-svn: 62262
This commit is contained in:
Dan Gohman 2009-01-15 16:58:17 +00:00
parent 6be2939d5d
commit 91febd1330
4 changed files with 9 additions and 10 deletions
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2
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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@ -736,7 +736,7 @@ SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
static
SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
TargetLowering &TLI) {
const TargetLowering &TLI) {
int SVOffset = LD->getSrcValueOffset();
SDValue Chain = LD->getChain();
SDValue Ptr = LD->getBasePtr();

2
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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@ -4982,7 +4982,7 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
return "<<Unknown Machine Node>>";
}
if (G) {
TargetLowering &TLI = G->getTargetLoweringInfo();
const TargetLowering &TLI = G->getTargetLoweringInfo();
const char *Name = TLI.getTargetNodeName(getOpcode());
if (Name) return Name;
return "<<Unknown Target Node>>";

9
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
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@ -380,7 +380,7 @@ static SDValue getCopyFromParts(SelectionDAG &DAG,
MVT ValueVT,
ISD::NodeType AssertOp = ISD::DELETED_NODE) {
assert(NumParts > 0 && "No parts to assemble!");
TargetLowering &TLI = DAG.getTargetLoweringInfo();
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
SDValue Val = Parts[0];
if (NumParts > 1) {
@ -525,7 +525,7 @@ static SDValue getCopyFromParts(SelectionDAG &DAG,
static void getCopyToParts(SelectionDAG &DAG, SDValue Val,
SDValue *Parts, unsigned NumParts, MVT PartVT,
ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
TargetLowering &TLI = DAG.getTargetLoweringInfo();
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
MVT PtrVT = TLI.getPointerTy();
MVT ValueVT = Val.getValueType();
unsigned PartBits = PartVT.getSizeInBits();
@ -648,8 +648,7 @@ static void getCopyToParts(SelectionDAG &DAG, SDValue Val,
// Handle a multi-element vector.
MVT IntermediateVT, RegisterVT;
unsigned NumIntermediates;
unsigned NumRegs =
DAG.getTargetLoweringInfo()
unsigned NumRegs = TLI
.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
RegisterVT);
unsigned NumElements = ValueVT.getVectorNumElements();
@ -4819,7 +4818,7 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
/// processed uses a memory 'm' constraint.
static bool
hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
TargetLowering &TLI) {
const TargetLowering &TLI) {
for (unsigned i = 0, e = CInfos.size(); i != e; ++i) {
InlineAsm::ConstraintInfo &CI = CInfos[i];
for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) {

6
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -141,8 +141,8 @@ namespace llvm {
const TargetMachine *TM,
MachineBasicBlock *BB,
bool Fast) {
TargetLowering &TLI = IS->getTargetLowering();
const TargetLowering &TLI = IS->getTargetLowering();
if (Fast)
return createFastDAGScheduler(IS, DAG, TM, BB, Fast);
if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
@ -399,7 +399,7 @@ static bool IsPossiblyOverwrittenArgumentOfTailCall(SDValue Op,
/// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the
/// DAG and fixes their tailcall attribute operand.
static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
TargetLowering& TLI) {
const TargetLowering& TLI) {
SDNode * Ret = NULL;
SDValue Terminator = DAG.getRoot();