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Fix 80-column violations, trailing whitespace, comment text. 

llvm-svn: 222269
This commit is contained in:
Eric Christopher 2014-11-18 22:36:15 +00:00
parent 8be702dbaa
commit 917e952d2d
1 changed files with 74 additions and 63 deletions
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137
clang/lib/Basic/Targets.cpp
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@ -317,7 +317,8 @@ protected:
Builder.defineMacro("_GNU_SOURCE"); Builder.defineMacro("_GNU_SOURCE");
} }
public: public:
KFreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { KFreeBSDTargetInfo(const llvm::Triple &Triple)
: OSTargetInfo<Target>(Triple) {
this->UserLabelPrefix = ""; this->UserLabelPrefix = "";
} }
}; };
@ -639,7 +640,8 @@ public:
// RegParmMax is inherited from the underlying architecture // RegParmMax is inherited from the underlying architecture
this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
if (Triple.getArch() == llvm::Triple::arm) { if (Triple.getArch() == llvm::Triple::arm) {
this->DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"; this->DescriptionString =
"e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128";
} else if (Triple.getArch() == llvm::Triple::x86) { } else if (Triple.getArch() == llvm::Triple::x86) {
this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128";
} else if (Triple.getArch() == llvm::Triple::x86_64) { } else if (Triple.getArch() == llvm::Triple::x86_64) {
@ -920,7 +922,7 @@ const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
#include "clang/Basic/BuiltinsPPC.def" #include "clang/Basic/BuiltinsPPC.def"
}; };
/// handleTargetFeatures - Perform initialization based on the user /// handleTargetFeatures - Perform initialization based on the user
/// configured set of features. /// configured set of features.
bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
DiagnosticsEngine &Diags) { DiagnosticsEngine &Diags) {
@ -1144,7 +1146,6 @@ bool PPCTargetInfo::hasFeature(StringRef Feature) const {
.Default(false); .Default(false);
} }
const char * const PPCTargetInfo::GCCRegNames[] = { const char * const PPCTargetInfo::GCCRegNames[] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
@ -1340,7 +1341,7 @@ public:
: DarwinTargetInfo<PPC32TargetInfo>(Triple) { : DarwinTargetInfo<PPC32TargetInfo>(Triple) {
HasAlignMac68kSupport = true; HasAlignMac68kSupport = true;
BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
LongLongAlign = 32; LongLongAlign = 32;
SuitableAlign = 128; SuitableAlign = 128;
DescriptionString = "E-m:o-p:32:32-f64:32:64-n32"; DescriptionString = "E-m:o-p:32:32-f64:32:64-n32";
@ -1407,8 +1408,9 @@ namespace {
Aliases = nullptr; Aliases = nullptr;
NumAliases = 0; NumAliases = 0;
} }
bool validateAsmConstraint(const char *&Name, bool
TargetInfo::ConstraintInfo &Info) const override { validateAsmConstraint(const char *&Name,
TargetInfo::ConstraintInfo &Info) const override {
switch (*Name) { switch (*Name) {
default: return false; default: return false;
case 'c': case 'c':
@ -1721,7 +1723,8 @@ class X86TargetInfo : public TargetInfo {
bool HasTBM; bool HasTBM;
bool HasFMA; bool HasFMA;
bool HasF16C; bool HasF16C;
bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW, HasAVX512VL; bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW,
HasAVX512VL;
bool HasSHA; bool HasSHA;
bool HasCX16; bool HasCX16;
@ -1923,7 +1926,7 @@ public:
NumNames = llvm::array_lengthof(AddlRegNames); NumNames = llvm::array_lengthof(AddlRegNames);
} }
bool validateAsmConstraint(const char *&Name, bool validateAsmConstraint(const char *&Name,
TargetInfo::ConstraintInfo &info) const override; TargetInfo::ConstraintInfo &info) const override;
bool validateOutputSize(StringRef Constraint, unsigned Size) const override; bool validateOutputSize(StringRef Constraint, unsigned Size) const override;
@ -2353,8 +2356,9 @@ void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
case AVX2: case AVX2:
Features["avx2"] = false; Features["avx2"] = false;
case AVX512F: case AVX512F:
Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = Features["avx512pf"] = Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
Features["avx512dq"] = Features["avx512bw"] = Features["avx512vl"] = false; Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
Features["avx512vl"] = false;
} }
} }
@ -3443,9 +3447,10 @@ public:
Int64Type = IsX32 ? SignedLongLong : SignedLong; Int64Type = IsX32 ? SignedLongLong : SignedLong;
RegParmMax = 6; RegParmMax = 6;
// Pointers are 32-bit in x32.
DescriptionString = (IsX32) DescriptionString = (IsX32)
? "e-m:e-" "p:32:32-" "i64:64-f80:128-n8:16:32:64-S128" ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128"
: "e-m:e-" "i64:64-f80:128-n8:16:32:64-S128"; : "e-m:e-i64:64-f80:128-n8:16:32:64-S128";
// Use fpret only for long double. // Use fpret only for long double.
RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
@ -3808,8 +3813,8 @@ public:
MaxAtomicInlineWidth = 64; MaxAtomicInlineWidth = 64;
// Do force alignment of members that follow zero length bitfields. If // Do force alignment of members that follow zero length bitfields. If
// the alignment of the zero-length bitfield is greater than the member // the alignment of the zero-length bitfield is greater than the member
// that follows it, `bar', `bar' will be aligned as the type of the // that follows it, `bar', `bar' will be aligned as the type of the
// zero length bitfield. // zero length bitfield.
UseZeroLengthBitfieldAlignment = true; UseZeroLengthBitfieldAlignment = true;
} }
@ -3955,40 +3960,43 @@ public:
} }
// FIXME: Should we actually have some table instead of these switches? // FIXME: Should we actually have some table instead of these switches?
static const char *getCPUDefineSuffix(StringRef Name) { static const char *getCPUDefineSuffix(StringRef Name) {
return llvm::StringSwitch<const char*>(Name) return llvm::StringSwitch<const char *>(Name)
.Cases("arm8", "arm810", "4") .Cases("arm8", "arm810", "4")
.Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4") .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110",
.Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T") "4")
.Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T") .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T")
.Case("ep9312", "4T") .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T")
.Cases("arm10tdmi", "arm1020t", "5T") .Case("ep9312", "4T")
.Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE") .Cases("arm10tdmi", "arm1020t", "5T")
.Case("arm926ej-s", "5TEJ") .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE")
.Cases("arm10e", "arm1020e", "arm1022e", "5TE") .Case("arm926ej-s", "5TEJ")
.Cases("xscale", "iwmmxt", "5TE") .Cases("arm10e", "arm1020e", "arm1022e", "5TE")
.Case("arm1136j-s", "6J") .Cases("xscale", "iwmmxt", "5TE")
.Cases("arm1176jz-s", "arm1176jzf-s", "6ZK") .Case("arm1136j-s", "6J")
.Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K") .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK")
.Cases("arm1156t2-s", "arm1156t2f-s", "6T2") .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K")
.Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A") .Cases("arm1156t2-s", "arm1156t2f-s", "6T2")
.Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait", "7A") .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A")
.Cases("cortex-r4", "cortex-r5", "7R") .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait",
.Case("swift", "7S") "7A")
.Case("cyclone", "8A") .Cases("cortex-r4", "cortex-r5", "7R")
.Case("cortex-m3", "7M") .Case("swift", "7S")
.Cases("cortex-m4", "cortex-m7", "7EM") .Case("cyclone", "8A")
.Case("cortex-m0", "6M") .Case("cortex-m3", "7M")
.Cases("cortex-a53", "cortex-a57", "8A") .Cases("cortex-m4", "cortex-m7", "7EM")
.Default(nullptr); .Case("cortex-m0", "6M")
.Cases("cortex-a53", "cortex-a57", "8A")
.Default(nullptr);
} }
static const char *getCPUProfile(StringRef Name) { static const char *getCPUProfile(StringRef Name) {
return llvm::StringSwitch<const char*>(Name) return llvm::StringSwitch<const char *>(Name)
.Cases("cortex-a5", "cortex-a7", "cortex-a8", "A") .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A")
.Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait", "A") .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait",
.Cases("cortex-a53", "cortex-a57", "A") "A")
.Cases("cortex-m3", "cortex-m4", "cortex-m0", "cortex-m7", "M") .Cases("cortex-a53", "cortex-a57", "A")
.Cases("cortex-r4", "cortex-r5", "R") .Cases("cortex-m3", "cortex-m4", "cortex-m0", "cortex-m7", "M")
.Default(""); .Cases("cortex-r4", "cortex-r5", "R")
.Default("");
} }
bool setCPU(const std::string &Name) override { bool setCPU(const std::string &Name) override {
if (!getCPUDefineSuffix(Name)) if (!getCPUDefineSuffix(Name))
@ -4038,9 +4046,9 @@ public:
// __ARM_ARCH is defined as an integer value indicating the current ARM ISA // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1)); Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
if (CPUArch[0] >= '8') { if (CPUArch[0] >= '8') {
Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN"); Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING"); Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
} }
// __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It
@ -4438,7 +4446,8 @@ public:
: DarwinTargetInfo<ARMleTargetInfo>(Triple) { : DarwinTargetInfo<ARMleTargetInfo>(Triple) {
HasAlignMac68kSupport = true; HasAlignMac68kSupport = true;
// iOS always has 64-bit atomic instructions. // iOS always has 64-bit atomic instructions.
// FIXME: This should be based off of the target features in ARMleTargetInfo. // FIXME: This should be based off of the target features in
// ARMleTargetInfo.
MaxAtomicInlineWidth = 64; MaxAtomicInlineWidth = 64;
// Darwin on iOS uses a variant of the ARM C++ ABI. // Darwin on iOS uses a variant of the ARM C++ ABI.
@ -4621,8 +4630,9 @@ public:
virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
unsigned &NumAliases) const override; unsigned &NumAliases) const override;
virtual bool validateAsmConstraint(const char *&Name, virtual bool
TargetInfo::ConstraintInfo &Info) const override { validateAsmConstraint(const char *&Name,
TargetInfo::ConstraintInfo &Info) const override {
switch (*Name) { switch (*Name) {
default: default:
return false; return false;
@ -4645,11 +4655,11 @@ public:
Info.setAllowsRegister(); Info.setAllowsRegister();
return true; return true;
case 'U': case 'U':
// Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
// Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be // Utf: A memory address suitable for ldp/stp in TF mode.
// Usa: An absolute symbolic address // Usa: An absolute symbolic address.
// Ush: The high part (bits 32:12) of a pc-relative symbolic address // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
llvm_unreachable("FIXME: Unimplemented support for bizarre constraints"); llvm_unreachable("FIXME: Unimplemented support for U* constraints.");
case 'z': // Zero register, wzr or xzr case 'z': // Zero register, wzr or xzr
Info.setAllowsRegister(); Info.setAllowsRegister();
return true; return true;
@ -5322,8 +5332,9 @@ namespace {
Aliases = nullptr; Aliases = nullptr;
NumAliases = 0; NumAliases = 0;
} }
bool validateAsmConstraint(const char *&Name, bool
TargetInfo::ConstraintInfo &info) const override { validateAsmConstraint(const char *&Name,
TargetInfo::ConstraintInfo &info) const override {
// No target constraints for now. // No target constraints for now.
return false; return false;
} }
@ -5609,7 +5620,6 @@ public:
switch (*Name) { switch (*Name) {
default: default:
return false; return false;
case 'r': // CPU registers. case 'r': // CPU registers.
case 'd': // Equivalent to "r" unless generating MIPS16 code. case 'd': // Equivalent to "r" unless generating MIPS16 code.
case 'y': // Equivalent to "r", backward compatibility only. case 'y': // Equivalent to "r", backward compatibility only.
@ -6122,8 +6132,9 @@ namespace {
} }
void getGCCRegNames(const char * const *&Names, void getGCCRegNames(const char * const *&Names,
unsigned &NumNames) const override {} unsigned &NumNames) const override {}
bool validateAsmConstraint(const char *&Name, bool
TargetInfo::ConstraintInfo &info) const override { validateAsmConstraint(const char *&Name,
TargetInfo::ConstraintInfo &info) const override {
return true; return true;
} }
void getGCCRegAliases(const GCCRegAlias *&Aliases, void getGCCRegAliases(const GCCRegAlias *&Aliases,