[AArch64] Add command-line option for SB
SB (Speculative Barrier) is only mandatory from 8.5 onwards but is optional from Armv8.0-A. This patch adds a command line option to enable SB, as it was previously only possible to enable by selecting -march=armv8.5-a. This patch also moves to FeatureSB the old FeatureSpecRestrict. Reviewers: pbarrio, olista01, t.p.northover, LukeCheeseman Differential Revision: https://reviews.llvm.org/D55921 llvm-svn: 350126
This commit is contained in:
Diogo N. Sampaio
parent
d5b685a9b2
commit
9123f82cc4
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@ -73,6 +73,7 @@ AARCH64_ARCH_EXT_NAME("rcpc", AArch64::AEK_RCPC, "+rcpc", "-rcpc")
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AARCH64_ARCH_EXT_NAME("rng", AArch64::AEK_RAND, "+rand", "-rand")
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AARCH64_ARCH_EXT_NAME("memtag", AArch64::AEK_MTE, "+mte", "-mte")
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AARCH64_ARCH_EXT_NAME("ssbs", AArch64::AEK_SSBS, "+ssbs", "-ssbs")
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AARCH64_ARCH_EXT_NAME("sb", AArch64::AEK_SB, "+sb", "-sb")
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#undef AARCH64_ARCH_EXT_NAME
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#ifndef AARCH64_CPU_NAME
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@ -48,6 +48,7 @@ enum ArchExtKind : unsigned {
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AEK_RAND = 1 << 18,
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AEK_MTE = 1 << 19,
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AEK_SSBS = 1 << 20,
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AEK_SB = 1 << 21,
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};
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enum class ArchKind {
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@ -306,12 +306,12 @@ def FeatureFRInt3264 : SubtargetFeature<"fptoint", "HasFRInt3264", "true",
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def FeatureSpecRestrict : SubtargetFeature<"specrestrict", "HasSpecRestrict",
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"true", "Enable architectural speculation restriction" >;
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def FeatureSB : SubtargetFeature<"sb", "HasSB",
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"true", "Enable v8.5 Speculation Barrier" >;
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def FeatureSSBS : SubtargetFeature<"ssbs", "HasSSBS",
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"true", "Enable Speculative Store Bypass Safe bit" >;
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def FeatureSpecCtrl : SubtargetFeature<"specctrl", "HasSpecCtrl", "true",
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"Enable speculation control barrier" >;
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def FeaturePredCtrl : SubtargetFeature<"predctrl", "HasPredCtrl", "true",
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"Enable execution and data prediction invalidation instructions" >;
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@ -352,7 +352,7 @@ def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true",
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def HasV8_5aOps : SubtargetFeature<
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"v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions",
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[HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict,
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FeatureSSBS, FeatureSpecCtrl, FeaturePredCtrl, FeatureCacheDeepPersist,
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FeatureSSBS, FeatureSB, FeaturePredCtrl, FeatureCacheDeepPersist,
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FeatureBranchTargetId]
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>;
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@ -114,8 +114,8 @@ def HasAltNZCV : Predicate<"Subtarget->hasAlternativeNZCV()">,
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AssemblerPredicate<"FeatureAltFPCmp", "altnzcv">;
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def HasFRInt3264 : Predicate<"Subtarget->hasFRInt3264()">,
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AssemblerPredicate<"FeatureFRInt3264", "frint3264">;
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def HasSpecCtrl : Predicate<"Subtarget->hasSpecCtrl()">,
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AssemblerPredicate<"FeatureSpecCtrl", "specctrl">;
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def HasSB : Predicate<"Subtarget->hasSB()">,
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AssemblerPredicate<"FeatureSB", "sb">;
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def HasPredCtrl : Predicate<"Subtarget->hasPredCtrl()">,
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AssemblerPredicate<"FeaturePredCtrl", "predctrl">;
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def HasCCDP : Predicate<"Subtarget->hasCCDP()">,
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@ -733,7 +733,7 @@ def AXFLAG : PstateWriteSimple<(ins), "axflag", "">, Sched<[WriteSys]> {
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def SB : SimpleSystemI<0, (ins), "sb", "">, Sched<[]> {
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let Inst{20-5} = 0b0001100110000111;
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let Unpredictable{11-8} = 0b1111;
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let Predicates = [HasSpecCtrl];
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let Predicates = [HasSB];
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let hasSideEffects = 1;
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}
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@ -126,8 +126,8 @@ protected:
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bool HasAlternativeNZCV = false;
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bool HasFRInt3264 = false;
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bool HasSpecRestrict = false;
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bool HasSpecCtrl = false;
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bool HasSSBS = false;
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bool HasSB = false;
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bool HasPredCtrl = false;
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bool HasCCDP = false;
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bool HasBTI = false;
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@ -355,8 +355,8 @@ public:
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bool hasAlternativeNZCV() const { return HasAlternativeNZCV; }
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bool hasFRInt3264() const { return HasFRInt3264; }
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bool hasSpecRestrict() const { return HasSpecRestrict; }
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bool hasSpecCtrl() const { return HasSpecCtrl; }
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bool hasSSBS() const { return HasSSBS; }
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bool hasSB() const { return HasSB; }
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bool hasPredCtrl() const { return HasPredCtrl; }
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bool hasCCDP() const { return HasCCDP; }
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bool hasBTI() const { return HasBTI; }
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@ -1,11 +1,11 @@
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// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+specctrl < %s | FileCheck %s
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// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.5a < %s | FileCheck %s
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// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-specctrl < %s 2>&1 | FileCheck %s --check-prefix=NOSB
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// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+sb -o - %s | FileCheck %s
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// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.5a -o - %s | FileCheck %s
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// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-sb -o - %s 2>&1 | FileCheck %s --check-prefix=NOSB
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// Flag manipulation
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sb
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// CHECK: sb // encoding: [0xff,0x30,0x03,0xd5]
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// NOSB: instruction requires: specctrl
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// NOSB: instruction requires: sb
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// NOSB-NEXT: sb
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@ -0,0 +1,9 @@
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# RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+sb -disassemble < %s | FileCheck %s
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# RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+v8.5a -disassemble < %s | FileCheck %s
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# RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=-sb -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOSB
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# New reg
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0xff 0x30 0x03 0xd5
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# CHECK: sb
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# NOSB: msr S0_3_C3_C0_7, xzr
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@ -1,9 +0,0 @@
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# RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+specctrl -disassemble < %s | FileCheck %s
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# RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+v8.5a -disassemble < %s | FileCheck %s
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# RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=-specctrl -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOSB
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# New reg
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0xff 0x30 0x03 0xd5
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# CHECK: sb
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# NOSB: msr S0_3_C3_C0_7, xzr
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@ -988,7 +988,8 @@ TEST(TargetParserTest, AArch64ArchExtFeature) {
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{"rcpc", "norcpc", "+rcpc", "-rcpc" },
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{"rng", "norng", "+rand", "-rand"},
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{"memtag", "nomemtag", "+mte", "-mte"},
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{"ssbs", "nossbs", "+ssbs", "-ssbs"}};
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{"ssbs", "nossbs", "+ssbs", "-ssbs"},
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{"sb", "nosb", "+sb", "-sb"}};
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for (unsigned i = 0; i < array_lengthof(ArchExt); i++) {
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EXPECT_EQ(StringRef(ArchExt[i][2]),
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