Add callback to allow target to adjust latency of schedule dependency edge.

llvm-svn: 78910

llvm/include/llvm/CodeGen/ScheduleDAG.h

@@ -145,6 +145,11 @@ namespace llvm {
       return Latency;
     }
 
+    /// setLatency - Set the latency for this edge.
+    void setLatency(unsigned Lat) {
+      Latency = Lat;
+    }
+
     //// getSUnit - Return the SUnit to which this edge points.
     SUnit *getSUnit() const {
       return Dep.getPointer();

llvm/include/llvm/Target/TargetSubtarget.h

@@ -16,6 +16,8 @@
 
 namespace llvm {
 
+class SDep;
+
 //===----------------------------------------------------------------------===//
 ///
 /// TargetSubtarget - Generic base class for all target subtargets.  All
@@ -35,6 +37,10 @@ public:
   /// indicating the number of scheduling cycles of backscheduling that
   /// should be attempted.
   virtual unsigned getSpecialAddressLatency() const { return 0; }
+
+  // adjustSchedDependency - Perform target specific adjustments to
+  // the latency of a schedule dependency.
+  virtual void adjustSchedDependency(SDep&) const { };
 };
 
 } // End llvm namespace

llvm/lib/CodeGen/ScheduleDAGInstrs.cpp

@@ -145,8 +145,8 @@ void ScheduleDAGInstrs::BuildSchedGraph() {
   bool UnitLatencies = ForceUnitLatencies();
 
   // Ask the target if address-backscheduling is desirable, and if so how much.
-  unsigned SpecialAddressLatency =
+  const TargetSubtarget &ST = TM.getSubtarget<TargetSubtarget>();
-    TM.getSubtarget<TargetSubtarget>().getSpecialAddressLatency();
+  unsigned SpecialAddressLatency = ST.getSpecialAddressLatency();
 
   // Walk the list of instructions, from bottom moving up.
   for (MachineBasicBlock::iterator MII = InsertPos, MIE = Begin;
@@ -220,15 +220,20 @@ void ScheduleDAGInstrs::BuildSchedGraph() {
                   UseTID.OpInfo[RegUseIndex].isLookupPtrRegClass())
                 LDataLatency += SpecialAddressLatency;
             }
-            UseSU->addPred(SDep(SU, SDep::Data, LDataLatency, Reg));
+            const SDep& dep = SDep(SU, SDep::Data, LDataLatency, Reg);
+            ST.adjustSchedDependency((SDep &)dep);
+            UseSU->addPred(dep);
           }
         }
         for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
           std::vector<SUnit *> &UseList = Uses[*Alias];
           for (unsigned i = 0, e = UseList.size(); i != e; ++i) {
             SUnit *UseSU = UseList[i];
-            if (UseSU != SU)
+            if (UseSU != SU) {
-              UseSU->addPred(SDep(SU, SDep::Data, DataLatency, *Alias));
+              const SDep& dep = SDep(SU, SDep::Data, DataLatency, *Alias);
+              ST.adjustSchedDependency((SDep &)dep);
+              UseSU->addPred(dep);
+            }
           }
         }
 

llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp

@@ -18,6 +18,7 @@
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/Target/TargetSubtarget.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 using namespace llvm;
@@ -152,6 +153,8 @@ void ScheduleDAGSDNodes::BuildSchedUnits() {
 }
 
 void ScheduleDAGSDNodes::AddSchedEdges() {
+  const TargetSubtarget &ST = TM.getSubtarget<TargetSubtarget>();
+
   // Pass 2: add the preds, succs, etc.
   for (unsigned su = 0, e = SUnits.size(); su != e; ++su) {
     SUnit *SU = &SUnits[su];
@@ -206,8 +209,13 @@ void ScheduleDAGSDNodes::AddSchedEdges() {
         // dependency. This may change in the future though.
         if (Cost >= 0)
           PhysReg = 0;
-        SU->addPred(SDep(OpSU, isChain ? SDep::Order : SDep::Data,
+
-                         OpSU->Latency, PhysReg));
+        const SDep& dep = SDep(OpSU, isChain ? SDep::Order : SDep::Data,
+                               OpSU->Latency, PhysReg);
+        if (!isChain)
+          ST.adjustSchedDependency((SDep &)dep);
+
+        SU->addPred(dep);
       }
     }
   }