From 9062b75a930c74a091dd974401bc783a48ba98b3 Mon Sep 17 00:00:00 2001
From: Krzysztof Parzyszek <kparzysz@codeaurora.org>
Date: Fri, 22 Apr 2016 16:47:01 +0000
Subject: [PATCH] [Hexagon] Teach mux expansion how to deal with undef
 predicates

llvm-svn: 267165
---
 .../Target/Hexagon/HexagonExpandCondsets.cpp  | 18 ++++++++++-----
 .../Hexagon/expand-condsets-pred-undef.ll     | 22 +++++++++++++++++++
 2 files changed, 35 insertions(+), 5 deletions(-)
 create mode 100644 llvm/test/CodeGen/Hexagon/expand-condsets-pred-undef.ll

diff --git a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
index 6b66ee2cef6e..35185ef2a4c8 100644
--- a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
@@ -110,6 +110,7 @@ namespace {
       AU.addRequired<LiveIntervals>();
       AU.addPreserved<LiveIntervals>();
       AU.addPreserved<SlotIndexes>();
+      AU.addPreservedID(MachineDominatorsID);
       MachineFunctionPass::getAnalysisUsage(AU);
     }
     virtual bool runOnMachineFunction(MachineFunction &MF);
@@ -166,7 +167,8 @@ namespace {
     bool canMoveOver(MachineInstr *MI, ReferenceMap &Defs, ReferenceMap &Uses);
     bool canMoveMemTo(MachineInstr *MI, MachineInstr *ToI, bool IsDown);
     void predicateAt(RegisterRef RD, MachineInstr *MI,
-        MachineBasicBlock::iterator Where, unsigned PredR, bool Cond);
+        MachineBasicBlock::iterator Where, unsigned PredR, bool Cond,
+        bool PredUndef);
     void renameInRange(RegisterRef RO, RegisterRef RN, unsigned PredR,
         bool Cond, MachineBasicBlock::iterator First,
         MachineBasicBlock::iterator Last);
@@ -884,7 +886,8 @@ bool HexagonExpandCondsets::canMoveMemTo(MachineInstr *TheI, MachineInstr *ToI,
 /// Generate a predicated version of MI (where the condition is given via
 /// PredR and Cond) at the point indicated by Where.
 void HexagonExpandCondsets::predicateAt(RegisterRef RD, MachineInstr *MI,
-      MachineBasicBlock::iterator Where, unsigned PredR, bool Cond) {
+      MachineBasicBlock::iterator Where, unsigned PredR, bool Cond,
+      bool PredUndef) {
   // The problem with updating live intervals is that we can move one def
   // past another def. In particular, this can happen when moving an A2_tfrt
   // over an A2_tfrf defining the same register. From the point of view of
@@ -912,7 +915,7 @@ void HexagonExpandCondsets::predicateAt(RegisterRef RD, MachineInstr *MI,
   // Add the new def, then the predicate register, then the rest of the
   // operands.
   MB.addReg(RD.Reg, RegState::Define, RD.Sub);
-  MB.addReg(PredR);
+  MB.addReg(PredR, PredUndef ? RegState::Undef : 0);
   while (Ox < NP) {
     MachineOperand &MO = MI->getOperand(Ox);
     if (!MO.isReg() || !MO.isImplicit())
@@ -1070,9 +1073,9 @@ bool HexagonExpandCondsets::predicate(MachineInstr *TfrI, bool Cond) {
                << ", can move down: " << (CanDown ? "yes\n" : "no\n"));
   MachineBasicBlock::iterator PastDefIt = std::next(DefIt);
   if (CanUp)
-    predicateAt(RD, DefI, PastDefIt, PredR, Cond);
+    predicateAt(RD, DefI, PastDefIt, PredR, Cond, MP.isUndef());
   else if (CanDown)
-    predicateAt(RD, DefI, TfrIt, PredR, Cond);
+    predicateAt(RD, DefI, TfrIt, PredR, Cond, MP.isUndef());
   else
     return false;
 
@@ -1308,6 +1311,7 @@ bool HexagonExpandCondsets::runOnMachineFunction(MachineFunction &MF) {
   TRI = MF.getSubtarget().getRegisterInfo();
   LIS = &getAnalysis<LiveIntervals>();
   MRI = &MF.getRegInfo();
+  DEBUG(MF.print(dbgs() << "Before expand-condsets\n", LIS->getSlotIndexes()));
 
   bool Changed = false;
 
@@ -1330,6 +1334,10 @@ bool HexagonExpandCondsets::runOnMachineFunction(MachineFunction &MF) {
 
   for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
     postprocessUndefImplicitUses(*I);
+
+  if (Changed)
+    DEBUG(MF.print(dbgs() << "After expand-condsets\n", LIS->getSlotIndexes()));
+
   return Changed;
 }
 
diff --git a/llvm/test/CodeGen/Hexagon/expand-condsets-pred-undef.ll b/llvm/test/CodeGen/Hexagon/expand-condsets-pred-undef.ll
new file mode 100644
index 000000000000..284170b5edb4
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/expand-condsets-pred-undef.ll
@@ -0,0 +1,22 @@
+; RUN: llc -march=hexagon < %s
+; REQUIRES: asserts
+
+target triple = "hexagon"
+
+%struct.0 = type { i64, i16 }
+
+declare void @foo(%struct.0* noalias nocapture sret, i8 zeroext, i32, i64) #0
+
+define hidden fastcc void @fred(%struct.0* noalias nocapture %p, i8 zeroext %t, i32 %r) unnamed_addr #0 {
+entry:
+  %. = select i1 undef, i64 549755813888, i64 1024
+  %cmp104 = icmp ult i64 undef, %.
+  %inc = zext i1 %cmp104 to i32
+  %inc.r = add nsw i32 %inc, %r
+  %.inc.r = select i1 undef, i32 0, i32 %inc.r
+  tail call void @foo(%struct.0* sret %p, i8 zeroext %t, i32 %.inc.r, i64 undef)
+  ret void
+}
+
+attributes #0 = { noinline nounwind }
+