[AMDGPU] DAG combine to produce V_PERM_B32
Differential Revision: https://reviews.llvm.org/D48099 llvm-svn: 334559
This commit is contained in:
Stanislav Mekhanoshin
parent
fa60e6966c
commit
8fd3c4e431
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@ -4119,6 +4119,7 @@ const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
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NODE_NAME_CASE(MAD_I24)
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NODE_NAME_CASE(MAD_I64_I32)
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NODE_NAME_CASE(MAD_U64_U32)
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NODE_NAME_CASE(PERM)
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NODE_NAME_CASE(TEXTURE_FETCH)
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NODE_NAME_CASE(EXPORT)
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NODE_NAME_CASE(EXPORT_DONE)
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@ -4374,6 +4375,34 @@ void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
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Known.Zero.setHighBits(32 - MaxValBits);
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break;
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}
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case AMDGPUISD::PERM: {
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ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(Op.getOperand(2));
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if (!CMask)
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return;
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KnownBits LHSKnown, RHSKnown;
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DAG.computeKnownBits(Op.getOperand(0), LHSKnown, Depth + 1);
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DAG.computeKnownBits(Op.getOperand(1), RHSKnown, Depth + 1);
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unsigned Sel = CMask->getZExtValue();
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for (unsigned I = 0; I < 32; I += 8) {
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unsigned ByteMask = 0xff << I;
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unsigned SelBits = Sel & 0xff;
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if (SelBits < 4) {
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Known.One |= RHSKnown.One & ByteMask;
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Known.Zero |= RHSKnown.Zero & ByteMask;
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} else if (SelBits < 7) {
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Known.One |= LHSKnown.One & ByteMask;
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Known.Zero |= LHSKnown.Zero & ByteMask;
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} else if (SelBits == 0x0c) {
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Known.Zero |= ByteMask;
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} else if (SelBits > 0x0c) {
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Known.One |= ByteMask;
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}
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Sel >>= 8;
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}
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break;
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}
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case ISD::INTRINSIC_WO_CHAIN: {
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unsigned IID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
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switch (IID) {
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@ -402,6 +402,7 @@ enum NodeType : unsigned {
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MAD_I64_I32,
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MUL_LOHI_I24,
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MUL_LOHI_U24,
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PERM,
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TEXTURE_FETCH,
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EXPORT, // exp on SI+
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EXPORT_DONE, // exp on SI+ with done bit set
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@ -339,6 +339,8 @@ def AMDGPUumed3 : SDNode<"AMDGPUISD::UMED3", AMDGPUDTIntTernaryOp,
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def AMDGPUfmed3 : SDNode<"AMDGPUISD::FMED3", SDTFPTernaryOp, []>;
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def AMDGPUperm : SDNode<"AMDGPUISD::PERM", AMDGPUDTIntTernaryOp, []>;
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def AMDGPUinit_exec : SDNode<"AMDGPUISD::INIT_EXEC",
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SDTypeProfile<0, 1, [SDTCisInt<0>]>,
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[SDNPHasChain, SDNPInGlue]>;
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@ -6135,6 +6135,71 @@ static bool isBoolSGPR(SDValue V) {
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return false;
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}
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// If a constant has all zeroes or all ones within each byte return it.
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// Otherwise return 0.
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static uint32_t getConstantPermuteMask(uint32_t C) {
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// 0xff for any zero byte in the mask
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uint32_t ZeroByteMask = 0;
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if (!(C & 0x000000ff)) ZeroByteMask |= 0x000000ff;
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if (!(C & 0x0000ff00)) ZeroByteMask |= 0x0000ff00;
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if (!(C & 0x00ff0000)) ZeroByteMask |= 0x00ff0000;
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if (!(C & 0xff000000)) ZeroByteMask |= 0xff000000;
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uint32_t NonZeroByteMask = ~ZeroByteMask; // 0xff for any non-zero byte
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if ((NonZeroByteMask & C) != NonZeroByteMask)
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return 0; // Partial bytes selected.
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return C;
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}
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// Check if a node selects whole bytes from its operand 0 starting at a byte
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// boundary while masking the rest. Returns select mask as in the v_perm_b32
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// or -1 if not succeeded.
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// Note byte select encoding:
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// value 0-3 selects corresponding source byte;
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// value 0xc selects zero;
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// value 0xff selects 0xff.
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static uint32_t getPermuteMask(SelectionDAG &DAG, SDValue V) {
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assert(V.getValueSizeInBits() == 32);
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if (V.getNumOperands() != 2)
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return ~0;
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ConstantSDNode *N1 = dyn_cast<ConstantSDNode>(V.getOperand(1));
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if (!N1)
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return ~0;
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uint32_t C = N1->getZExtValue();
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switch (V.getOpcode()) {
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default:
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break;
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case ISD::AND:
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if (uint32_t ConstMask = getConstantPermuteMask(C)) {
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return (0x03020100 & ConstMask) | (0x0c0c0c0c & ~ConstMask);
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}
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break;
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case ISD::OR:
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if (uint32_t ConstMask = getConstantPermuteMask(C)) {
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return (0x03020100 & ~ConstMask) | ConstMask;
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}
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break;
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case ISD::SHL:
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if (C % 8)
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return ~0;
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return uint32_t((0x030201000c0c0c0cull << C) >> 32);
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case ISD::SRL:
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if (C % 8)
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return ~0;
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return uint32_t(0x0c0c0c0c03020100ull >> C);
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}
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return ~0;
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}
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SDValue SITargetLowering::performAndCombine(SDNode *N,
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DAGCombinerInfo &DCI) const {
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if (DCI.isBeforeLegalize())
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@ -6181,6 +6246,20 @@ SDValue SITargetLowering::performAndCombine(SDNode *N,
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}
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}
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}
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// and (perm x, y, c1), c2 -> perm x, y, permute_mask(c1, c2)
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if (LHS.hasOneUse() && LHS.getOpcode() == AMDGPUISD::PERM &&
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isa<ConstantSDNode>(LHS.getOperand(2))) {
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uint32_t Sel = getConstantPermuteMask(Mask);
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if (!Sel)
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return SDValue();
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// Select 0xc for all zero bytes
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Sel = (LHS.getConstantOperandVal(2) & Sel) | (~Sel & 0x0c0c0c0c);
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SDLoc DL(N);
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return DAG.getNode(AMDGPUISD::PERM, DL, MVT::i32, LHS.getOperand(0),
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LHS.getOperand(1), DAG.getConstant(Sel, DL, MVT::i32));
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}
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}
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// (and (fcmp ord x, x), (fcmp une (fabs x), inf)) ->
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@ -6233,6 +6312,54 @@ SDValue SITargetLowering::performAndCombine(SDNode *N,
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LHS, DAG.getConstant(0, SDLoc(N), MVT::i32));
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}
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// and (op x, c1), (op y, c2) -> perm x, y, permute_mask(c1, c2)
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const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
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if (VT == MVT::i32 && LHS.hasOneUse() && RHS.hasOneUse() &&
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N->isDivergent() && TII->pseudoToMCOpcode(AMDGPU::V_PERM_B32) != -1) {
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uint32_t LHSMask = getPermuteMask(DAG, LHS);
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uint32_t RHSMask = getPermuteMask(DAG, RHS);
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if (LHSMask != ~0u && RHSMask != ~0u) {
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// Canonicalize the expression in an attempt to have fewer unique masks
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// and therefore fewer registers used to hold the masks.
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if (LHSMask > RHSMask) {
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std::swap(LHSMask, RHSMask);
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std::swap(LHS, RHS);
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}
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// Select 0xc for each lane used from source operand. Zero has 0xc mask
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// set, 0xff have 0xff in the mask, actual lanes are in the 0-3 range.
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uint32_t LHSUsedLanes = ~(LHSMask & 0x0c0c0c0c) & 0x0c0c0c0c;
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uint32_t RHSUsedLanes = ~(RHSMask & 0x0c0c0c0c) & 0x0c0c0c0c;
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// Check of we need to combine values from two sources within a byte.
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if (!(LHSUsedLanes & RHSUsedLanes) &&
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// If we select high and lower word keep it for SDWA.
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// TODO: teach SDWA to work with v_perm_b32 and remove the check.
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!(LHSUsedLanes == 0x0c0c0000 && RHSUsedLanes == 0x00000c0c)) {
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// Each byte in each mask is either selector mask 0-3, or has higher
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// bits set in either of masks, which can be 0xff for 0xff or 0x0c for
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// zero. If 0x0c is in either mask it shall always be 0x0c. Otherwise
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// mask which is not 0xff wins. By anding both masks we have a correct
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// result except that 0x0c shall be corrected to give 0x0c only.
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uint32_t Mask = LHSMask & RHSMask;
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for (unsigned I = 0; I < 32; I += 8) {
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uint32_t ByteSel = 0xff << I;
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if ((LHSMask & ByteSel) == 0x0c || (RHSMask & ByteSel) == 0x0c)
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Mask &= (0x0c << I) & 0xffffffff;
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}
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// Add 4 to each active LHS lane. It will not affect any existing 0xff
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// or 0x0c.
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uint32_t Sel = Mask | (LHSUsedLanes & 0x04040404);
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SDLoc DL(N);
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return DAG.getNode(AMDGPUISD::PERM, DL, MVT::i32,
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LHS.getOperand(0), RHS.getOperand(0),
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DAG.getConstant(Sel, DL, MVT::i32));
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}
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}
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}
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return SDValue();
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}
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@ -6268,6 +6395,60 @@ SDValue SITargetLowering::performOrCombine(SDNode *N,
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return SDValue();
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}
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// or (perm x, y, c1), c2 -> perm x, y, permute_mask(c1, c2)
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if (isa<ConstantSDNode>(RHS) && LHS.hasOneUse() &&
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LHS.getOpcode() == AMDGPUISD::PERM &&
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isa<ConstantSDNode>(LHS.getOperand(2))) {
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uint32_t Sel = getConstantPermuteMask(N->getConstantOperandVal(1));
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if (!Sel)
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return SDValue();
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Sel |= LHS.getConstantOperandVal(2);
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SDLoc DL(N);
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return DAG.getNode(AMDGPUISD::PERM, DL, MVT::i32, LHS.getOperand(0),
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LHS.getOperand(1), DAG.getConstant(Sel, DL, MVT::i32));
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}
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// or (op x, c1), (op y, c2) -> perm x, y, permute_mask(c1, c2)
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const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
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if (VT == MVT::i32 && LHS.hasOneUse() && RHS.hasOneUse() &&
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N->isDivergent() && TII->pseudoToMCOpcode(AMDGPU::V_PERM_B32) != -1) {
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uint32_t LHSMask = getPermuteMask(DAG, LHS);
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uint32_t RHSMask = getPermuteMask(DAG, RHS);
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if (LHSMask != ~0u && RHSMask != ~0u) {
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// Canonicalize the expression in an attempt to have fewer unique masks
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// and therefore fewer registers used to hold the masks.
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if (LHSMask > RHSMask) {
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std::swap(LHSMask, RHSMask);
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std::swap(LHS, RHS);
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}
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// Select 0xc for each lane used from source operand. Zero has 0xc mask
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// set, 0xff have 0xff in the mask, actual lanes are in the 0-3 range.
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uint32_t LHSUsedLanes = ~(LHSMask & 0x0c0c0c0c) & 0x0c0c0c0c;
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uint32_t RHSUsedLanes = ~(RHSMask & 0x0c0c0c0c) & 0x0c0c0c0c;
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// Check of we need to combine values from two sources within a byte.
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if (!(LHSUsedLanes & RHSUsedLanes) &&
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// If we select high and lower word keep it for SDWA.
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// TODO: teach SDWA to work with v_perm_b32 and remove the check.
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!(LHSUsedLanes == 0x0c0c0000 && RHSUsedLanes == 0x00000c0c)) {
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// Kill zero bytes selected by other mask. Zero value is 0xc.
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LHSMask &= ~RHSUsedLanes;
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RHSMask &= ~LHSUsedLanes;
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// Add 4 to each active LHS lane
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LHSMask |= LHSUsedLanes & 0x04040404;
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// Combine masks
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uint32_t Sel = LHSMask | RHSMask;
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SDLoc DL(N);
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return DAG.getNode(AMDGPUISD::PERM, DL, MVT::i32,
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LHS.getOperand(0), RHS.getOperand(0),
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DAG.getConstant(Sel, DL, MVT::i32));
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}
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}
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}
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if (VT != MVT::i64)
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return SDValue();
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@ -449,7 +449,7 @@ def V_INTERP_P1_F32_e64 : VOP3Interp <"v_interp_p1_f32", VOP3_INTERP>;
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def V_INTERP_P2_F32_e64 : VOP3Interp <"v_interp_p2_f32", VOP3_INTERP>;
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def V_INTERP_MOV_F32_e64 : VOP3Interp <"v_interp_mov_f32", VOP3_INTERP_MOV>;
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def V_PERM_B32 : VOP3Inst <"v_perm_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
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def V_PERM_B32 : VOP3Inst <"v_perm_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUperm>;
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} // End SubtargetPredicate = isVI
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let Predicates = [Has16BitInsts] in {
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@ -0,0 +1,199 @@
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
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; GCN-LABEL: {{^}}lsh8_or_and:
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; GCN: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x6050400
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; GCN: v_perm_b32 v{{[0-9]+}}, {{[vs][0-9]+}}, {{[vs][0-9]+}}, [[MASK]]
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define amdgpu_kernel void @lsh8_or_and(i32 addrspace(1)* nocapture %arg, i32 %arg1) {
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bb:
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr i32, i32 addrspace(1)* %arg, i32 %id
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%tmp = load i32, i32 addrspace(1)* %gep, align 4
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%tmp2 = shl i32 %tmp, 8
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%tmp3 = and i32 %arg1, 255
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%tmp4 = or i32 %tmp2, %tmp3
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store i32 %tmp4, i32 addrspace(1)* %gep, align 4
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ret void
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}
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; GCN-LABEL: {{^}}lsr24_or_and:
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; GCN: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x7060503
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; GCN: v_perm_b32 v{{[0-9]+}}, {{[vs][0-9]+}}, {{[vs][0-9]+}}, [[MASK]]
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define amdgpu_kernel void @lsr24_or_and(i32 addrspace(1)* nocapture %arg, i32 %arg1) {
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bb:
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr i32, i32 addrspace(1)* %arg, i32 %id
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%tmp = load i32, i32 addrspace(1)* %gep, align 4
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%tmp2 = lshr i32 %tmp, 24
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%tmp3 = and i32 %arg1, 4294967040 ; 0xffffff00
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%tmp4 = or i32 %tmp2, %tmp3
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store i32 %tmp4, i32 addrspace(1)* %gep, align 4
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ret void
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}
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; GCN-LABEL: {{^}}and_or_lsr24:
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; GCN: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x7060503
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; GCN: v_perm_b32 v{{[0-9]+}}, {{[vs][0-9]+}}, {{[vs][0-9]+}}, [[MASK]]
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define amdgpu_kernel void @and_or_lsr24(i32 addrspace(1)* nocapture %arg, i32 %arg1) {
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bb:
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr i32, i32 addrspace(1)* %arg, i32 %id
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%tmp = load i32, i32 addrspace(1)* %gep, align 4
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%tmp2 = and i32 %tmp, 4294967040 ; 0xffffff00
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%tmp3 = lshr i32 %arg1, 24
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%tmp4 = or i32 %tmp2, %tmp3
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%tmp5 = xor i32 %tmp4, -2147483648
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store i32 %tmp5, i32 addrspace(1)* %gep, align 4
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ret void
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}
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; GCN-LABEL: {{^}}and_or_and:
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; GCN: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x7020500
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; GCN: v_perm_b32 v{{[0-9]+}}, {{[vs][0-9]+}}, {{[vs][0-9]+}}, [[MASK]]
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define amdgpu_kernel void @and_or_and(i32 addrspace(1)* nocapture %arg, i32 %arg1) {
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bb:
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr i32, i32 addrspace(1)* %arg, i32 %id
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%tmp = load i32, i32 addrspace(1)* %gep, align 4
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%tmp2 = and i32 %tmp, -16711936
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%tmp3 = and i32 %arg1, 16711935
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%tmp4 = or i32 %tmp2, %tmp3
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store i32 %tmp4, i32 addrspace(1)* %gep, align 4
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ret void
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}
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; GCN-LABEL: {{^}}lsh8_or_lsr24:
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; GCN: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x6050403
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; GCN: v_perm_b32 v{{[0-9]+}}, {{[vs][0-9]+}}, {{[vs][0-9]+}}, [[MASK]]
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define amdgpu_kernel void @lsh8_or_lsr24(i32 addrspace(1)* nocapture %arg, i32 %arg1) {
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bb:
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr i32, i32 addrspace(1)* %arg, i32 %id
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%tmp = load i32, i32 addrspace(1)* %gep, align 4
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%tmp2 = shl i32 %tmp, 8
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%tmp3 = lshr i32 %arg1, 24
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%tmp4 = or i32 %tmp2, %tmp3
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store i32 %tmp4, i32 addrspace(1)* %gep, align 4
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ret void
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}
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; GCN-LABEL: {{^}}lsh16_or_lsr24:
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; GCN: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x5040c03
|
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; GCN: v_perm_b32 v{{[0-9]+}}, {{[vs][0-9]+}}, {{[vs][0-9]+}}, [[MASK]]
|
||||
define amdgpu_kernel void @lsh16_or_lsr24(i32 addrspace(1)* nocapture %arg, i32 %arg1) {
|
||||
bb:
|
||||
%id = tail call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%gep = getelementptr i32, i32 addrspace(1)* %arg, i32 %id
|
||||
%tmp = load i32, i32 addrspace(1)* %gep, align 4
|
||||
%tmp2 = shl i32 %tmp, 16
|
||||
%tmp3 = lshr i32 %arg1, 24
|
||||
%tmp4 = or i32 %tmp2, %tmp3
|
||||
store i32 %tmp4, i32 addrspace(1)* %gep, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}and_xor_and:
|
||||
; GCN: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x7020104
|
||||
; GCN: v_perm_b32 v{{[0-9]+}}, {{[vs][0-9]+}}, {{[vs][0-9]+}}, [[MASK]]
|
||||
define amdgpu_kernel void @and_xor_and(i32 addrspace(1)* nocapture %arg, i32 %arg1) {
|
||||
bb:
|
||||
%id = tail call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%gep = getelementptr i32, i32 addrspace(1)* %arg, i32 %id
|
||||
%tmp = load i32, i32 addrspace(1)* %gep, align 4
|
||||
%tmp2 = and i32 %tmp, -16776961
|
||||
%tmp3 = and i32 %arg1, 16776960
|
||||
%tmp4 = xor i32 %tmp2, %tmp3
|
||||
store i32 %tmp4, i32 addrspace(1)* %gep, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}and_or_or_and:
|
||||
; GCN: v_mov_b32_e32 [[MASK:v[0-9]+]], 0xffff0500
|
||||
; GCN: v_perm_b32 v{{[0-9]+}}, {{[vs][0-9]+}}, {{[vs][0-9]+}}, [[MASK]]
|
||||
define amdgpu_kernel void @and_or_or_and(i32 addrspace(1)* nocapture %arg, i32 %arg1) {
|
||||
bb:
|
||||
%id = tail call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%gep = getelementptr i32, i32 addrspace(1)* %arg, i32 %id
|
||||
%tmp = load i32, i32 addrspace(1)* %gep, align 4
|
||||
%and = and i32 %tmp, 16711935 ; 0x00ff00ff
|
||||
%tmp1 = and i32 %arg1, 4294967040 ; 0xffffff00
|
||||
%tmp2 = or i32 %tmp1, -65536
|
||||
%tmp3 = or i32 %tmp2, %and
|
||||
store i32 %tmp3, i32 addrspace(1)* %gep, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}and_or_and_shl:
|
||||
; GCN: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x50c0c00
|
||||
; GCN: v_perm_b32 v{{[0-9]+}}, {{[vs][0-9]+}}, {{[vs][0-9]+}}, [[MASK]]
|
||||
define amdgpu_kernel void @and_or_and_shl(i32 addrspace(1)* nocapture %arg, i32 %arg1) {
|
||||
bb:
|
||||
%id = tail call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%gep = getelementptr i32, i32 addrspace(1)* %arg, i32 %id
|
||||
%tmp = load i32, i32 addrspace(1)* %gep, align 4
|
||||
%tmp2 = shl i32 %tmp, 16
|
||||
%tmp3 = and i32 %arg1, 65535
|
||||
%tmp4 = or i32 %tmp2, %tmp3
|
||||
%and = and i32 %tmp4, 4278190335
|
||||
store i32 %and, i32 addrspace(1)* %gep, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}or_and_or:
|
||||
; GCN: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x7020104
|
||||
; GCN: v_perm_b32 v{{[0-9]+}}, {{[vs][0-9]+}}, {{[vs][0-9]+}}, [[MASK]]
|
||||
define amdgpu_kernel void @or_and_or(i32 addrspace(1)* nocapture %arg, i32 %arg1) {
|
||||
bb:
|
||||
%id = tail call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%gep = getelementptr i32, i32 addrspace(1)* %arg, i32 %id
|
||||
%tmp = load i32, i32 addrspace(1)* %gep, align 4
|
||||
%or1 = or i32 %tmp, 16776960 ; 0x00ffff00
|
||||
%or2 = or i32 %arg1, 4278190335 ; 0xff0000ff
|
||||
%and = and i32 %or1, %or2
|
||||
store i32 %and, i32 addrspace(1)* %gep, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}known_ffff0500:
|
||||
; GCN-DAG: v_mov_b32_e32 [[MASK:v[0-9]+]], 0xffff0500
|
||||
; GCN-DAG: v_mov_b32_e32 [[RES:v[0-9]+]], 0xffff8004
|
||||
; GCN: v_perm_b32 v{{[0-9]+}}, {{[vs][0-9]+}}, {{[vs][0-9]+}}, [[MASK]]
|
||||
; GCN: store_dword v[{{[0-9:]+}}], [[RES]]{{$}}
|
||||
define amdgpu_kernel void @known_ffff0500(i32 addrspace(1)* nocapture %arg, i32 %arg1) {
|
||||
bb:
|
||||
%id = tail call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%gep = getelementptr i32, i32 addrspace(1)* %arg, i32 %id
|
||||
%load = load i32, i32 addrspace(1)* %gep, align 4
|
||||
%mask1 = or i32 %arg1, 32768 ; 0x8000
|
||||
%mask2 = or i32 %load, 4
|
||||
%and = and i32 %mask2, 16711935 ; 0x00ff00ff
|
||||
%tmp1 = and i32 %mask1, 4294967040 ; 0xffffff00
|
||||
%tmp2 = or i32 %tmp1, 4294901760 ; 0xffff0000
|
||||
%tmp3 = or i32 %tmp2, %and
|
||||
store i32 %tmp3, i32 addrspace(1)* %gep, align 4
|
||||
%v = and i32 %tmp3, 4294934532 ; 0xffff8004
|
||||
store i32 %v, i32 addrspace(1)* %arg, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}known_050c0c00:
|
||||
; GCN-DAG: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x50c0c00
|
||||
; GCN-DAG: v_mov_b32_e32 [[RES:v[0-9]+]], 4{{$}}
|
||||
; GCN: v_perm_b32 v{{[0-9]+}}, {{[vs][0-9]+}}, {{[vs][0-9]+}}, [[MASK]]
|
||||
; GCN: store_dword v[{{[0-9:]+}}], [[RES]]{{$}}
|
||||
define amdgpu_kernel void @known_050c0c00(i32 addrspace(1)* nocapture %arg, i32 %arg1) {
|
||||
bb:
|
||||
%id = tail call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%gep = getelementptr i32, i32 addrspace(1)* %arg, i32 %id
|
||||
%tmp = load i32, i32 addrspace(1)* %gep, align 4
|
||||
%tmp2 = shl i32 %tmp, 16
|
||||
%mask = or i32 %arg1, 4
|
||||
%tmp3 = and i32 %mask, 65535
|
||||
%tmp4 = or i32 %tmp2, %tmp3
|
||||
%and = and i32 %tmp4, 4278190335
|
||||
store i32 %and, i32 addrspace(1)* %gep, align 4
|
||||
%v = and i32 %and, 16776964
|
||||
store i32 %v, i32 addrspace(1)* %arg, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
declare i32 @llvm.amdgcn.workitem.id.x()
|
||||
Loading…
Reference in New Issue