Adding pseudo 256-bit registers QQ0 . . . QQ7 to represent pairs of Q registers. These will be used to model VLD2 / VST2 instructions in order to get substantially better codegen for them.
llvm-svn: 103156
This commit is contained in:
Evan Cheng
parent
9d768f4445
commit
8f99a1c6b4
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@ -547,7 +547,8 @@ ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,
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case ARM::VMOVS:
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case ARM::VMOVD:
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case ARM::VMOVDneon:
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case ARM::VMOVQ: {
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case ARM::VMOVQ:
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case ARM::VMOVQQ : {
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SrcReg = MI.getOperand(1).getReg();
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DstReg = MI.getOperand(0).getReg();
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return true;
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@ -679,6 +680,14 @@ ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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SrcRC == ARM::QPR_8RegisterClass)
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SrcRC = ARM::QPRRegisterClass;
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// Allow QQPR / QQPR_VFP2 / QQPR_8 cross-class copies.
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if (DestRC == ARM::QQPR_VFP2RegisterClass ||
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DestRC == ARM::QQPR_8RegisterClass)
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DestRC = ARM::QQPRRegisterClass;
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if (SrcRC == ARM::QQPR_VFP2RegisterClass ||
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SrcRC == ARM::QQPR_8RegisterClass)
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SrcRC = ARM::QQPRRegisterClass;
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// Disallow copies of unequal sizes.
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if (DestRC != SrcRC && DestRC->getSize() != SrcRC->getSize())
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return false;
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@ -703,11 +712,12 @@ ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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Opc = ARM::VMOVDneon;
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else if (DestRC == ARM::QPRRegisterClass)
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Opc = ARM::VMOVQ;
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else if (DestRC == ARM::QQPRRegisterClass)
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Opc = ARM::VMOVQQ;
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else
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return false;
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AddDefaultPred(BuildMI(MBB, I, DL, get(Opc), DestReg)
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.addReg(SrcReg));
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AddDefaultPred(BuildMI(MBB, I, DL, get(Opc), DestReg).addReg(SrcReg));
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}
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return true;
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@ -748,12 +758,11 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
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.addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FI).addImm(0).addMemOperand(MMO));
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} else {
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assert((RC == ARM::QPRRegisterClass ||
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RC == ARM::QPR_VFP2RegisterClass ||
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RC == ARM::QPR_8RegisterClass) && "Unknown regclass!");
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} else if (RC == ARM::QPRRegisterClass ||
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RC == ARM::QPR_VFP2RegisterClass ||
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RC == ARM::QPR_8RegisterClass) {
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// FIXME: Neon instructions should support predicates
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if (Align >= 16 && (getRegisterInfo().canRealignStack(MF))) {
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if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q))
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.addFrameIndex(FI).addImm(128)
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.addMemOperand(MMO)
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@ -765,6 +774,11 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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.addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
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.addMemOperand(MMO));
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}
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} else {
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assert((RC == ARM::QQPRRegisterClass ||
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RC == ARM::QQPR_VFP2RegisterClass ||
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RC == ARM::QQPR_8RegisterClass) && "Unknown regclass!");
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llvm_unreachable("Not yet implemented!");
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}
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}
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@ -800,12 +814,10 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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RC == ARM::DPR_8RegisterClass) {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
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.addFrameIndex(FI).addImm(0).addMemOperand(MMO));
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} else {
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assert((RC == ARM::QPRRegisterClass ||
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RC == ARM::QPR_VFP2RegisterClass ||
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RC == ARM::QPR_8RegisterClass) && "Unknown regclass!");
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if (Align >= 16
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&& (getRegisterInfo().canRealignStack(MF))) {
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} else if (RC == ARM::QPRRegisterClass ||
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RC == ARM::QPR_VFP2RegisterClass ||
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RC == ARM::QPR_8RegisterClass) {
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if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q), DestReg)
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.addFrameIndex(FI).addImm(128)
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.addMemOperand(MMO));
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@ -815,6 +827,11 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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.addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
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.addMemOperand(MMO));
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}
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} else {
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assert((RC == ARM::QQPRRegisterClass ||
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RC == ARM::QQPR_VFP2RegisterClass ||
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RC == ARM::QQPR_8RegisterClass) && "Unknown regclass!");
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llvm_unreachable("Not yet implemented!");
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}
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}
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@ -262,7 +262,7 @@ ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
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case 1:
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case 2:
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case 3:
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case 4:
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case 4: {
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// S sub-registers.
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if (A->getSize() == 8) {
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if (B == &ARM::SPR_8RegClass)
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@ -273,19 +273,48 @@ ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
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return &ARM::DPR_VFP2RegClass;
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}
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assert(A->getSize() == 16 && "Expecting a Q register class!");
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if (A->getSize() == 16) {
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if (B == &ARM::SPR_8RegClass)
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return &ARM::QPR_8RegClass;
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return &ARM::QPR_VFP2RegClass;
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}
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assert(A->getSize() == 32 && "Expecting a QQ register class!");
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if (B == &ARM::SPR_8RegClass)
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return &ARM::QPR_8RegClass;
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return &ARM::QPR_VFP2RegClass;
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return &ARM::QQPR_8RegClass;
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return &ARM::QQPR_VFP2RegClass;
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}
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case 5:
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case 6:
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case 7:
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case 8: {
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// D sub-registers.
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if (A->getSize() == 16) {
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if (B == &ARM::DPR_VFP2RegClass)
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return &ARM::QPR_VFP2RegClass;
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if (B == &ARM::DPR_8RegClass)
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return &ARM::QPR_8RegClass;
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return A;
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}
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assert(A->getSize() == 32 && "Expecting a QQ register class!");
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if (B == &ARM::DPR_VFP2RegClass)
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return &ARM::QPR_VFP2RegClass;
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return &ARM::QQPR_VFP2RegClass;
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if (B == &ARM::DPR_8RegClass)
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return &ARM::QPR_8RegClass;
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return &ARM::QQPR_8RegClass;
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return A;
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}
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case 9:
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case 10: {
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// Q sub-registers.
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assert(A->getSize() == 32 && "Expecting a QQ register class!");
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if (B == &ARM::QPR_VFP2RegClass)
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return &ARM::QQPR_VFP2RegClass;
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if (B == &ARM::QPR_8RegClass)
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return &ARM::QQPR_8RegClass;
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return A;
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}
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}
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return 0;
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}
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@ -2834,6 +2834,11 @@ def VMOVDneon: N3VX<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
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def VMOVQ : N3VX<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
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N3RegFrm, IIC_VMOVD, "vmov", "$dst, $src", "", []>;
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// Pseudo vector move instruction for QQ (a pair of Q) registers. This should
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// be expanded after register allocation is completed.
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def VMOVQQ : PseudoInst<(outs QQPR:$dst), (ins QQPR:$src),
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NoItinerary, "@ vmov\t$dst, $src", []>;
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// VMOV : Vector Move (Immediate)
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// VMOV_get_imm8 xform function: convert build_vector to VMOV.i8 imm.
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@ -29,7 +29,8 @@ namespace ARM {
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/// ARMRegisterInfo.td file.
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enum SubregIndex {
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SSUBREG_0 = 1, SSUBREG_1 = 2, SSUBREG_2 = 3, SSUBREG_3 = 4,
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DSUBREG_0 = 5, DSUBREG_1 = 6
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DSUBREG_0 = 5, DSUBREG_1 = 6, DSUBREG_2 = 7, DSUBREG_3 = 8,
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QSUBREG_0 = 9, QSUBREG_1 = 10
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};
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}
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@ -106,6 +106,17 @@ def Q13 : ARMReg<13, "q13", [D26, D27]>;
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def Q14 : ARMReg<14, "q14", [D28, D29]>;
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def Q15 : ARMReg<15, "q15", [D30, D31]>;
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// Pseudo 256-bit registers to represent pairs of Q registers. These should
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// never be present in the emitted code.
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def QQ0 : ARMReg<0, "qq0", [Q0, Q1]>;
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def QQ1 : ARMReg<1, "qq1", [Q2, Q3]>;
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def QQ2 : ARMReg<2, "qq2", [Q4, Q5]>;
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def QQ3 : ARMReg<3, "qq3", [Q6, Q7]>;
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def QQ4 : ARMReg<4, "qq4", [Q8, Q9]>;
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def QQ5 : ARMReg<5, "qq5", [Q10, Q11]>;
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def QQ6 : ARMReg<6, "qq6", [Q12, Q13]>;
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def QQ7 : ARMReg<7, "qq7", [Q14, Q15]>;
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// Current Program Status Register.
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def CPSR : ARMReg<0, "cpsr">;
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@ -364,6 +375,32 @@ def QPR_8 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
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let SubRegClassList = [SPR_8, SPR_8, SPR_8, SPR_8, DPR_8, DPR_8];
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}
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// Pseudo 256-bit vector register class to model pairs of Q registers.
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def QQPR : RegisterClass<"ARM", [v4i64],
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256,
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[QQ0, QQ1, QQ2, QQ3, QQ4, QQ5, QQ6, QQ7]> {
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let SubRegClassList = [SPR_INVALID, SPR_INVALID, SPR_INVALID, SPR_INVALID,
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DPR, DPR, DPR, DPR, QPR, QPR];
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}
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// Subset of QQPR that have 32-bit SPR subregs.
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def QQPR_VFP2 : RegisterClass<"ARM", [v4i64],
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256,
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[QQ0, QQ1, QQ2, QQ3]> {
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let SubRegClassList = [SPR, SPR, SPR, SPR,
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DPR_VFP2, DPR_VFP2, DPR_VFP2, DPR_VFP2,
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QPR_VFP2, QPR_VFP2];
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}
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// Subset of QQPR that have QPR_8, DPR_8, and SPR_8 subregs.
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def QQPR_8 : RegisterClass<"ARM", [v4i64],
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256,
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[QQ0, QQ1]> {
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let SubRegClassList = [SPR_8, SPR_8, SPR_8, SPR_8,
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DPR_8, DPR_8, DPR_8, DPR_8,
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QPR_8, QPR_8];
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}
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// Condition code registers.
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def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]>;
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@ -378,6 +415,10 @@ def arm_ssubreg_2 : PatLeaf<(i32 3)>;
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def arm_ssubreg_3 : PatLeaf<(i32 4)>;
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def arm_dsubreg_0 : PatLeaf<(i32 5)>;
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def arm_dsubreg_1 : PatLeaf<(i32 6)>;
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def arm_dsubreg_2 : PatLeaf<(i32 7)>;
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def arm_dsubreg_3 : PatLeaf<(i32 8)>;
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def arm_qsubreg_0 : PatLeaf<(i32 9)>;
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def arm_qsubreg_1 : PatLeaf<(i32 10)>;
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// S sub-registers of D registers.
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def : SubRegSet<1, [D0, D1, D2, D3, D4, D5, D6, D7,
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@ -408,3 +449,31 @@ def : SubRegSet<6, [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7,
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Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15],
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[D1, D3, D5, D7, D9, D11, D13, D15,
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D17, D19, D21, D23, D25, D27, D29, D31]>;
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// S sub-registers of QQ registers. Note there are no sub-indices
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// for referencing S4 - S7, S12 - S15, and S20 - S23. It doesn't
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// look like we need them.
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def : SubRegSet<1, [QQ0, QQ1, QQ2, QQ3],
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[S0, S8, S16, S24]>;
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def : SubRegSet<2, [QQ0, QQ1, QQ2, QQ3],
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[S1, S9, S17, S25]>;
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def : SubRegSet<3, [QQ0, QQ1, QQ2, QQ3],
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[S2, S10, S18, S26]>;
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def : SubRegSet<4, [QQ0, QQ1, QQ2, QQ3],
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[S3, S11, S19, S27]>;
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// D sub-registers of QQ registers.
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def : SubRegSet<5, [QQ0, QQ1, QQ2, QQ3, QQ4, QQ5, QQ6, QQ7],
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[D0, D4, D8, D12, D16, D20, D24, D28]>;
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def : SubRegSet<6, [QQ0, QQ1, QQ2, QQ3, QQ4, QQ5, QQ6, QQ7],
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[D1, D5, D9, D13, D17, D21, D25, D29]>;
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def : SubRegSet<7, [QQ0, QQ1, QQ2, QQ3, QQ4, QQ5, QQ6, QQ7],
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[D2, D6, D10, D14, D18, D22, D26, D30]>;
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def : SubRegSet<8, [QQ0, QQ1, QQ2, QQ3, QQ4, QQ5, QQ6, QQ7],
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[D3, D7, D11, D15, D19, D23, D27, D31]>;
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// Q sub-registers of QQ registers.
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def : SubRegSet<9, [QQ0, QQ1, QQ2, QQ3, QQ4, QQ5, QQ6, QQ7],
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[Q0, Q2, Q4, Q6, Q8, Q10, Q12, Q14]>;
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def : SubRegSet<10,[QQ0, QQ1, QQ2, QQ3, QQ4, QQ5, QQ6, QQ7],
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[Q1, Q3, Q5, Q7, Q9, Q11, Q13, Q15]>;
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