Emit a left-shift instead of a power-of-two multiply for jump-tables
Summary: SelectionDAGLegalize::ExpandNode() inserts an ISD::MUL when lowering a BR_JT opcode. While many backends optimize this multiply into a shift, e.g. the MIPS backend currently always lowers this into a sequence of load-immediate+multiply+mflo in MipsSETargetLowering::lowerMulDiv(). I initially changed the multiply to a shift in the MIPS backend but it turns out that would not have handled the MIPSR6 case and was a lot more code than doing it in LegalizeDAG. I believe performing this simple optimization in LegalizeDAG instead of each individual backend is the better solution since this also fixes other backeds such as MSP430 which calls the multiply runtime function __mspabi_mpyi without this patch. Reviewers: sdardis, atanasyan, pftbest, asl Reviewed By: sdardis Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45760 llvm-svn: 332439
This commit is contained in:
Alexander Richardson
parent
85e38ee18e
commit
8f44579d0b
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@ -3688,8 +3688,17 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
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unsigned EntrySize =
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DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
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Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(), Index,
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DAG.getConstant(EntrySize, dl, Index.getValueType()));
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// For power-of-two jumptable entry sizes convert multiplication to a shift.
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// This transformation needs to be done here since otherwise the MIPS
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// backend will end up emitting a three instruction multiply sequence
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// instead of a single shift and MSP430 will call a runtime function.
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if (llvm::isPowerOf2_32(EntrySize))
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Index = DAG.getNode(
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ISD::SHL, dl, Index.getValueType(), Index,
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DAG.getConstant(llvm::Log2_32(EntrySize), dl, Index.getValueType()));
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else
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Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(), Index,
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DAG.getConstant(EntrySize, dl, Index.getValueType()));
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SDValue Addr = DAG.getNode(ISD::ADD, dl, Index.getValueType(),
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Index, Table);
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@ -7,13 +7,16 @@ target triple = "msp430---elf"
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define i16 @test(i16 %i) #0 {
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entry:
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; CHECK-LABEL: test:
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; CHECK: sub.w #4, r1
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; CHECK-NEXT: mov.w r12, 0(r1)
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; CHECK-NEXT: cmp.w #4, r12
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; CHECK-NEXT: jhs .LBB0_3
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%retval = alloca i16, align 2
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%i.addr = alloca i16, align 2
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store i16 %i, i16* %i.addr, align 2
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%0 = load i16, i16* %i.addr, align 2
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; CHECK: mov.w #2, r13
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; CHECK: call #__mspabi_mpyi
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; CHECK: br .LJTI0_0(r12)
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; CHECK: rla.w r12
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; CHECK-NEXT: br .LJTI0_0(r12)
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switch i16 %0, label %sw.default [
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i16 0, label %sw.bb
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i16 1, label %sw.bb1
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@ -28,7 +28,8 @@ entry:
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; PIC-O32: addu $[[R5:[0-9]+]], $[[R4:[0-9]+]]
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; PIC-O32: jr $[[R5]]
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; STATIC-N64: mflo $[[R0:[0-9]]]
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; STATIC-N64: dsrl $[[I32:[0-9]]], ${{[0-9]+}}, 32
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; STATIC-N64: dsll $[[R0:[0-9]]], $[[I32]], 3
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; STATIC-N64: lui $[[R1:[0-9]]], %highest(.LJTI0_0)
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; STATIC-N64: daddiu $[[R2:[0-9]]], $[[R1]], %higher(.LJTI0_0)
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; STATIC-N64: dsll $[[R3:[0-9]]], $[[R2]], 16
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@ -161,9 +161,7 @@ define i8* @_Z3fooi(i32 signext %Letter) {
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; MIPS64R2-NEXT: beqz $1, .LBB0_3
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; MIPS64R2-NEXT: nop
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; MIPS64R2-NEXT: .LBB0_1: # %entry
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; MIPS64R2-NEXT: daddiu $1, $zero, 8
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; MIPS64R2-NEXT: dmult $2, $1
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; MIPS64R2-NEXT: mflo $1
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; MIPS64R2-NEXT: dsll $1, $2, 3
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; MIPS64R2-NEXT: lui $2, %highest(.LJTI0_0)
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; MIPS64R2-NEXT: daddiu $2, $2, %higher(.LJTI0_0)
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; MIPS64R2-NEXT: dsll $2, $2, 16
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@ -481,9 +479,7 @@ define i8* @_Z3fooi(i32 signext %Letter) {
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; PIC-MIPS64R2-NEXT: beqz $1, .LBB0_3
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; PIC-MIPS64R2-NEXT: nop
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; PIC-MIPS64R2-NEXT: .LBB0_1: # %entry
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; PIC-MIPS64R2-NEXT: daddiu $1, $zero, 8
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; PIC-MIPS64R2-NEXT: dmult $3, $1
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; PIC-MIPS64R2-NEXT: mflo $1
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; PIC-MIPS64R2-NEXT: dsll $1, $3, 3
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; PIC-MIPS64R2-NEXT: ld $3, %got_page(.LJTI0_0)($2)
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; PIC-MIPS64R2-NEXT: daddu $1, $1, $3
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; PIC-MIPS64R2-NEXT: ld $1, %got_ofst(.LJTI0_0)($1)
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@ -0,0 +1,66 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; We used to generate a mul+mflo sequence instead of shifting by 2/3 to get the jump table address
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; RUN: llc %s -O2 -mtriple=mips64-unknown-freebsd -target-abi n64 -relocation-model=pic -o - | FileCheck %s
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define i64 @test(i64 %arg) {
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; CHECK-LABEL: test:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lui $1, %hi(%neg(%gp_rel(test)))
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; CHECK-NEXT: daddu $2, $1, $25
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; CHECK-NEXT: sltiu $1, $4, 11
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; CHECK-NEXT: beqz $1, .LBB0_3
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; CHECK-NEXT: nop
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; CHECK-NEXT: .LBB0_1: # %entry
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; CHECK-NEXT: daddiu $1, $2, %lo(%neg(%gp_rel(test)))
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; CHECK-NEXT: dsll $2, $4, 3
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; Previously this dsll was the following sequence:
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; daddiu $2, $zero, 8
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; dmult $4, $2
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; mflo $2
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; CHECK-NEXT: ld $3, %got_page(.LJTI0_0)($1)
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; CHECK-NEXT: daddu $2, $2, $3
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; CHECK-NEXT: ld $2, %got_ofst(.LJTI0_0)($2)
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; CHECK-NEXT: daddu $1, $2, $1
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; CHECK-NEXT: jr $1
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; CHECK-NEXT: nop
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; CHECK-NEXT: .LBB0_2: # %sw.bb
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; CHECK-NEXT: jr $ra
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; CHECK-NEXT: daddiu $2, $zero, 1
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; CHECK-NEXT: .LBB0_3: # %default
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; CHECK-NEXT: jr $ra
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; CHECK-NEXT: daddiu $2, $zero, 1234
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; CHECK-NEXT: .LBB0_4: # %sw.bb1
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; CHECK-NEXT: jr $ra
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; CHECK-NEXT: daddiu $2, $zero, 0
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entry:
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switch i64 %arg, label %default [
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i64 0, label %sw.bb
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i64 3, label %sw.bb
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i64 5, label %sw.bb
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i64 10, label %sw.bb1
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]
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default:
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ret i64 1234
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sw.bb:
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ret i64 1
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sw.bb1:
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ret i64 0
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}
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; CHECK-LABEL: .section .rodata,"a",@progbits
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; CHECK-NEXT: .p2align 3
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; CHECK-LABEL: .LJTI0_0:
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; CHECK-NEXT: .gpdword .LBB0_2
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; CHECK-NEXT: .gpdword .LBB0_3
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; CHECK-NEXT: .gpdword .LBB0_3
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; CHECK-NEXT: .gpdword .LBB0_2
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; CHECK-NEXT: .gpdword .LBB0_3
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; CHECK-NEXT: .gpdword .LBB0_2
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; CHECK-NEXT: .gpdword .LBB0_3
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; CHECK-NEXT: .gpdword .LBB0_3
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; CHECK-NEXT: .gpdword .LBB0_3
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; CHECK-NEXT: .gpdword .LBB0_3
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; CHECK-NEXT: .gpdword .LBB0_4
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