From 8c7956985326addc15b001ae419f31db4f668b5e Mon Sep 17 00:00:00 2001
From: Dan Gohman <gohman@apple.com>
Date: Wed, 5 Aug 2009 05:33:42 +0000
Subject: [PATCH] Teach X86FastISel how to handle CCValAssign::BCvt, which is
 used for MMX arguments. This fixes PR4684.

llvm-svn: 78163
---
 llvm/lib/Target/X86/X86FastISel.cpp           |  8 ++++++++
 llvm/test/CodeGen/X86/coalesce-esp.ll         |  2 +-
 llvm/test/CodeGen/X86/fast-isel-bc.ll         | 19 +++++++++++++++++++
 llvm/test/CodeGen/X86/stack-color-with-reg.ll |  2 +-
 4 files changed, 29 insertions(+), 2 deletions(-)
 create mode 100644 llvm/test/CodeGen/X86/fast-isel-bc.ll

diff --git a/llvm/lib/Target/X86/X86FastISel.cpp b/llvm/lib/Target/X86/X86FastISel.cpp
index de519e4feca6..a4bb1be799e2 100644
--- a/llvm/lib/Target/X86/X86FastISel.cpp
+++ b/llvm/lib/Target/X86/X86FastISel.cpp
@@ -1351,6 +1351,14 @@ bool X86FastISel::X86SelectCall(Instruction *I) {
       ArgVT = VA.getLocVT();
       break;
     }
+    case CCValAssign::BCvt: {
+      unsigned BC = FastEmit_r(ArgVT.getSimpleVT(), VA.getLocVT().getSimpleVT(),
+                               ISD::BIT_CONVERT, Arg);
+      assert(BC != 0 && "Failed to emit a bitcast!");
+      Arg = BC;
+      ArgVT = VA.getLocVT();
+      break;
+    }
     }
     
     if (VA.isRegLoc()) {
diff --git a/llvm/test/CodeGen/X86/coalesce-esp.ll b/llvm/test/CodeGen/X86/coalesce-esp.ll
index 8a1597870dd0..ede9b59a7e56 100644
--- a/llvm/test/CodeGen/X86/coalesce-esp.ll
+++ b/llvm/test/CodeGen/X86/coalesce-esp.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -strict-index-regclass | grep {movl	%esp, %eax}
+; RUN: llvm-as < %s | llc | grep {movl	%esp, %eax}
 ; PR4572
 
 ; Don't coalesce with %esp if it would end up putting %esp in
diff --git a/llvm/test/CodeGen/X86/fast-isel-bc.ll b/llvm/test/CodeGen/X86/fast-isel-bc.ll
new file mode 100644
index 000000000000..c713387f7277
--- /dev/null
+++ b/llvm/test/CodeGen/X86/fast-isel-bc.ll
@@ -0,0 +1,19 @@
+; RUN: llvm-as < %s | llc -O0 -march=x86-64 -mattr=+mmx | FileCheck %s
+; PR4684
+
+target datalayout =
+"e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-apple-darwin9.8"
+
+declare void @func2(<1 x i64>)
+
+define void @func1() nounwind {
+
+; This isn't spectacular, but it's MMX code at -O0...
+; CHECK: movl $2, %eax
+; CHECK: movd %rax, %mm0
+; CHECK: movd %mm0, %rdi
+
+        call void @func2(<1 x i64> <i64 2>)
+        ret void
+}
diff --git a/llvm/test/CodeGen/X86/stack-color-with-reg.ll b/llvm/test/CodeGen/X86/stack-color-with-reg.ll
index 832886be7560..114e9bf48d73 100644
--- a/llvm/test/CodeGen/X86/stack-color-with-reg.ll
+++ b/llvm/test/CodeGen/X86/stack-color-with-reg.ll
@@ -1,7 +1,7 @@
 ; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin10 -relocation-model=pic -disable-fp-elim -color-ss-with-regs -stats -info-output-file - > %t
 ; RUN:   grep stackcoloring %t | grep "loads eliminated" 
 ; RUN:   grep stackcoloring %t | grep "stack slot refs replaced with reg refs"  | grep 5
-; RUN:   grep asm-printer %t   | grep 180
+; RUN:   grep asm-printer %t   | grep 182
 
 	type { [62 x %struct.Bitvec*] }		; type %0
 	type { i8* }		; type %1