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[LegacyPassManager] Remove TargetMachine constructors 

This provides a new way to access the TargetMachine through
TargetPassConfig, as a dependency.

The patterns replaced here are:

* Passes handling a null TargetMachine call
  `getAnalysisIfAvailable<TargetPassConfig>`.

* Passes not handling a null TargetMachine
  `addRequired<TargetPassConfig>` and call
  `getAnalysis<TargetPassConfig>`.

* MachineFunctionPasses now use MF.getTarget().

* Remove all the TargetMachine constructors.
* Remove INITIALIZE_TM_PASS.

This fixes a crash when running `llc -start-before prologepilog`.

PEI needs StackProtector, which gets constructed without a TargetMachine
by the pass manager. The StackProtector pass doesn't handle the case
where there is no TargetMachine, so it segfaults.

Related to PR30324.

Differential Revision: https://reviews.llvm.org/D33222

llvm-svn: 303360
This commit is contained in:
Francis Visoiu Mistrih 2017-05-18 17:21:13 +00:00
parent 162c5cdf8f
commit 8b61764cbb
53 changed files with 323 additions and 370 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

47
llvm/include/llvm/CodeGen/Passes.h
View File

@ -33,7 +33,7 @@ class raw_ostream;
/// List of target independent CodeGen pass IDs.
namespace llvm {
FunctionPass *createAtomicExpandPass(const TargetMachine *TM);
FunctionPass *createAtomicExpandPass();
/// createUnreachableBlockEliminationPass - The LLVM code generator does not
/// work well with unreachable basic blocks (what live ranges make sense for a
@ -66,7 +66,7 @@ namespace llvm {
/// createCodeGenPreparePass - Transform the code to expose more pattern
/// matching during instruction selection.
FunctionPass *createCodeGenPreparePass(const TargetMachine *TM = nullptr);
FunctionPass *createCodeGenPreparePass();
/// createScalarizeMaskedMemIntrinPass - Replace masked load, store, gather
/// and scatter intrinsics with scalar code when target doesn't support them.
@ -177,7 +177,7 @@ namespace llvm {
/// PrologEpilogCodeInserter - This pass inserts prolog and epilog code,
/// and eliminates abstract frame references.
extern char &PrologEpilogCodeInserterID;
MachineFunctionPass *createPrologEpilogInserterPass(const TargetMachine *TM);
MachineFunctionPass *createPrologEpilogInserterPass();
/// ExpandPostRAPseudos - This pass expands pseudo instructions after
/// register allocation.
@ -305,7 +305,7 @@ namespace llvm {
/// createStackProtectorPass - This pass adds stack protectors to functions.
///
FunctionPass *createStackProtectorPass(const TargetMachine *TM);
FunctionPass *createStackProtectorPass();
/// createMachineVerifierPass - This pass verifies cenerated machine code
/// instructions for correctness.
@ -314,11 +314,11 @@ namespace llvm {
/// createDwarfEHPass - This pass mulches exception handling code into a form
/// adapted to code generation. Required if using dwarf exception handling.
FunctionPass *createDwarfEHPass(const TargetMachine *TM);
FunctionPass *createDwarfEHPass();
/// createWinEHPass - Prepares personality functions used by MSVC on Windows,
/// in addition to the Itanium LSDA based personalities.
FunctionPass *createWinEHPass(const TargetMachine *TM);
FunctionPass *createWinEHPass();
/// createSjLjEHPreparePass - This pass adapts exception handling code to use
/// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control flow.
@ -362,12 +362,12 @@ namespace llvm {
/// InterleavedAccess Pass - This pass identifies and matches interleaved
/// memory accesses to target specific intrinsics.
///
FunctionPass *createInterleavedAccessPass(const TargetMachine *TM);
FunctionPass *createInterleavedAccessPass();
/// LowerEmuTLS - This pass generates __emutls_[vt].xyz variables for all
/// TLS variables for the emulated TLS model.
///
ModulePass *createLowerEmuTLSPass(const TargetMachine *TM);
ModulePass *createLowerEmuTLSPass();
/// This pass lowers the @llvm.load.relative intrinsic to instructions.
/// This is unsafe to do earlier because a pass may combine the constant
@ -384,7 +384,7 @@ namespace llvm {
/// This pass splits the stack into a safe stack and an unsafe stack to
/// protect against stack-based overflow vulnerabilities.
FunctionPass *createSafeStackPass(const TargetMachine *TM = nullptr);
FunctionPass *createSafeStackPass();
/// This pass detects subregister lanes in a virtual register that are used
/// independently of other lanes and splits them into separate virtual
@ -419,33 +419,4 @@ namespace llvm {
} // End llvm namespace
/// Target machine pass initializer for passes with dependencies. Use with
/// INITIALIZE_TM_PASS_END.
#define INITIALIZE_TM_PASS_BEGIN INITIALIZE_PASS_BEGIN
/// Target machine pass initializer for passes with dependencies. Use with
/// INITIALIZE_TM_PASS_BEGIN.
#define INITIALIZE_TM_PASS_END(passName, arg, name, cfg, analysis) \
PassInfo *PI = new PassInfo( \
name, arg, &passName::ID, \
PassInfo::NormalCtor_t(callDefaultCtor<passName>), cfg, analysis, \
PassInfo::TargetMachineCtor_t(callTargetMachineCtor<passName>)); \
Registry.registerPass(*PI, true); \
return PI; \
} \
static llvm::once_flag Initialize##passName##PassFlag; \
void llvm::initialize##passName##Pass(PassRegistry &Registry) { \
llvm::call_once(Initialize##passName##PassFlag, \
initialize##passName##PassOnce, std::ref(Registry)); \
}
/// This initializer registers TargetMachine constructor, so the pass being
/// initialized can use target dependent interfaces. Please do not move this
/// macro to be together with INITIALIZE_PASS, which is a complete target
/// independent initializer, and we don't want to make libScalarOpts depend
/// on libCodeGen.
#define INITIALIZE_TM_PASS(passName, arg, name, cfg, analysis) \
INITIALIZE_TM_PASS_BEGIN(passName, arg, name, cfg, analysis) \
INITIALIZE_TM_PASS_END(passName, arg, name, cfg, analysis)
#endif

12
llvm/include/llvm/CodeGen/StackProtector.h
View File

@ -19,6 +19,7 @@
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/Triple.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/IR/Dominators.h"
#include "llvm/IR/ValueMap.h"
#include "llvm/Pass.h"
@ -55,7 +56,7 @@ private:
/// TLI - Keep a pointer of a TargetLowering to consult for determining
/// target type sizes.
const TargetLoweringBase *TLI = nullptr;
const Triple Trip;
Triple Trip;
Function *F;
Module *M;
@ -114,17 +115,12 @@ private:
public:
static char ID; // Pass identification, replacement for typeid.
StackProtector() : FunctionPass(ID) {
initializeStackProtectorPass(*PassRegistry::getPassRegistry());
}
StackProtector(const TargetMachine *TM)
: FunctionPass(ID), TM(TM), Trip(TM->getTargetTriple()),
SSPBufferSize(8) {
StackProtector() : FunctionPass(ID), SSPBufferSize(8) {
initializeStackProtectorPass(*PassRegistry::getPassRegistry());
}
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<TargetPassConfig>();
AU.addPreserved<DominatorTreeWrapperPass>();
}

21
llvm/include/llvm/PassInfo.h
View File

@ -32,7 +32,6 @@ class TargetMachine;
class PassInfo {
public:
typedef Pass* (*NormalCtor_t)();
typedef Pass *(*TargetMachineCtor_t)(TargetMachine *);
private:
StringRef PassName; // Nice name for Pass
@ -44,24 +43,20 @@ private:
std::vector<const PassInfo *> ItfImpl; // Interfaces implemented by this pass
NormalCtor_t NormalCtor;
TargetMachineCtor_t TargetMachineCtor;
public:
/// PassInfo ctor - Do not call this directly, this should only be invoked
/// through RegisterPass.
PassInfo(StringRef name, StringRef arg, const void *pi, NormalCtor_t normal,
bool isCFGOnly, bool is_analysis,
TargetMachineCtor_t machine = nullptr)
bool isCFGOnly, bool is_analysis)
: PassName(name), PassArgument(arg), PassID(pi), IsCFGOnlyPass(isCFGOnly),
IsAnalysis(is_analysis), IsAnalysisGroup(false), NormalCtor(normal),
TargetMachineCtor(machine) {}
IsAnalysis(is_analysis), IsAnalysisGroup(false), NormalCtor(normal) {}
/// PassInfo ctor - Do not call this directly, this should only be invoked
/// through RegisterPass. This version is for use by analysis groups; it
/// does not auto-register the pass.
PassInfo(StringRef name, const void *pi)
: PassName(name), PassArgument(""), PassID(pi), IsCFGOnlyPass(false),
IsAnalysis(false), IsAnalysisGroup(true), NormalCtor(nullptr),
TargetMachineCtor(nullptr) {}
IsAnalysis(false), IsAnalysisGroup(true), NormalCtor(nullptr) {}
/// getPassName - Return the friendly name for the pass, never returns null
///
@ -101,16 +96,6 @@ public:
NormalCtor = Ctor;
}
/// getTargetMachineCtor - Return a pointer to a function, that when called
/// with a TargetMachine, creates an instance of the pass and returns it.
/// This pointer may be null if there is no constructor with a TargetMachine
/// for the pass.
///
TargetMachineCtor_t getTargetMachineCtor() const { return TargetMachineCtor; }
void setTargetMachineCtor(TargetMachineCtor_t Ctor) {
TargetMachineCtor = Ctor;
}
/// createPass() - Use this method to create an instance of this pass.
Pass *createPass() const {
assert((!isAnalysisGroup() || NormalCtor) &&

6
llvm/include/llvm/PassSupport.h
View File

@ -31,8 +31,6 @@
namespace llvm {
class TargetMachine;
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis) \
static void *initialize##passName##PassOnce(PassRegistry &Registry) { \
PassInfo *PI = new PassInfo( \
@ -78,10 +76,6 @@ class TargetMachine;
template <typename PassName> Pass *callDefaultCtor() { return new PassName(); }
template <typename PassName> Pass *callTargetMachineCtor(TargetMachine *TM) {
return new PassName(TM);
}
//===---------------------------------------------------------------------------
/// RegisterPass<t> template - This template class is used to notify the system
/// that a Pass is available for use, and registers it into the internal

22
llvm/lib/CodeGen/AtomicExpandPass.cpp
View File

@ -17,6 +17,7 @@
#include "llvm/CodeGen/AtomicExpandUtils.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/InstIterator.h"
@ -35,12 +36,10 @@ using namespace llvm;
namespace {
class AtomicExpand: public FunctionPass {
const TargetMachine *TM;
const TargetLowering *TLI;
public:
static char ID; // Pass identification, replacement for typeid
explicit AtomicExpand(const TargetMachine *TM = nullptr)
: FunctionPass(ID), TM(TM), TLI(nullptr) {
AtomicExpand() : FunctionPass(ID), TLI(nullptr) {
initializeAtomicExpandPass(*PassRegistry::getPassRegistry());
}
@ -97,12 +96,10 @@ namespace {
char AtomicExpand::ID = 0;
char &llvm::AtomicExpandID = AtomicExpand::ID;
INITIALIZE_TM_PASS(AtomicExpand, "atomic-expand", "Expand Atomic instructions",
false, false)
INITIALIZE_PASS(AtomicExpand, "atomic-expand", "Expand Atomic instructions",
false, false)
FunctionPass *llvm::createAtomicExpandPass(const TargetMachine *TM) {
return new AtomicExpand(TM);
}
FunctionPass *llvm::createAtomicExpandPass() { return new AtomicExpand(); }
namespace {
// Helper functions to retrieve the size of atomic instructions.
@ -172,9 +169,14 @@ bool atomicSizeSupported(const TargetLowering *TLI, Inst *I) {
} // end anonymous namespace
bool AtomicExpand::runOnFunction(Function &F) {
if (!TM || !TM->getSubtargetImpl(F)->enableAtomicExpand())
auto *TPC = getAnalysisIfAvailable<TargetPassConfig>();
if (!TPC)
return false;
TLI = TM->getSubtargetImpl(F)->getTargetLowering();
auto &TM = TPC->getTM<TargetMachine>();
if (!TM.getSubtargetImpl(F)->enableAtomicExpand())
return false;
TLI = TM.getSubtargetImpl(F)->getTargetLowering();
SmallVector<Instruction *, 1> AtomicInsts;

25
llvm/lib/CodeGen/CodeGenPrepare.cpp
View File

@ -14,6 +14,7 @@
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/SetVector.h"
#include "llvm/ADT/SmallSet.h"
@ -197,10 +198,11 @@ class TypePromotionTransaction;
public:
static char ID; // Pass identification, replacement for typeid
explicit CodeGenPrepare(const TargetMachine *TM = nullptr)
: FunctionPass(ID), TM(TM), TLI(nullptr), TTI(nullptr), DL(nullptr) {
initializeCodeGenPreparePass(*PassRegistry::getPassRegistry());
}
CodeGenPrepare()
: FunctionPass(ID), TM(nullptr), TLI(nullptr), TTI(nullptr),
DL(nullptr) {
initializeCodeGenPreparePass(*PassRegistry::getPassRegistry());
}
bool runOnFunction(Function &F) override;
StringRef getPassName() const override { return "CodeGen Prepare"; }
@ -255,15 +257,13 @@ class TypePromotionTransaction;
}
char CodeGenPrepare::ID = 0;
INITIALIZE_TM_PASS_BEGIN(CodeGenPrepare, "codegenprepare",
"Optimize for code generation", false, false)
INITIALIZE_PASS_BEGIN(CodeGenPrepare, "codegenprepare",
"Optimize for code generation", false, false)
INITIALIZE_PASS_DEPENDENCY(ProfileSummaryInfoWrapperPass)
INITIALIZE_TM_PASS_END(CodeGenPrepare, "codegenprepare",
"Optimize for code generation", false, false)
INITIALIZE_PASS_END(CodeGenPrepare, "codegenprepare",
"Optimize for code generation", false, false)
FunctionPass *llvm::createCodeGenPreparePass(const TargetMachine *TM) {
return new CodeGenPrepare(TM);
}
FunctionPass *llvm::createCodeGenPreparePass() { return new CodeGenPrepare(); }
bool CodeGenPrepare::runOnFunction(Function &F) {
if (skipFunction(F))
@ -279,7 +279,8 @@ bool CodeGenPrepare::runOnFunction(Function &F) {
BPI.reset();
ModifiedDT = false;
if (TM) {
if (auto *TPC = getAnalysisIfAvailable<TargetPassConfig>()) {
TM = &TPC->getTM<TargetMachine>();
SubtargetInfo = TM->getSubtargetImpl(F);
TLI = SubtargetInfo->getTargetLowering();
TRI = SubtargetInfo->getRegisterInfo();

32
llvm/lib/CodeGen/DwarfEHPrepare.cpp
View File

@ -13,6 +13,7 @@
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/CFG.h"
@ -34,8 +35,6 @@ STATISTIC(NumResumesLowered, "Number of resume calls lowered");
namespace {
class DwarfEHPrepare : public FunctionPass {
const TargetMachine *TM;
// RewindFunction - _Unwind_Resume or the target equivalent.
Constant *RewindFunction;
@ -52,15 +51,9 @@ namespace {
public:
static char ID; // Pass identification, replacement for typeid.
// INITIALIZE_TM_PASS requires a default constructor, but it isn't used in
// practice.
DwarfEHPrepare()
: FunctionPass(ID), TM(nullptr), RewindFunction(nullptr), DT(nullptr),
TLI(nullptr) {}
DwarfEHPrepare(const TargetMachine *TM)
: FunctionPass(ID), TM(TM), RewindFunction(nullptr), DT(nullptr),
TLI(nullptr) {}
: FunctionPass(ID), RewindFunction(nullptr), DT(nullptr), TLI(nullptr) {
}
bool runOnFunction(Function &Fn) override;
@ -78,18 +71,18 @@ namespace {
} // end anonymous namespace
char DwarfEHPrepare::ID = 0;
INITIALIZE_TM_PASS_BEGIN(DwarfEHPrepare, "dwarfehprepare",
"Prepare DWARF exceptions", false, false)
INITIALIZE_PASS_BEGIN(DwarfEHPrepare, "dwarfehprepare",
"Prepare DWARF exceptions", false, false)
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
INITIALIZE_PASS_DEPENDENCY(TargetTransformInfoWrapperPass)
INITIALIZE_TM_PASS_END(DwarfEHPrepare, "dwarfehprepare",
"Prepare DWARF exceptions", false, false)
INITIALIZE_PASS_END(DwarfEHPrepare, "dwarfehprepare",
"Prepare DWARF exceptions", false, false)
FunctionPass *llvm::createDwarfEHPass(const TargetMachine *TM) {
return new DwarfEHPrepare(TM);
}
FunctionPass *llvm::createDwarfEHPass() { return new DwarfEHPrepare(); }
void DwarfEHPrepare::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<TargetPassConfig>();
AU.addRequired<TargetTransformInfoWrapperPass>();
AU.addRequired<DominatorTreeWrapperPass>();
}
@ -254,9 +247,10 @@ bool DwarfEHPrepare::InsertUnwindResumeCalls(Function &Fn) {
}
bool DwarfEHPrepare::runOnFunction(Function &Fn) {
assert(TM && "DWARF EH preparation requires a target machine");
const TargetMachine &TM =
getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
DT = &getAnalysis<DominatorTreeWrapperPass>().getDomTree();
TLI = TM->getSubtargetImpl(Fn)->getTargetLowering();
TLI = TM.getSubtargetImpl(Fn)->getTargetLowering();
bool Changed = InsertUnwindResumeCalls(Fn);
DT = nullptr;
TLI = nullptr;

19
llvm/lib/CodeGen/InterleavedAccessPass.cpp
View File

@ -45,6 +45,7 @@
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/IR/Dominators.h"
#include "llvm/IR/InstIterator.h"
#include "llvm/Support/Debug.h"
@ -68,8 +69,7 @@ class InterleavedAccess : public FunctionPass {
public:
static char ID;
InterleavedAccess(const TargetMachine *TM = nullptr)
: FunctionPass(ID), DT(nullptr), TM(TM), TLI(nullptr) {
InterleavedAccess() : FunctionPass(ID), DT(nullptr), TLI(nullptr) {
initializeInterleavedAccessPass(*PassRegistry::getPassRegistry());
}
@ -84,7 +84,6 @@ public:
private:
DominatorTree *DT;
const TargetMachine *TM;
const TargetLowering *TLI;
/// The maximum supported interleave factor.
@ -108,18 +107,18 @@ private:
} // end anonymous namespace.
char InterleavedAccess::ID = 0;
INITIALIZE_TM_PASS_BEGIN(
INITIALIZE_PASS_BEGIN(
InterleavedAccess, "interleaved-access",
"Lower interleaved memory accesses to target specific intrinsics", false,
false)
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
INITIALIZE_TM_PASS_END(
INITIALIZE_PASS_END(
InterleavedAccess, "interleaved-access",
"Lower interleaved memory accesses to target specific intrinsics", false,
false)
FunctionPass *llvm::createInterleavedAccessPass(const TargetMachine *TM) {
return new InterleavedAccess(TM);
FunctionPass *llvm::createInterleavedAccessPass() {
return new InterleavedAccess();
}
/// \brief Check if the mask is a DE-interleave mask of the given factor
@ -426,13 +425,15 @@ bool InterleavedAccess::lowerInterleavedStore(
}
bool InterleavedAccess::runOnFunction(Function &F) {
if (!TM || !LowerInterleavedAccesses)
auto *TPC = getAnalysisIfAvailable<TargetPassConfig>();
if (!TPC || !LowerInterleavedAccesses)
return false;
DEBUG(dbgs() << "*** " << getPassName() << ": " << F.getName() << "\n");
DT = &getAnalysis<DominatorTreeWrapperPass>().getDomTree();
TLI = TM->getSubtargetImpl(F)->getTargetLowering();
auto &TM = TPC->getTM<TargetMachine>();
TLI = TM.getSubtargetImpl(F)->getTargetLowering();
MaxFactor = TLI->getMaxSupportedInterleaveFactor();
// Holds dead instructions that will be erased later.

20
llvm/lib/CodeGen/LLVMTargetMachine.cpp
View File

@ -109,26 +109,24 @@ addPassesToGenerateCode(LLVMTargetMachine *TM, PassManagerBase &PM,
AnalysisID StopAfter,
MachineFunctionInitializer *MFInitializer = nullptr) {
// When in emulated TLS mode, add the LowerEmuTLS pass.
if (TM->Options.EmulatedTLS)
PM.add(createLowerEmuTLSPass(TM));
PM.add(createPreISelIntrinsicLoweringPass());
// Add internal analysis passes from the target machine.
PM.add(createTargetTransformInfoWrapperPass(TM->getTargetIRAnalysis()));
// Targets may override createPassConfig to provide a target-specific
// subclass.
TargetPassConfig *PassConfig = TM->createPassConfig(PM);
PassConfig->setStartStopPasses(StartBefore, StartAfter, StopBefore,
StopAfter);
// Set PassConfig options provided by TargetMachine.
PassConfig->setDisableVerify(DisableVerify);
PM.add(PassConfig);
// When in emulated TLS mode, add the LowerEmuTLS pass.
if (TM->Options.EmulatedTLS)
PM.add(createLowerEmuTLSPass());
PM.add(createPreISelIntrinsicLoweringPass());
// Add internal analysis passes from the target machine.
PM.add(createTargetTransformInfoWrapperPass(TM->getTargetIRAnalysis()));
PassConfig->addIRPasses();
PassConfig->addCodeGenPrepare();

22
llvm/lib/CodeGen/LowerEmuTLS.cpp
View File

@ -16,6 +16,7 @@
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/IR/LLVMContext.h"
#include "llvm/IR/Module.h"
#include "llvm/Pass.h"
@ -28,14 +29,12 @@ using namespace llvm;
namespace {
class LowerEmuTLS : public ModulePass {
const TargetMachine *TM;
public:
static char ID; // Pass identification, replacement for typeid
explicit LowerEmuTLS() : ModulePass(ID), TM(nullptr) { }
explicit LowerEmuTLS(const TargetMachine *TM)
: ModulePass(ID), TM(TM) {
LowerEmuTLS() : ModulePass(ID) {
initializeLowerEmuTLSPass(*PassRegistry::getPassRegistry());
}
bool runOnModule(Module &M) override;
private:
bool addEmuTlsVar(Module &M, const GlobalVariable *GV);
@ -55,18 +54,21 @@ private:
char LowerEmuTLS::ID = 0;
INITIALIZE_PASS(LowerEmuTLS, "loweremutls",
"Add __emutls_[vt]. variables for emultated TLS model",
false, false)
"Add __emutls_[vt]. variables for emultated TLS model", false,
false)
ModulePass *llvm::createLowerEmuTLSPass(const TargetMachine *TM) {
return new LowerEmuTLS(TM);
}
ModulePass *llvm::createLowerEmuTLSPass() { return new LowerEmuTLS(); }
bool LowerEmuTLS::runOnModule(Module &M) {
if (skipModule(M))
return false;
if (!TM || !TM->Options.EmulatedTLS)
auto *TPC = getAnalysisIfAvailable<TargetPassConfig>();
if (!TPC)
return false;
auto &TM = TPC->getTM<TargetMachine>();
if (!TM.Options.EmulatedTLS)
return false;
bool Changed = false;

4
llvm/lib/CodeGen/MachineModuleInfo.cpp
View File

@ -32,8 +32,8 @@ using namespace llvm;
using namespace llvm::dwarf;
// Handle the Pass registration stuff necessary to use DataLayout's.
INITIALIZE_TM_PASS(MachineModuleInfo, "machinemoduleinfo",
"Machine Module Information", false, false)
INITIALIZE_PASS(MachineModuleInfo, "machinemoduleinfo",
"Machine Module Information", false, false)
char MachineModuleInfo::ID = 0;
// Out of line virtual method.

42
llvm/lib/CodeGen/PrologEpilogInserter.cpp
View File

@ -60,19 +60,8 @@ namespace {
class PEI : public MachineFunctionPass {
public:
static char ID;
explicit PEI(const TargetMachine *TM = nullptr) : MachineFunctionPass(ID) {
PEI() : MachineFunctionPass(ID) {
initializePEIPass(*PassRegistry::getPassRegistry());
if (TM && (!TM->usesPhysRegsForPEI())) {
SpillCalleeSavedRegisters = [](MachineFunction &, RegScavenger *,
unsigned &, unsigned &, const MBBVector &,
const MBBVector &) {};
ScavengeFrameVirtualRegs = [](MachineFunction &, RegScavenger *) {};
} else {
SpillCalleeSavedRegisters = doSpillCalleeSavedRegs;
ScavengeFrameVirtualRegs = doScavengeFrameVirtualRegs;
UsesCalleeSaves = true;
}
}
void getAnalysisUsage(AnalysisUsage &AU) const override;
@ -140,18 +129,17 @@ WarnStackSize("warn-stack-size", cl::Hidden, cl::init((unsigned)-1),
cl::desc("Warn for stack size bigger than the given"
" number"));
INITIALIZE_TM_PASS_BEGIN(PEI, "prologepilog", "Prologue/Epilogue Insertion",
false, false)
INITIALIZE_PASS_BEGIN(PEI, "prologepilog", "Prologue/Epilogue Insertion", false,
false)
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
INITIALIZE_PASS_DEPENDENCY(StackProtector)
INITIALIZE_TM_PASS_END(PEI, "prologepilog",
"Prologue/Epilogue Insertion & Frame Finalization",
false, false)
INITIALIZE_PASS_END(PEI, "prologepilog",
"Prologue/Epilogue Insertion & Frame Finalization", false,
false)
MachineFunctionPass *
llvm::createPrologEpilogInserterPass(const TargetMachine *TM) {
return new PEI(TM);
MachineFunctionPass *llvm::createPrologEpilogInserterPass() {
return new PEI();
}
STATISTIC(NumScavengedRegs, "Number of frame index regs scavenged");
@ -174,6 +162,20 @@ typedef SmallSetVector<int, 8> StackObjSet;
/// frame indexes with appropriate references.
///
bool PEI::runOnMachineFunction(MachineFunction &Fn) {
if (!SpillCalleeSavedRegisters) {
const TargetMachine &TM = Fn.getTarget();
if (!TM.usesPhysRegsForPEI()) {
SpillCalleeSavedRegisters = [](MachineFunction &, RegScavenger *,
unsigned &, unsigned &, const MBBVector &,
const MBBVector &) {};
ScavengeFrameVirtualRegs = [](MachineFunction &, RegScavenger *) {};
} else {
SpillCalleeSavedRegisters = doSpillCalleeSavedRegs;
ScavengeFrameVirtualRegs = doScavengeFrameVirtualRegs;
UsesCalleeSaves = true;
}
}
const Function* F = Fn.getFunction();
const TargetRegisterInfo *TRI = Fn.getSubtarget().getRegisterInfo();
const TargetFrameLowering *TFI = Fn.getSubtarget().getFrameLowering();

22
llvm/lib/CodeGen/SafeStack.cpp
View File

@ -24,6 +24,7 @@
#include "llvm/Analysis/ScalarEvolution.h"
#include "llvm/Analysis/ScalarEvolutionExpressions.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DIBuilder.h"
#include "llvm/IR/DataLayout.h"
@ -767,13 +768,12 @@ class SafeStackLegacyPass : public FunctionPass {
public:
static char ID; // Pass identification, replacement for typeid..
SafeStackLegacyPass(const TargetMachine *TM) : FunctionPass(ID), TM(TM) {
SafeStackLegacyPass() : FunctionPass(ID), TM(nullptr) {
initializeSafeStackLegacyPassPass(*PassRegistry::getPassRegistry());
}
SafeStackLegacyPass() : SafeStackLegacyPass(nullptr) {}
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<TargetPassConfig>();
AU.addRequired<TargetLibraryInfoWrapperPass>();
AU.addRequired<AssumptionCacheTracker>();
}
@ -793,8 +793,7 @@ public:
return false;
}
if (!TM)
report_fatal_error("Target machine is required");
TM = &getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
auto *TL = TM->getSubtargetImpl(F)->getTargetLowering();
if (!TL)
report_fatal_error("TargetLowering instance is required");
@ -821,11 +820,10 @@ public:
} // anonymous namespace
char SafeStackLegacyPass::ID = 0;
INITIALIZE_TM_PASS_BEGIN(SafeStackLegacyPass, "safe-stack",
"Safe Stack instrumentation pass", false, false)
INITIALIZE_TM_PASS_END(SafeStackLegacyPass, "safe-stack",
"Safe Stack instrumentation pass", false, false)
INITIALIZE_PASS_BEGIN(SafeStackLegacyPass, "safe-stack",
"Safe Stack instrumentation pass", false, false)
INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
INITIALIZE_PASS_END(SafeStackLegacyPass, "safe-stack",
"Safe Stack instrumentation pass", false, false)
FunctionPass *llvm::createSafeStackPass(const llvm::TargetMachine *TM) {
return new SafeStackLegacyPass(TM);
}
FunctionPass *llvm::createSafeStackPass() { return new SafeStackLegacyPass(); }

13
llvm/lib/CodeGen/StackProtector.cpp
View File

@ -58,12 +58,13 @@ static cl::opt<bool> EnableSelectionDAGSP("enable-selectiondag-sp",
cl::init(true), cl::Hidden);
char StackProtector::ID = 0;
INITIALIZE_TM_PASS(StackProtector, "stack-protector", "Insert stack protectors",
false, true)
INITIALIZE_PASS_BEGIN(StackProtector, "stack-protector",
"Insert stack protectors", false, true)
INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
INITIALIZE_PASS_END(StackProtector, "stack-protector",
"Insert stack protectors", false, true)
FunctionPass *llvm::createStackProtectorPass(const TargetMachine *TM) {
return new StackProtector(TM);
}
FunctionPass *llvm::createStackProtectorPass() { return new StackProtector(); }
StackProtector::SSPLayoutKind
StackProtector::getSSPLayout(const AllocaInst *AI) const {
@ -97,6 +98,8 @@ bool StackProtector::runOnFunction(Function &Fn) {
DominatorTreeWrapperPass *DTWP =
getAnalysisIfAvailable<DominatorTreeWrapperPass>();
DT = DTWP ? &DTWP->getDomTree() : nullptr;
TM = &getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
Trip = TM->getTargetTriple();
TLI = TM->getSubtargetImpl(Fn)->getTargetLowering();
HasPrologue = false;
HasIRCheck = false;

18
llvm/lib/CodeGen/TargetPassConfig.cpp
View File

@ -315,7 +315,9 @@ TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) {
TargetPassConfig::TargetPassConfig()
: ImmutablePass(ID), PM(nullptr) {
llvm_unreachable("TargetPassConfig should not be constructed on-the-fly");
report_fatal_error("Trying to construct TargetPassConfig without a target "
"machine. Scheduling a CodeGen pass without a target "
"triple set?");
}
// Helper to verify the analysis is really immutable.
@ -514,14 +516,14 @@ void TargetPassConfig::addPassesToHandleExceptions() {
LLVM_FALLTHROUGH;
case ExceptionHandling::DwarfCFI:
case ExceptionHandling::ARM:
addPass(createDwarfEHPass(TM));
addPass(createDwarfEHPass());
break;
case ExceptionHandling::WinEH:
// We support using both GCC-style and MSVC-style exceptions on Windows, so
// add both preparation passes. Each pass will only actually run if it
// recognizes the personality function.
addPass(createWinEHPass(TM));
addPass(createDwarfEHPass(TM));
addPass(createWinEHPass());
addPass(createDwarfEHPass());
break;
case ExceptionHandling::None:
addPass(createLowerInvokePass());
@ -536,7 +538,7 @@ void TargetPassConfig::addPassesToHandleExceptions() {
/// before exception handling preparation passes.
void TargetPassConfig::addCodeGenPrepare() {
if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
addPass(createCodeGenPreparePass(TM));
addPass(createCodeGenPreparePass());
addPass(createRewriteSymbolsPass());
}
@ -551,8 +553,8 @@ void TargetPassConfig::addISelPrepare() {
// Add both the safe stack and the stack protection passes: each of them will
// only protect functions that have corresponding attributes.
addPass(createSafeStackPass(TM));
addPass(createStackProtectorPass(TM));
addPass(createSafeStackPass());
addPass(createStackProtectorPass());
if (PrintISelInput)
addPass(createPrintFunctionPass(
@ -647,7 +649,7 @@ void TargetPassConfig::addMachinePasses() {
// Prolog/Epilog inserter needs a TargetMachine to instantiate. But only
// do so if it hasn't been disabled, substituted, or overridden.
if (!isPassSubstitutedOrOverridden(&PrologEpilogCodeInserterID))
addPass(createPrologEpilogInserterPass(TM));
addPass(createPrologEpilogInserterPass());
/// Add passes that optimize machine instructions after register allocation.
if (getOptLevel() != CodeGenOpt::None)

10
llvm/lib/CodeGen/WinEHPrepare.cpp
View File

@ -54,7 +54,7 @@ namespace {
class WinEHPrepare : public FunctionPass {
public:
static char ID; // Pass identification, replacement for typeid.
WinEHPrepare(const TargetMachine *TM = nullptr) : FunctionPass(ID) {}
WinEHPrepare() : FunctionPass(ID) {}
bool runOnFunction(Function &Fn) override;
@ -94,12 +94,10 @@ private:
} // end anonymous namespace
char WinEHPrepare::ID = 0;
INITIALIZE_TM_PASS(WinEHPrepare, "winehprepare", "Prepare Windows exceptions",
false, false)
INITIALIZE_PASS(WinEHPrepare, "winehprepare", "Prepare Windows exceptions",
false, false)
FunctionPass *llvm::createWinEHPass(const TargetMachine *TM) {
return new WinEHPrepare(TM);
}
FunctionPass *llvm::createWinEHPass() { return new WinEHPrepare(); }
bool WinEHPrepare::runOnFunction(Function &Fn) {
if (!Fn.hasPersonalityFn())

2
llvm/lib/IR/PassRegistry.cpp
View File

@ -105,8 +105,6 @@ void PassRegistry::registerAnalysisGroup(const void *InterfaceID,
ImplementationInfo->getNormalCtor() &&
"Cannot specify pass as default if it does not have a default ctor");
InterfaceInfo->setNormalCtor(ImplementationInfo->getNormalCtor());
InterfaceInfo->setTargetMachineCtor(
ImplementationInfo->getTargetMachineCtor());
}
}

4
llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
View File

@ -324,7 +324,7 @@ TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
void AArch64PassConfig::addIRPasses() {
// Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
// ourselves.
addPass(createAtomicExpandPass(TM));
addPass(createAtomicExpandPass());
// Cmpxchg instructions are often used with a subsequent comparison to
// determine whether it succeeded. We can exploit existing control-flow in
@ -343,7 +343,7 @@ void AArch64PassConfig::addIRPasses() {
// Match interleaved memory accesses to ldN/stN intrinsics.
if (TM->getOptLevel() != CodeGenOpt::None)
addPass(createInterleavedAccessPass(TM));
addPass(createInterleavedAccessPass());
if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
// Call SeparateConstOffsetFromGEP pass to extract constants within indices

20
llvm/lib/Target/AMDGPU/AMDGPU.h
View File

@ -27,12 +27,12 @@ class PassRegistry;
class Module;
// R600 Passes
FunctionPass *createR600VectorRegMerger(TargetMachine &tm);
FunctionPass *createR600ExpandSpecialInstrsPass(TargetMachine &tm);
FunctionPass *createR600VectorRegMerger();
FunctionPass *createR600ExpandSpecialInstrsPass();
FunctionPass *createR600EmitClauseMarkers();
FunctionPass *createR600ClauseMergePass(TargetMachine &tm);
FunctionPass *createR600Packetizer(TargetMachine &tm);
FunctionPass *createR600ControlFlowFinalizer(TargetMachine &tm);
FunctionPass *createR600ClauseMergePass();
FunctionPass *createR600Packetizer();
FunctionPass *createR600ControlFlowFinalizer();
FunctionPass *createAMDGPUCFGStructurizerPass();
// SI Passes
@ -42,24 +42,24 @@ FunctionPass *createSIFoldOperandsPass();
FunctionPass *createSIPeepholeSDWAPass();
FunctionPass *createSILowerI1CopiesPass();
FunctionPass *createSIShrinkInstructionsPass();
FunctionPass *createSILoadStoreOptimizerPass(TargetMachine &tm);
FunctionPass *createSILoadStoreOptimizerPass();
FunctionPass *createSIWholeQuadModePass();
FunctionPass *createSIFixControlFlowLiveIntervalsPass();
FunctionPass *createSIFixSGPRCopiesPass();
FunctionPass *createSIDebuggerInsertNopsPass();
FunctionPass *createSIInsertWaitsPass();
FunctionPass *createSIInsertWaitcntsPass();
FunctionPass *createAMDGPUCodeGenPreparePass(const GCNTargetMachine *TM = nullptr);
FunctionPass *createAMDGPUCodeGenPreparePass();
FunctionPass *createAMDGPUMachineCFGStructurizerPass();
void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry&);
extern char &AMDGPUMachineCFGStructurizerID;
ModulePass *createAMDGPUAnnotateKernelFeaturesPass(const TargetMachine *TM = nullptr);
ModulePass *createAMDGPUAnnotateKernelFeaturesPass();
void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &);
extern char &AMDGPUAnnotateKernelFeaturesID;
ModulePass *createAMDGPULowerIntrinsicsPass(const TargetMachine *TM = nullptr);
ModulePass *createAMDGPULowerIntrinsicsPass();
void initializeAMDGPULowerIntrinsicsPass(PassRegistry &);
extern char &AMDGPULowerIntrinsicsID;
@ -97,7 +97,7 @@ void initializeSIOptimizeExecMaskingPass(PassRegistry &);
extern char &SIOptimizeExecMaskingID;
// Passes common to R600 and SI
FunctionPass *createAMDGPUPromoteAlloca(const TargetMachine *TM = nullptr);
FunctionPass *createAMDGPUPromoteAlloca();
void initializeAMDGPUPromoteAllocaPass(PassRegistry&);
extern char &AMDGPUPromoteAllocaID;

15
llvm/lib/Target/AMDGPU/AMDGPUAnnotateKernelFeatures.cpp
View File

@ -15,6 +15,7 @@
#include "AMDGPU.h"
#include "AMDGPUSubtarget.h"
#include "llvm/ADT/Triple.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/Module.h"
@ -27,7 +28,6 @@ namespace {
class AMDGPUAnnotateKernelFeatures : public ModulePass {
private:
const TargetMachine *TM;
AMDGPUAS AS;
static bool hasAddrSpaceCast(const Function &F, AMDGPUAS AS);
@ -37,8 +37,7 @@ private:
public:
static char ID;
AMDGPUAnnotateKernelFeatures(const TargetMachine *TM_ = nullptr) :
ModulePass(ID), TM(TM_) {}
AMDGPUAnnotateKernelFeatures() : ModulePass(ID) {}
bool runOnModule(Module &M) override;
StringRef getPassName() const override {
return "AMDGPU Annotate Kernel Features";
@ -221,8 +220,10 @@ bool AMDGPUAnnotateKernelFeatures::runOnModule(Module &M) {
if (F.hasFnAttribute("amdgpu-queue-ptr"))
continue;
bool HasApertureRegs =
TM && TM->getSubtarget<AMDGPUSubtarget>(F).hasApertureRegs();
auto *TPC = getAnalysisIfAvailable<TargetPassConfig>();
bool HasApertureRegs = TPC && TPC->getTM<TargetMachine>()
.getSubtarget<AMDGPUSubtarget>(F)
.hasApertureRegs();
if (!HasApertureRegs && hasAddrSpaceCast(F, AS))
F.addFnAttr("amdgpu-queue-ptr");
}
@ -231,6 +232,6 @@ bool AMDGPUAnnotateKernelFeatures::runOnModule(Module &M) {
return Changed;
}
ModulePass *llvm::createAMDGPUAnnotateKernelFeaturesPass(const TargetMachine *TM) {
return new AMDGPUAnnotateKernelFeatures(TM);
ModulePass *llvm::createAMDGPUAnnotateKernelFeaturesPass() {
return new AMDGPUAnnotateKernelFeatures();
}

24
llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
View File

@ -19,6 +19,7 @@
#include "llvm/ADT/StringRef.h"
#include "llvm/Analysis/DivergenceAnalysis.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/Constants.h"
@ -48,7 +49,6 @@ namespace {
class AMDGPUCodeGenPrepare : public FunctionPass,
public InstVisitor<AMDGPUCodeGenPrepare, bool> {
const GCNTargetMachine *TM;
const SISubtarget *ST = nullptr;
DivergenceAnalysis *DA = nullptr;
Module *Mod = nullptr;
@ -127,8 +127,7 @@ class AMDGPUCodeGenPrepare : public FunctionPass,
public:
static char ID;
AMDGPUCodeGenPrepare(const TargetMachine *TM = nullptr) :
FunctionPass(ID), TM(static_cast<const GCNTargetMachine *>(TM)) {}
AMDGPUCodeGenPrepare() : FunctionPass(ID) {}
bool visitFDiv(BinaryOperator &I);
@ -487,10 +486,15 @@ bool AMDGPUCodeGenPrepare::doInitialization(Module &M) {
}
bool AMDGPUCodeGenPrepare::runOnFunction(Function &F) {
if (!TM || skipFunction(F))
if (skipFunction(F))
return false;
ST = &TM->getSubtarget<SISubtarget>(F);
auto *TPC = getAnalysisIfAvailable<TargetPassConfig>();
if (!TPC)
return false;
const TargetMachine &TM = TPC->getTM<TargetMachine>();
ST = &TM.getSubtarget<SISubtarget>(F);
DA = &getAnalysis<DivergenceAnalysis>();
HasUnsafeFPMath = hasUnsafeFPMath(F);
@ -507,14 +511,14 @@ bool AMDGPUCodeGenPrepare::runOnFunction(Function &F) {
return MadeChange;
}
INITIALIZE_TM_PASS_BEGIN(AMDGPUCodeGenPrepare, DEBUG_TYPE,
INITIALIZE_PASS_BEGIN(AMDGPUCodeGenPrepare, DEBUG_TYPE,
"AMDGPU IR optimizations", false, false)
INITIALIZE_PASS_DEPENDENCY(DivergenceAnalysis)
INITIALIZE_TM_PASS_END(AMDGPUCodeGenPrepare, DEBUG_TYPE,
"AMDGPU IR optimizations", false, false)
INITIALIZE_PASS_END(AMDGPUCodeGenPrepare, DEBUG_TYPE, "AMDGPU IR optimizations",
false, false)
char AMDGPUCodeGenPrepare::ID = 0;
FunctionPass *llvm::createAMDGPUCodeGenPreparePass(const GCNTargetMachine *TM) {
return new AMDGPUCodeGenPrepare(TM);
FunctionPass *llvm::createAMDGPUCodeGenPreparePass() {
return new AMDGPUCodeGenPrepare();
}

21
llvm/lib/Target/AMDGPU/AMDGPULowerIntrinsics.cpp
View File

@ -9,6 +9,7 @@
#include "AMDGPU.h"
#include "AMDGPUSubtarget.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/IntrinsicInst.h"
@ -25,15 +26,13 @@ const unsigned MaxStaticSize = 1024;
class AMDGPULowerIntrinsics : public ModulePass {
private:
const TargetMachine *TM;
bool makeLIDRangeMetadata(Function &F) const;
public:
static char ID;
AMDGPULowerIntrinsics(const TargetMachine *TM = nullptr)
: ModulePass(ID), TM(TM) { }
AMDGPULowerIntrinsics() : ModulePass(ID) {}
bool runOnModule(Module &M) override;
StringRef getPassName() const override {
return "AMDGPU Lower Intrinsics";
@ -46,8 +45,8 @@ char AMDGPULowerIntrinsics::ID = 0;
char &llvm::AMDGPULowerIntrinsicsID = AMDGPULowerIntrinsics::ID;
INITIALIZE_TM_PASS(AMDGPULowerIntrinsics, DEBUG_TYPE,
"Lower intrinsics", false, false)
INITIALIZE_PASS(AMDGPULowerIntrinsics, DEBUG_TYPE, "Lower intrinsics", false,
false)
// TODO: Should refine based on estimated number of accesses (e.g. does it
// require splitting based on alignment)
@ -104,11 +103,13 @@ static bool expandMemIntrinsicUses(Function &F) {
}
bool AMDGPULowerIntrinsics::makeLIDRangeMetadata(Function &F) const {
if (!TM)
auto *TPC = getAnalysisIfAvailable<TargetPassConfig>();
if (!TPC)
return false;
const TargetMachine &TM = TPC->getTM<TargetMachine>();
const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>(F);
bool Changed = false;
const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>(F);
for (auto *U : F.users()) {
auto *CI = dyn_cast<CallInst>(U);
@ -155,6 +156,6 @@ bool AMDGPULowerIntrinsics::runOnModule(Module &M) {
return Changed;
}
ModulePass *llvm::createAMDGPULowerIntrinsicsPass(const TargetMachine *TM) {
return new AMDGPULowerIntrinsics(TM);
ModulePass *llvm::createAMDGPULowerIntrinsicsPass() {
return new AMDGPULowerIntrinsics();
}

31
llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
View File

@ -23,6 +23,7 @@
#include "llvm/ADT/Twine.h"
#include "llvm/Analysis/CaptureTracking.h"
#include "llvm/Analysis/ValueTracking.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/Constant.h"
@ -99,8 +100,7 @@ private:
public:
static char ID;
AMDGPUPromoteAlloca(const TargetMachine *TM_ = nullptr) :
FunctionPass(ID), TM(TM_) {}
AMDGPUPromoteAlloca() : FunctionPass(ID) {}
bool doInitialization(Module &M) override;
bool runOnFunction(Function &F) override;
@ -119,30 +119,31 @@ public:
char AMDGPUPromoteAlloca::ID = 0;
INITIALIZE_TM_PASS(AMDGPUPromoteAlloca, DEBUG_TYPE,
"AMDGPU promote alloca to vector or LDS", false, false)
INITIALIZE_PASS(AMDGPUPromoteAlloca, DEBUG_TYPE,
"AMDGPU promote alloca to vector or LDS", false, false)
char &llvm::AMDGPUPromoteAllocaID = AMDGPUPromoteAlloca::ID;
bool AMDGPUPromoteAlloca::doInitialization(Module &M) {
if (!TM)
return false;
Mod = &M;
DL = &Mod->getDataLayout();
const Triple &TT = TM->getTargetTriple();
IsAMDGCN = TT.getArch() == Triple::amdgcn;
IsAMDHSA = TT.getOS() == Triple::AMDHSA;
return false;
}
bool AMDGPUPromoteAlloca::runOnFunction(Function &F) {
if (!TM || skipFunction(F))
if (skipFunction(F))
return false;
if (auto *TPC = getAnalysisIfAvailable<TargetPassConfig>())
TM = &TPC->getTM<TargetMachine>();
else
return false;
const Triple &TT = TM->getTargetTriple();
IsAMDGCN = TT.getArch() == Triple::amdgcn;
IsAMDHSA = TT.getOS() == Triple::AMDHSA;
const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>(F);
if (!ST.isPromoteAllocaEnabled())
return false;
@ -874,6 +875,6 @@ void AMDGPUPromoteAlloca::handleAlloca(AllocaInst &I) {
}
}
FunctionPass *llvm::createAMDGPUPromoteAlloca(const TargetMachine *TM) {
return new AMDGPUPromoteAlloca(TM);
FunctionPass *llvm::createAMDGPUPromoteAlloca() {
return new AMDGPUPromoteAlloca();
}

20
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
View File

@ -570,7 +570,7 @@ void AMDGPUPassConfig::addIRPasses() {
disablePass(&FuncletLayoutID);
disablePass(&PatchableFunctionID);
addPass(createAMDGPULowerIntrinsicsPass(&TM));
addPass(createAMDGPULowerIntrinsicsPass());
// Function calls are not supported, so make sure we inline everything.
addPass(createAMDGPUAlwaysInlinePass());
@ -585,8 +585,7 @@ void AMDGPUPassConfig::addIRPasses() {
if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
// TODO: May want to move later or split into an early and late one.
addPass(createAMDGPUCodeGenPreparePass(
static_cast<const GCNTargetMachine *>(&TM)));
addPass(createAMDGPUCodeGenPreparePass());
}
// Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
@ -594,7 +593,7 @@ void AMDGPUPassConfig::addIRPasses() {
if (TM.getOptLevel() > CodeGenOpt::None) {
addPass(createInferAddressSpacesPass());
addPass(createAMDGPUPromoteAlloca(&TM));
addPass(createAMDGPUPromoteAlloca());
if (EnableSROA)
addPass(createSROAPass());
@ -664,22 +663,22 @@ bool R600PassConfig::addPreISel() {
}
void R600PassConfig::addPreRegAlloc() {
addPass(createR600VectorRegMerger(*TM));
addPass(createR600VectorRegMerger());
}
void R600PassConfig::addPreSched2() {
addPass(createR600EmitClauseMarkers(), false);
if (EnableR600IfConvert)
addPass(&IfConverterID, false);
addPass(createR600ClauseMergePass(*TM), false);
addPass(createR600ClauseMergePass(), false);
}
void R600PassConfig::addPreEmitPass() {
addPass(createAMDGPUCFGStructurizerPass(), false);
addPass(createR600ExpandSpecialInstrsPass(*TM), false);
addPass(createR600ExpandSpecialInstrsPass(), false);
addPass(&FinalizeMachineBundlesID, false);
addPass(createR600Packetizer(*TM), false);
addPass(createR600ControlFlowFinalizer(*TM), false);
addPass(createR600Packetizer(), false);
addPass(createR600ControlFlowFinalizer(), false);
}
TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
@ -703,8 +702,7 @@ bool GCNPassConfig::addPreISel() {
// FIXME: We need to run a pass to propagate the attributes when calls are
// supported.
const AMDGPUTargetMachine &TM = getAMDGPUTargetMachine();
addPass(createAMDGPUAnnotateKernelFeaturesPass(&TM));
addPass(createAMDGPUAnnotateKernelFeaturesPass());
// Merge divergent exit nodes. StructurizeCFG won't recognize the multi-exit
// regions formed by them.

6
llvm/lib/Target/AMDGPU/R600ClauseMergePass.cpp
View File

@ -62,7 +62,7 @@ private:
const MachineInstr &LatrCFAlu) const;
public:
R600ClauseMergePass(TargetMachine &tm) : MachineFunctionPass(ID) { }
R600ClauseMergePass() : MachineFunctionPass(ID) { }
bool runOnMachineFunction(MachineFunction &MF) override;
@ -208,6 +208,6 @@ StringRef R600ClauseMergePass::getPassName() const {
} // end anonymous namespace
llvm::FunctionPass *llvm::createR600ClauseMergePass(TargetMachine &TM) {
return new R600ClauseMergePass(TM);
llvm::FunctionPass *llvm::createR600ClauseMergePass() {
return new R600ClauseMergePass();
}

6
llvm/lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp
View File

@ -499,7 +499,7 @@ private:
}
public:
R600ControlFlowFinalizer(TargetMachine &tm) : MachineFunctionPass(ID) {}
R600ControlFlowFinalizer() : MachineFunctionPass(ID) {}
bool runOnMachineFunction(MachineFunction &MF) override {
ST = &MF.getSubtarget<R600Subtarget>();
@ -706,6 +706,6 @@ char R600ControlFlowFinalizer::ID = 0;
} // end anonymous namespace
FunctionPass *llvm::createR600ControlFlowFinalizer(TargetMachine &TM) {
return new R600ControlFlowFinalizer(TM);
FunctionPass *llvm::createR600ControlFlowFinalizer() {
return new R600ControlFlowFinalizer();
}

6
llvm/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp
View File

@ -37,7 +37,7 @@ private:
unsigned Op);
public:
R600ExpandSpecialInstrsPass(TargetMachine &tm) : MachineFunctionPass(ID),
R600ExpandSpecialInstrsPass() : MachineFunctionPass(ID),
TII(nullptr) { }
bool runOnMachineFunction(MachineFunction &MF) override;
@ -51,8 +51,8 @@ public:
char R600ExpandSpecialInstrsPass::ID = 0;
FunctionPass *llvm::createR600ExpandSpecialInstrsPass(TargetMachine &TM) {
return new R600ExpandSpecialInstrsPass(TM);
FunctionPass *llvm::createR600ExpandSpecialInstrsPass() {
return new R600ExpandSpecialInstrsPass();
}
void R600ExpandSpecialInstrsPass::SetFlagInNewMI(MachineInstr *NewMI,

6
llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp
View File

@ -124,7 +124,7 @@ private:
public:
static char ID;
R600VectorRegMerger(TargetMachine &tm) : MachineFunctionPass(ID),
R600VectorRegMerger() : MachineFunctionPass(ID),
TII(nullptr) { }
void getAnalysisUsage(AnalysisUsage &AU) const override {
@ -396,6 +396,6 @@ bool R600VectorRegMerger::runOnMachineFunction(MachineFunction &Fn) {
return false;
}
llvm::FunctionPass *llvm::createR600VectorRegMerger(TargetMachine &tm) {
return new R600VectorRegMerger(tm);
llvm::FunctionPass *llvm::createR600VectorRegMerger() {
return new R600VectorRegMerger();
}

6
llvm/lib/Target/AMDGPU/R600Packetizer.cpp
View File

@ -36,7 +36,7 @@ class R600Packetizer : public MachineFunctionPass {
public:
static char ID;
R600Packetizer(const TargetMachine &TM) : MachineFunctionPass(ID) {}
R600Packetizer() : MachineFunctionPass(ID) {}
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesCFG();
@ -404,6 +404,6 @@ bool R600Packetizer::runOnMachineFunction(MachineFunction &Fn) {
} // end anonymous namespace
llvm::FunctionPass *llvm::createR600Packetizer(TargetMachine &tm) {
return new R600Packetizer(tm);
llvm::FunctionPass *llvm::createR600Packetizer() {
return new R600Packetizer();
}

8
llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
View File

@ -97,9 +97,7 @@ private:
public:
static char ID;
SILoadStoreOptimizer() : MachineFunctionPass(ID) {}
SILoadStoreOptimizer(const TargetMachine &TM_) : MachineFunctionPass(ID) {
SILoadStoreOptimizer() : MachineFunctionPass(ID) {
initializeSILoadStoreOptimizerPass(*PassRegistry::getPassRegistry());
}
@ -129,8 +127,8 @@ char SILoadStoreOptimizer::ID = 0;
char &llvm::SILoadStoreOptimizerID = SILoadStoreOptimizer::ID;
FunctionPass *llvm::createSILoadStoreOptimizerPass(TargetMachine &TM) {
return new SILoadStoreOptimizer(TM);
FunctionPass *llvm::createSILoadStoreOptimizerPass() {
return new SILoadStoreOptimizer();
}
static void moveInstsAfter(MachineBasicBlock::iterator I,

4
llvm/lib/Target/ARM/ARMTargetMachine.cpp
View File

@ -471,7 +471,7 @@ void ARMPassConfig::addIRPasses() {
if (TM->Options.ThreadModel == ThreadModel::Single)
addPass(createLowerAtomicPass());
else
addPass(createAtomicExpandPass(TM));
addPass(createAtomicExpandPass());
// Cmpxchg instructions are often used with a subsequent comparison to
// determine whether it succeeded. We can exploit existing control-flow in
@ -486,7 +486,7 @@ void ARMPassConfig::addIRPasses() {
// Match interleaved memory accesses to ldN/stN intrinsics.
if (TM->getOptLevel() != CodeGenOpt::None)
addPass(createInterleavedAccessPass(TM));
addPass(createInterleavedAccessPass());
}
bool ARMPassConfig::addPreISel() {

2
llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
View File

@ -252,7 +252,7 @@ void HexagonPassConfig::addIRPasses() {
TargetPassConfig::addIRPasses();
bool NoOpt = (getOptLevel() == CodeGenOpt::None);
addPass(createAtomicExpandPass(TM));
addPass(createAtomicExpandPass());
if (!NoOpt) {
if (EnableLoopPrefetch)
addPass(createLoopDataPrefetchPass());

12
llvm/lib/Target/Mips/Mips.h
View File

@ -23,14 +23,14 @@ namespace llvm {
class ModulePass;
class FunctionPass;
ModulePass *createMipsOs16Pass(MipsTargetMachine &TM);
ModulePass *createMips16HardFloatPass(MipsTargetMachine &TM);
ModulePass *createMipsOs16Pass();
ModulePass *createMips16HardFloatPass();
FunctionPass *createMipsModuleISelDagPass(MipsTargetMachine &TM);
FunctionPass *createMipsOptimizePICCallPass(MipsTargetMachine &TM);
FunctionPass *createMipsDelaySlotFillerPass(MipsTargetMachine &TM);
FunctionPass *createMipsModuleISelDagPass();
FunctionPass *createMipsOptimizePICCallPass();
FunctionPass *createMipsDelaySlotFillerPass();
FunctionPass *createMipsHazardSchedule();
FunctionPass *createMipsLongBranchPass(MipsTargetMachine &TM);
FunctionPass *createMipsLongBranchPass();
FunctionPass *createMipsConstantIslandPass();
FunctionPass *createMicroMipsSizeReductionPass();
} // end namespace llvm;

17
llvm/lib/Target/Mips/Mips16HardFloat.cpp
View File

@ -12,6 +12,7 @@
//===----------------------------------------------------------------------===//
#include "MipsTargetMachine.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/IR/Module.h"
#include "llvm/IR/Value.h"
#include "llvm/Support/Debug.h"
@ -28,14 +29,16 @@ namespace {
public:
static char ID;
Mips16HardFloat(MipsTargetMachine &TM_) : ModulePass(ID), TM(TM_) {}
Mips16HardFloat() : ModulePass(ID) {}
StringRef getPassName() const override { return "MIPS16 Hard Float Pass"; }
bool runOnModule(Module &M) override;
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<TargetPassConfig>();
ModulePass::getAnalysisUsage(AU);
}
protected:
const MipsTargetMachine &TM;
bool runOnModule(Module &M) override;
};
static void EmitInlineAsm(LLVMContext &C, BasicBlock *BB, StringRef AsmText) {
@ -520,6 +523,8 @@ static void removeUseSoftFloat(Function &F) {
// during call lowering but it should be moved here in the future.
//
bool Mips16HardFloat::runOnModule(Module &M) {
auto &TM = static_cast<const MipsTargetMachine &>(
getAnalysis<TargetPassConfig>().getTM<TargetMachine>());
DEBUG(errs() << "Run on Module Mips16HardFloat\n");
bool Modified = false;
for (Module::iterator F = M.begin(), E = M.end(); F != E; ++F) {
@ -541,6 +546,6 @@ bool Mips16HardFloat::runOnModule(Module &M) {
}
ModulePass *llvm::createMips16HardFloatPass(MipsTargetMachine &TM) {
return new Mips16HardFloat(TM);
ModulePass *llvm::createMips16HardFloatPass() {
return new Mips16HardFloat();
}

12
llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
View File

@ -211,12 +211,12 @@ namespace {
class Filler : public MachineFunctionPass {
public:
Filler(TargetMachine &tm)
: MachineFunctionPass(ID), TM(tm) { }
Filler() : MachineFunctionPass(ID), TM(nullptr) {}
StringRef getPassName() const override { return "Mips Delay Slot Filler"; }
bool runOnMachineFunction(MachineFunction &F) override {
TM = &F.getTarget();
bool Changed = false;
for (MachineFunction::iterator FI = F.begin(), FE = F.end();
FI != FE; ++FI)
@ -290,7 +290,7 @@ namespace {
bool terminateSearch(const MachineInstr &Candidate) const;
TargetMachine &TM;
const TargetMachine *TM;
static char ID;
};
@ -610,7 +610,7 @@ bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
Changed = true;
// Delay slot filling is disabled at -O0.
if (!DisableDelaySlotFiller && (TM.getOptLevel() != CodeGenOpt::None)) {
if (!DisableDelaySlotFiller && (TM->getOptLevel() != CodeGenOpt::None)) {
bool Filled = false;
if (MipsCompactBranchPolicy.getValue() != CB_Always ||
@ -910,6 +910,4 @@ bool Filler::terminateSearch(const MachineInstr &Candidate) const {
/// createMipsDelaySlotFillerPass - Returns a pass that fills in delay
/// slots in Mips MachineFunctions
FunctionPass *llvm::createMipsDelaySlotFillerPass(MipsTargetMachine &tm) {
return new Filler(tm);
}
FunctionPass *llvm::createMipsDelaySlotFillerPass() { return new Filler(); }

16
llvm/lib/Target/Mips/MipsLongBranch.cpp
View File

@ -75,9 +75,8 @@ namespace {
public:
static char ID;
MipsLongBranch(TargetMachine &tm)
: MachineFunctionPass(ID), TM(tm), IsPIC(TM.isPositionIndependent()),
ABI(static_cast<const MipsTargetMachine &>(TM).getABI()) {}
MipsLongBranch()
: MachineFunctionPass(ID), ABI(MipsABIInfo::Unknown()) {}
StringRef getPassName() const override { return "Mips Long Branch"; }
@ -96,7 +95,6 @@ namespace {
MachineBasicBlock *MBBOpnd);
void expandToLongBranch(MBBInfo &Info);
const TargetMachine &TM;
MachineFunction *MF;
SmallVector<MBBInfo, 16> MBBInfos;
bool IsPIC;
@ -469,6 +467,12 @@ bool MipsLongBranch::runOnMachineFunction(MachineFunction &F) {
static_cast<const MipsSubtarget &>(F.getSubtarget());
const MipsInstrInfo *TII =
static_cast<const MipsInstrInfo *>(STI.getInstrInfo());
const TargetMachine& TM = F.getTarget();
IsPIC = TM.isPositionIndependent();
ABI = static_cast<const MipsTargetMachine &>(TM).getABI();
LongBranchSeqSize =
!IsPIC ? 2 : (ABI.IsN64() ? 10 : (!STI.isTargetNaCl() ? 9 : 10));
@ -541,6 +545,4 @@ bool MipsLongBranch::runOnMachineFunction(MachineFunction &F) {
/// createMipsLongBranchPass - Returns a pass that converts branches to long
/// branches.
FunctionPass *llvm::createMipsLongBranchPass(MipsTargetMachine &tm) {
return new MipsLongBranch(tm);
}
FunctionPass *llvm::createMipsLongBranchPass() { return new MipsLongBranch(); }

18
llvm/lib/Target/Mips/MipsModuleISelDAGToDAG.cpp
View File

@ -10,6 +10,7 @@
#include "Mips.h"
#include "MipsTargetMachine.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
@ -22,18 +23,19 @@ namespace {
public:
static char ID;
explicit MipsModuleDAGToDAGISel(MipsTargetMachine &TM_)
: MachineFunctionPass(ID), TM(TM_) {}
MipsModuleDAGToDAGISel() : MachineFunctionPass(ID) {}
// Pass Name
StringRef getPassName() const override {
return "MIPS DAG->DAG Pattern Instruction Selection";
}
bool runOnMachineFunction(MachineFunction &MF) override;
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<TargetPassConfig>();
MachineFunctionPass::getAnalysisUsage(AU);
}
protected:
MipsTargetMachine &TM;
bool runOnMachineFunction(MachineFunction &MF) override;
};
char MipsModuleDAGToDAGISel::ID = 0;
@ -41,10 +43,12 @@ namespace {
bool MipsModuleDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
DEBUG(errs() << "In MipsModuleDAGToDAGISel::runMachineFunction\n");
auto &TPC = getAnalysis<TargetPassConfig>();
auto &TM = TPC.getTM<MipsTargetMachine>();
TM.resetSubtarget(&MF);
return false;
}
llvm::FunctionPass *llvm::createMipsModuleISelDagPass(MipsTargetMachine &TM) {
return new MipsModuleDAGToDAGISel(TM);
llvm::FunctionPass *llvm::createMipsModuleISelDagPass() {
return new MipsModuleDAGToDAGISel();
}

6
llvm/lib/Target/Mips/MipsOptimizePICCall.cpp
View File

@ -59,7 +59,7 @@ private:
class OptimizePICCall : public MachineFunctionPass {
public:
OptimizePICCall(TargetMachine &tm) : MachineFunctionPass(ID) {}
OptimizePICCall() : MachineFunctionPass(ID) {}
StringRef getPassName() const override { return "Mips OptimizePICCall"; }
@ -297,6 +297,6 @@ void OptimizePICCall::incCntAndSetReg(ValueType Entry, unsigned Reg) {
}
/// Return an OptimizeCall object.
FunctionPass *llvm::createMipsOptimizePICCallPass(MipsTargetMachine &TM) {
return new OptimizePICCall(TM);
FunctionPass *llvm::createMipsOptimizePICCallPass() {
return new OptimizePICCall();
}

4
llvm/lib/Target/Mips/MipsOs16.cpp
View File

@ -155,6 +155,4 @@ bool MipsOs16::runOnModule(Module &M) {
return modified;
}
ModulePass *llvm::createMipsOs16Pass(MipsTargetMachine &TM) {
return new MipsOs16;
}
ModulePass *llvm::createMipsOs16Pass() { return new MipsOs16(); }

15
llvm/lib/Target/Mips/MipsTargetMachine.cpp
View File

@ -223,23 +223,23 @@ TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) {
void MipsPassConfig::addIRPasses() {
TargetPassConfig::addIRPasses();
addPass(createAtomicExpandPass(&getMipsTargetMachine()));
addPass(createAtomicExpandPass());
if (getMipsSubtarget().os16())
addPass(createMipsOs16Pass(getMipsTargetMachine()));
addPass(createMipsOs16Pass());
if (getMipsSubtarget().inMips16HardFloat())
addPass(createMips16HardFloatPass(getMipsTargetMachine()));
addPass(createMips16HardFloatPass());
}
// Install an instruction selector pass using
// the ISelDag to gen Mips code.
bool MipsPassConfig::addInstSelector() {
addPass(createMipsModuleISelDagPass(getMipsTargetMachine()));
addPass(createMipsModuleISelDagPass());
addPass(createMips16ISelDag(getMipsTargetMachine(), getOptLevel()));
addPass(createMipsSEISelDag(getMipsTargetMachine(), getOptLevel()));
return false;
}
void MipsPassConfig::addPreRegAlloc() {
addPass(createMipsOptimizePICCallPass(getMipsTargetMachine()));
addPass(createMipsOptimizePICCallPass());
}
TargetIRAnalysis MipsTargetMachine::getTargetIRAnalysis() {
@ -259,15 +259,14 @@ TargetIRAnalysis MipsTargetMachine::getTargetIRAnalysis() {
// machine code is emitted. return true if -print-machineinstrs should
// print out the code after the passes.
void MipsPassConfig::addPreEmitPass() {
MipsTargetMachine &TM = getMipsTargetMachine();
addPass(createMicroMipsSizeReductionPass());
// The delay slot filler pass can potientially create forbidden slot (FS)
// hazards for MIPSR6 which the hazard schedule pass (HSP) will fix. Any
// (new) pass that creates compact branches after the HSP must handle FS
// hazards itself or be pipelined before the HSP.
addPass(createMipsDelaySlotFillerPass(TM));
addPass(createMipsDelaySlotFillerPass());
addPass(createMipsHazardSchedule());
addPass(createMipsLongBranchPass(TM));
addPass(createMipsLongBranchPass());
addPass(createMipsConstantIslandPass());
}

2
llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
View File

@ -322,7 +322,7 @@ TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
void PPCPassConfig::addIRPasses() {
if (TM->getOptLevel() != CodeGenOpt::None)
addPass(createPPCBoolRetToIntPass());
addPass(createAtomicExpandPass(&getPPCTargetMachine()));
addPass(createAtomicExpandPass());
// For the BG/Q (or if explicitly requested), add explicit data prefetch
// intrinsics.

2
llvm/lib/Target/Sparc/DelaySlotFiller.cpp
View File

@ -96,7 +96,7 @@ namespace {
/// createSparcDelaySlotFillerPass - Returns a pass that fills in delay
/// slots in Sparc MachineFunctions
///
FunctionPass *llvm::createSparcDelaySlotFillerPass(TargetMachine &tm) {
FunctionPass *llvm::createSparcDelaySlotFillerPass() {
return new Filler;
}

17
llvm/lib/Target/Sparc/LeonPasses.cpp
View File

@ -21,9 +21,6 @@
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
LEONMachineFunctionPass::LEONMachineFunctionPass(TargetMachine &tm, char &ID)
: MachineFunctionPass(ID) {}
LEONMachineFunctionPass::LEONMachineFunctionPass(char &ID)
: MachineFunctionPass(ID) {}
@ -72,8 +69,7 @@ int LEONMachineFunctionPass::getUnusedFPRegister(MachineRegisterInfo &MRI) {
//
char InsertNOPLoad::ID = 0;
InsertNOPLoad::InsertNOPLoad(TargetMachine &tm)
: LEONMachineFunctionPass(tm, ID) {}
InsertNOPLoad::InsertNOPLoad() : LEONMachineFunctionPass(ID) {}
bool InsertNOPLoad::runOnMachineFunction(MachineFunction &MF) {
Subtarget = &MF.getSubtarget<SparcSubtarget>();
@ -114,7 +110,7 @@ bool InsertNOPLoad::runOnMachineFunction(MachineFunction &MF) {
//
char FixFSMULD::ID = 0;
FixFSMULD::FixFSMULD(TargetMachine &tm) : LEONMachineFunctionPass(tm, ID) {}
FixFSMULD::FixFSMULD() : LEONMachineFunctionPass(ID) {}
bool FixFSMULD::runOnMachineFunction(MachineFunction &MF) {
Subtarget = &MF.getSubtarget<SparcSubtarget>();
@ -203,8 +199,7 @@ bool FixFSMULD::runOnMachineFunction(MachineFunction &MF) {
//
char ReplaceFMULS::ID = 0;
ReplaceFMULS::ReplaceFMULS(TargetMachine &tm)
: LEONMachineFunctionPass(tm, ID) {}
ReplaceFMULS::ReplaceFMULS() : LEONMachineFunctionPass(ID) {}
bool ReplaceFMULS::runOnMachineFunction(MachineFunction &MF) {
Subtarget = &MF.getSubtarget<SparcSubtarget>();
@ -287,8 +282,7 @@ bool ReplaceFMULS::runOnMachineFunction(MachineFunction &MF) {
char DetectRoundChange::ID = 0;
DetectRoundChange::DetectRoundChange(TargetMachine &tm)
: LEONMachineFunctionPass(tm, ID) {}
DetectRoundChange::DetectRoundChange() : LEONMachineFunctionPass(ID) {}
bool DetectRoundChange::runOnMachineFunction(MachineFunction &MF) {
Subtarget = &MF.getSubtarget<SparcSubtarget>();
@ -338,8 +332,7 @@ bool DetectRoundChange::runOnMachineFunction(MachineFunction &MF) {
//
char FixAllFDIVSQRT::ID = 0;
FixAllFDIVSQRT::FixAllFDIVSQRT(TargetMachine &tm)
: LEONMachineFunctionPass(tm, ID) {}
FixAllFDIVSQRT::FixAllFDIVSQRT() : LEONMachineFunctionPass(ID) {}
bool FixAllFDIVSQRT::runOnMachineFunction(MachineFunction &MF) {
Subtarget = &MF.getSubtarget<SparcSubtarget>();

11
llvm/lib/Target/Sparc/LeonPasses.h
View File

@ -32,7 +32,6 @@ protected:
std::vector<int> UsedRegisters;
protected:
LEONMachineFunctionPass(TargetMachine &tm, char &ID);
LEONMachineFunctionPass(char &ID);
int GetRegIndexForOperand(MachineInstr &MI, int OperandIndex);
@ -48,7 +47,7 @@ class LLVM_LIBRARY_VISIBILITY InsertNOPLoad : public LEONMachineFunctionPass {
public:
static char ID;
InsertNOPLoad(TargetMachine &tm);
InsertNOPLoad();
bool runOnMachineFunction(MachineFunction &MF) override;
StringRef getPassName() const override {
@ -62,7 +61,7 @@ class LLVM_LIBRARY_VISIBILITY FixFSMULD : public LEONMachineFunctionPass {
public:
static char ID;
FixFSMULD(TargetMachine &tm);
FixFSMULD();
bool runOnMachineFunction(MachineFunction &MF) override;
StringRef getPassName() const override {
@ -74,7 +73,7 @@ class LLVM_LIBRARY_VISIBILITY ReplaceFMULS : public LEONMachineFunctionPass {
public:
static char ID;
ReplaceFMULS(TargetMachine &tm);
ReplaceFMULS();
bool runOnMachineFunction(MachineFunction &MF) override;
StringRef getPassName() const override {
@ -89,7 +88,7 @@ class LLVM_LIBRARY_VISIBILITY DetectRoundChange
public:
static char ID;
DetectRoundChange(TargetMachine &tm);
DetectRoundChange();
bool runOnMachineFunction(MachineFunction &MF) override;
StringRef getPassName() const override {
@ -102,7 +101,7 @@ class LLVM_LIBRARY_VISIBILITY FixAllFDIVSQRT : public LEONMachineFunctionPass {
public:
static char ID;
FixAllFDIVSQRT(TargetMachine &tm);
FixAllFDIVSQRT();
bool runOnMachineFunction(MachineFunction &MF) override;
StringRef getPassName() const override {

2
llvm/lib/Target/Sparc/Sparc.h
View File

@ -28,7 +28,7 @@ namespace llvm {
class MachineInstr;
FunctionPass *createSparcISelDag(SparcTargetMachine &TM);
FunctionPass *createSparcDelaySlotFillerPass(TargetMachine &TM);
FunctionPass *createSparcDelaySlotFillerPass();
void LowerSparcMachineInstrToMCInst(const MachineInstr *MI,
MCInst &OutMI,

14
llvm/lib/Target/Sparc/SparcTargetMachine.cpp
View File

@ -132,7 +132,7 @@ TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) {
}
void SparcPassConfig::addIRPasses() {
addPass(createAtomicExpandPass(&getSparcTargetMachine()));
addPass(createAtomicExpandPass());
TargetPassConfig::addIRPasses();
}
@ -143,26 +143,26 @@ bool SparcPassConfig::addInstSelector() {
}
void SparcPassConfig::addPreEmitPass(){
addPass(createSparcDelaySlotFillerPass(getSparcTargetMachine()));
addPass(createSparcDelaySlotFillerPass());
if (this->getSparcTargetMachine().getSubtargetImpl()->insertNOPLoad())
{
addPass(new InsertNOPLoad(getSparcTargetMachine()));
addPass(new InsertNOPLoad());
}
if (this->getSparcTargetMachine().getSubtargetImpl()->fixFSMULD())
{
addPass(new FixFSMULD(getSparcTargetMachine()));
addPass(new FixFSMULD());
}
if (this->getSparcTargetMachine().getSubtargetImpl()->replaceFMULS())
{
addPass(new ReplaceFMULS(getSparcTargetMachine()));
addPass(new ReplaceFMULS());
}
if (this->getSparcTargetMachine().getSubtargetImpl()->detectRoundChange()) {
addPass(new DetectRoundChange(getSparcTargetMachine()));
addPass(new DetectRoundChange());
}
if (this->getSparcTargetMachine().getSubtargetImpl()->fixAllFDIVSQRT())
{
addPass(new FixAllFDIVSQRT(getSparcTargetMachine()));
addPass(new FixAllFDIVSQRT());
}
}

2
llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
View File

@ -173,7 +173,7 @@ void WebAssemblyPassConfig::addIRPasses() {
else
// Expand some atomic operations. WebAssemblyTargetLowering has hooks which
// control specifically what gets lowered.
addPass(createAtomicExpandPass(TM));
addPass(createAtomicExpandPass());
// Fix function bitcasts, as WebAssembly requires caller and callee signatures
// to match.

4
llvm/lib/Target/X86/X86TargetMachine.cpp
View File

@ -380,12 +380,12 @@ TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
}
void X86PassConfig::addIRPasses() {
addPass(createAtomicExpandPass(&getX86TargetMachine()));
addPass(createAtomicExpandPass());
TargetPassConfig::addIRPasses();
if (TM->getOptLevel() != CodeGenOpt::None)
addPass(createInterleavedAccessPass(TM));
addPass(createInterleavedAccessPass());
}
bool X86PassConfig::addInstSelector() {

2
llvm/lib/Target/XCore/XCoreTargetMachine.cpp
View File

@ -74,7 +74,7 @@ TargetPassConfig *XCoreTargetMachine::createPassConfig(PassManagerBase &PM) {
}
void XCorePassConfig::addIRPasses() {
addPass(createAtomicExpandPass(&getXCoreTargetMachine()));
addPass(createAtomicExpandPass());
TargetPassConfig::addIRPasses();
}

3
llvm/test/CodeGen/Generic/opt-codegen-no-target-machine.ll Normal file
View File

@ -0,0 +1,3 @@
; RUN: not opt %s -dwarfehprepare -o - 2>&1 | FileCheck %s
; CHECK: Trying to construct TargetPassConfig without a target machine. Scheduling a CodeGen pass without a target triple set?

2
llvm/test/CodeGen/X86/O0-pipeline.ll
View File

@ -4,8 +4,8 @@
; CHECK-LABEL: Pass Arguments:
; CHECK-NEXT: Target Library Information
; CHECK-NEXT: Target Transform Information
; CHECK-NEXT: Target Pass Configuration
; CHECK-NEXT: Target Transform Information
; CHECK-NEXT: Type-Based Alias Analysis
; CHECK-NEXT: Scoped NoAlias Alias Analysis
; CHECK-NEXT: Assumption Cache Tracker

4
llvm/tools/llc/llc.cpp
View File

@ -356,9 +356,7 @@ static bool addPass(PassManagerBase &PM, const char *argv0,
}
Pass *P;
if (PI->getTargetMachineCtor())
P = PI->getTargetMachineCtor()(&TPC.getTM<TargetMachine>());
else if (PI->getNormalCtor())
if (PI->getNormalCtor())
P = PI->getNormalCtor()();
else {
errs() << argv0 << ": cannot create pass: " << PI->getPassName() << "\n";

12
llvm/tools/opt/opt.cpp
View File

@ -24,6 +24,7 @@
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/Bitcode/BitcodeWriterPass.h"
#include "llvm/CodeGen/CommandFlags.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DebugInfo.h"
#include "llvm/IR/IRPrintingPasses.h"
@ -579,6 +580,13 @@ int main(int argc, char **argv) {
NoOutput = true;
}
if (TM) {
// FIXME: We should dyn_cast this when supported.
auto &LTM = static_cast<LLVMTargetMachine &>(*TM);
Pass *TPC = LTM.createPassConfig(Passes);
Passes.add(TPC);
}
// Create a new optimization pass for each one specified on the command line
for (unsigned i = 0; i < PassList.size(); ++i) {
if (StandardLinkOpts &&
@ -619,9 +627,7 @@ int main(int argc, char **argv) {
const PassInfo *PassInf = PassList[i];
Pass *P = nullptr;
if (PassInf->getTargetMachineCtor())
P = PassInf->getTargetMachineCtor()(TM.get());
else if (PassInf->getNormalCtor())
if (PassInf->getNormalCtor())
P = PassInf->getNormalCtor()();
else
errs() << argv[0] << ": cannot create pass: "