[SystemZ] Add support for anyregcc calling convention
This adds back-end support for the anyregcc calling convention for use with patchpoints. Since all registers are considered call-saved with anyregcc (except for 0 and 1 which may still be clobbered by PLT stubs and the like), this required adding support for saving and restoring vector registers in prologue/epilogue code for the first time. This is not used by any other calling convention. llvm-svn: 326612
This commit is contained in:
Ulrich Weigand
parent
5eb64110d2
commit
8b19be46c7
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@ -120,3 +120,12 @@ def CSR_SystemZ : CalleeSavedRegs<(add (sequence "R%dD", 6, 15),
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// R9 is used to return SwiftError; remove it from CSR.
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def CSR_SystemZ_SwiftError : CalleeSavedRegs<(sub CSR_SystemZ, R9D)>;
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// "All registers" as used by the AnyReg calling convention.
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// Note that registers 0 and 1 are still defined as intra-call scratch
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// registers that may be clobbered e.g. by PLT stubs.
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def CSR_SystemZ_AllRegs : CalleeSavedRegs<(add (sequence "R%dD", 2, 15),
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(sequence "F%dD", 0, 15))>;
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def CSR_SystemZ_AllRegs_Vector : CalleeSavedRegs<(add (sequence "R%dD", 2, 15),
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(sequence "V%d", 0, 31))>;
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@ -204,7 +204,7 @@ spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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addSavedGPR(MBB, MIB, SystemZ::ArgGPRs[I], true);
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}
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// Save FPRs in the normal TargetInstrInfo way.
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// Save FPRs/VRs in the normal TargetInstrInfo way.
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for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
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unsigned Reg = CSI[I].getReg();
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if (SystemZ::FP64BitRegClass.contains(Reg)) {
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@ -212,6 +212,11 @@ spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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TII->storeRegToStackSlot(MBB, MBBI, Reg, true, CSI[I].getFrameIdx(),
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&SystemZ::FP64BitRegClass, TRI);
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}
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if (SystemZ::VR128BitRegClass.contains(Reg)) {
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MBB.addLiveIn(Reg);
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TII->storeRegToStackSlot(MBB, MBBI, Reg, true, CSI[I].getFrameIdx(),
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&SystemZ::VR128BitRegClass, TRI);
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}
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}
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return true;
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@ -231,12 +236,15 @@ restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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bool HasFP = hasFP(MF);
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DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
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// Restore FPRs in the normal TargetInstrInfo way.
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// Restore FPRs/VRs in the normal TargetInstrInfo way.
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for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
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unsigned Reg = CSI[I].getReg();
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if (SystemZ::FP64BitRegClass.contains(Reg))
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TII->loadRegFromStackSlot(MBB, MBBI, Reg, CSI[I].getFrameIdx(),
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&SystemZ::FP64BitRegClass, TRI);
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if (SystemZ::VR128BitRegClass.contains(Reg))
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TII->loadRegFromStackSlot(MBB, MBBI, Reg, CSI[I].getFrameIdx(),
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&SystemZ::VR128BitRegClass, TRI);
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}
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// Restore call-saved GPRs (but not call-clobbered varargs, which at
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@ -425,7 +433,7 @@ void SystemZFrameLowering::emitPrologue(MachineFunction &MF,
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I->addLiveIn(SystemZ::R11D);
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}
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// Skip over the FPR saves.
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// Skip over the FPR/VR saves.
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SmallVector<unsigned, 8> CFIIndexes;
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for (auto &Save : CSI) {
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unsigned Reg = Save.getReg();
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@ -436,6 +444,14 @@ void SystemZFrameLowering::emitPrologue(MachineFunction &MF,
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++MBBI;
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else
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llvm_unreachable("Couldn't skip over FPR save");
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} else if (SystemZ::VR128BitRegClass.contains(Reg)) {
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if (MBBI != MBB.end() &&
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MBBI->getOpcode() == SystemZ::VST)
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++MBBI;
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else
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llvm_unreachable("Couldn't skip over VR save");
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} else
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continue;
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// Add CFI for the this save.
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unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
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@ -447,8 +463,7 @@ void SystemZFrameLowering::emitPrologue(MachineFunction &MF,
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nullptr, DwarfReg, SPOffsetFromCFA + Offset));
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CFIIndexes.push_back(CFIIndex);
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}
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}
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// Complete the CFI for the FPR saves, modelling them as taking effect
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// Complete the CFI for the FPR/VR saves, modelling them as taking effect
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// after the last save.
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for (auto CFIIndex : CFIIndexes) {
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BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
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@ -108,6 +108,10 @@ SystemZRegisterInfo::getRegAllocationHints(unsigned VirtReg,
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const MCPhysReg *
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SystemZRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>();
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if (MF->getFunction().getCallingConv() == CallingConv::AnyReg)
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return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_SaveList
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: CSR_SystemZ_AllRegs_SaveList;
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if (MF->getSubtarget().getTargetLowering()->supportSwiftError() &&
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MF->getFunction().getAttributes().hasAttrSomewhere(
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Attribute::SwiftError))
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@ -118,6 +122,10 @@ SystemZRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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const uint32_t *
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SystemZRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
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CallingConv::ID CC) const {
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const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>();
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if (CC == CallingConv::AnyReg)
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return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_RegMask
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: CSR_SystemZ_AllRegs_RegMask;
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if (MF.getSubtarget().getTargetLowering()->supportSwiftError() &&
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MF.getFunction().getAttributes().hasAttrSomewhere(
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Attribute::SwiftError))
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@ -0,0 +1,65 @@
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Make sure all regs are spilled
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define anyregcc void @anyregcc1() {
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entry:
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;CHECK-LABEL: anyregcc1
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;CHECK: stmg %r2, %r15, 16(%r15)
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;CHECK: std %f0,
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;CHECK: std %f1,
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;CHECK: std %f2,
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;CHECK: std %f3,
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;CHECK: std %f4,
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;CHECK: std %f5,
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;CHECK: std %f6,
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;CHECK: std %f7,
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;CHECK: std %f8,
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;CHECK: std %f9,
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;CHECK: std %f10,
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;CHECK: std %f11,
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;CHECK: std %f12,
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;CHECK: std %f13,
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;CHECK: std %f14,
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;CHECK: std %f15,
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call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15}"() nounwind
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ret void
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}
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; Make sure we don't spill any FPs
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declare anyregcc void @foo()
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define void @anyregcc2() {
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entry:
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;CHECK-LABEL: anyregcc2
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;CHECK-NOT: std
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;CHECK: std %f8,
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;CHECK-NEXT: std %f9,
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;CHECK-NEXT: std %f10,
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;CHECK-NEXT: std %f11,
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;CHECK-NEXT: std %f12,
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;CHECK-NEXT: std %f13,
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;CHECK-NEXT: std %f14,
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;CHECK-NEXT: std %f15,
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;CHECK-NOT: std
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%a0 = call double asm sideeffect "", "={f0}"() nounwind
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%a1 = call double asm sideeffect "", "={f1}"() nounwind
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%a2 = call double asm sideeffect "", "={f2}"() nounwind
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%a3 = call double asm sideeffect "", "={f3}"() nounwind
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%a4 = call double asm sideeffect "", "={f4}"() nounwind
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%a5 = call double asm sideeffect "", "={f5}"() nounwind
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%a6 = call double asm sideeffect "", "={f6}"() nounwind
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%a7 = call double asm sideeffect "", "={f7}"() nounwind
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%a8 = call double asm sideeffect "", "={f8}"() nounwind
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%a9 = call double asm sideeffect "", "={f9}"() nounwind
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%a10 = call double asm sideeffect "", "={f10}"() nounwind
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%a11 = call double asm sideeffect "", "={f11}"() nounwind
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%a12 = call double asm sideeffect "", "={f12}"() nounwind
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%a13 = call double asm sideeffect "", "={f13}"() nounwind
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%a14 = call double asm sideeffect "", "={f14}"() nounwind
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%a15 = call double asm sideeffect "", "={f15}"() nounwind
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call anyregcc void @foo()
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call void asm sideeffect "", "{f0},{f1},{f2},{f3},{f4},{f5},{f6},{f7},{f8},{f9},{f10},{f11},{f12},{f13},{f14},{f15}"(double %a0, double %a1, double %a2, double %a3, double %a4, double %a5, double %a6, double %a7, double %a8, double %a9, double %a10, double %a11, double %a12, double %a13, double %a14, double %a15)
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ret void
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}
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declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
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declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
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@ -0,0 +1,99 @@
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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; Make sure all regs are spilled
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define anyregcc void @anyregcc1() {
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entry:
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;CHECK-LABEL: anyregcc1
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;CHECK: stmg %r2, %r15, 16(%r15)
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;CHECK: vst %v0,
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;CHECK: vst %v1,
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;CHECK: vst %v2,
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;CHECK: vst %v3,
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;CHECK: vst %v4,
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;CHECK: vst %v5,
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;CHECK: vst %v6,
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;CHECK: vst %v7,
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;CHECK: vst %v8,
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;CHECK: vst %v9,
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;CHECK: vst %v10,
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;CHECK: vst %v11,
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;CHECK: vst %v12,
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;CHECK: vst %v13,
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;CHECK: vst %v14,
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;CHECK: vst %v15,
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;CHECK: vst %v16,
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;CHECK: vst %v17,
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;CHECK: vst %v18,
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;CHECK: vst %v19,
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;CHECK: vst %v20,
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;CHECK: vst %v21,
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;CHECK: vst %v22,
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;CHECK: vst %v23,
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;CHECK: vst %v24,
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;CHECK: vst %v25,
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;CHECK: vst %v26,
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;CHECK: vst %v27,
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;CHECK: vst %v28,
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;CHECK: vst %v29,
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;CHECK: vst %v30,
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;CHECK: vst %v31,
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call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"() nounwind
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ret void
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}
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; Make sure we don't spill any FPs
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declare anyregcc void @foo()
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define void @anyregcc2() {
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entry:
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;CHECK-LABEL: anyregcc2
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;CHECK-NOT: std
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;CHECK-NOT: vst
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;CHECK: std %f8,
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;CHECK-NEXT: std %f9,
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;CHECK-NEXT: std %f10,
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;CHECK-NEXT: std %f11,
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;CHECK-NEXT: std %f12,
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;CHECK-NEXT: std %f13,
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;CHECK-NEXT: std %f14,
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;CHECK-NEXT: std %f15,
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;CHECK-NOT: std
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;CHECK-NOT: vst
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%a0 = call <2 x i64> asm sideeffect "", "={v0}"() nounwind
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%a1 = call <2 x i64> asm sideeffect "", "={v1}"() nounwind
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%a2 = call <2 x i64> asm sideeffect "", "={v2}"() nounwind
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%a3 = call <2 x i64> asm sideeffect "", "={v3}"() nounwind
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%a4 = call <2 x i64> asm sideeffect "", "={v4}"() nounwind
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%a5 = call <2 x i64> asm sideeffect "", "={v5}"() nounwind
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%a6 = call <2 x i64> asm sideeffect "", "={v6}"() nounwind
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%a7 = call <2 x i64> asm sideeffect "", "={v7}"() nounwind
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%a8 = call <2 x i64> asm sideeffect "", "={v8}"() nounwind
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%a9 = call <2 x i64> asm sideeffect "", "={v9}"() nounwind
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%a10 = call <2 x i64> asm sideeffect "", "={v10}"() nounwind
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%a11 = call <2 x i64> asm sideeffect "", "={v11}"() nounwind
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%a12 = call <2 x i64> asm sideeffect "", "={v12}"() nounwind
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%a13 = call <2 x i64> asm sideeffect "", "={v13}"() nounwind
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%a14 = call <2 x i64> asm sideeffect "", "={v14}"() nounwind
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%a15 = call <2 x i64> asm sideeffect "", "={v15}"() nounwind
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%a16 = call <2 x i64> asm sideeffect "", "={v16}"() nounwind
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%a17 = call <2 x i64> asm sideeffect "", "={v17}"() nounwind
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%a18 = call <2 x i64> asm sideeffect "", "={v18}"() nounwind
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%a19 = call <2 x i64> asm sideeffect "", "={v19}"() nounwind
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%a20 = call <2 x i64> asm sideeffect "", "={v20}"() nounwind
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%a21 = call <2 x i64> asm sideeffect "", "={v21}"() nounwind
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%a22 = call <2 x i64> asm sideeffect "", "={v22}"() nounwind
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%a23 = call <2 x i64> asm sideeffect "", "={v23}"() nounwind
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%a24 = call <2 x i64> asm sideeffect "", "={v24}"() nounwind
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%a25 = call <2 x i64> asm sideeffect "", "={v25}"() nounwind
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%a26 = call <2 x i64> asm sideeffect "", "={v26}"() nounwind
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%a27 = call <2 x i64> asm sideeffect "", "={v27}"() nounwind
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%a28 = call <2 x i64> asm sideeffect "", "={v28}"() nounwind
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%a29 = call <2 x i64> asm sideeffect "", "={v29}"() nounwind
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%a30 = call <2 x i64> asm sideeffect "", "={v30}"() nounwind
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%a31 = call <2 x i64> asm sideeffect "", "={v31}"() nounwind
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call anyregcc void @foo()
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call void asm sideeffect "", "{v0},{v1},{v2},{v3},{v4},{v5},{v6},{v7},{v8},{v9},{v10},{v11},{v12},{v13},{v14},{v15},{v16},{v17},{v18},{v19},{v20},{v21},{v22},{v23},{v24},{v25},{v26},{v27},{v28},{v29},{v30},{v31}"(<2 x i64> %a0, <2 x i64> %a1, <2 x i64> %a2, <2 x i64> %a3, <2 x i64> %a4, <2 x i64> %a5, <2 x i64> %a6, <2 x i64> %a7, <2 x i64> %a8, <2 x i64> %a9, <2 x i64> %a10, <2 x i64> %a11, <2 x i64> %a12, <2 x i64> %a13, <2 x i64> %a14, <2 x i64> %a15, <2 x i64> %a16, <2 x i64> %a17, <2 x i64> %a18, <2 x i64> %a19, <2 x i64> %a20, <2 x i64> %a21, <2 x i64> %a22, <2 x i64> %a23, <2 x i64> %a24, <2 x i64> %a25, <2 x i64> %a26, <2 x i64> %a27, <2 x i64> %a28, <2 x i64> %a29, <2 x i64> %a30, <2 x i64> %a31)
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ret void
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}
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declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
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declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
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@ -0,0 +1,449 @@
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Stackmap Header: no constants - 6 callsites
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; CHECK: .section .llvm_stackmaps
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; CHECK-NEXT: __LLVM_StackMaps:
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; Header
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; CHECK-NEXT: .byte 3
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 0
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; Num Functions
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; CHECK-NEXT: .long 8
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; Num Constants
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; CHECK-NEXT: .long 0
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; Num Callsites
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; CHECK-NEXT: .long 8
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; Functions and stack size
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; CHECK-NEXT: .quad test
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; CHECK-NEXT: .quad 160
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; CHECK-NEXT: .quad 1
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; CHECK-NEXT: .quad property_access1
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; CHECK-NEXT: .quad 160
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; CHECK-NEXT: .quad 1
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; CHECK-NEXT: .quad property_access2
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; CHECK-NEXT: .quad 168
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; CHECK-NEXT: .quad 1
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; CHECK-NEXT: .quad property_access3
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; CHECK-NEXT: .quad 168
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; CHECK-NEXT: .quad 1
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; CHECK-NEXT: .quad anyreg_test1
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; CHECK-NEXT: .quad 160
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; CHECK-NEXT: .quad 1
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; CHECK-NEXT: .quad anyreg_test2
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; CHECK-NEXT: .quad 160
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; CHECK-NEXT: .quad 1
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; CHECK-NEXT: .quad patchpoint_spilldef
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; CHECK-NEXT: .quad 168
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; CHECK-NEXT: .quad 1
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; CHECK-NEXT: .quad patchpoint_spillargs
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; CHECK-NEXT: .quad 192
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; CHECK-NEXT: .quad 1
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; No constants
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; Callsites
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; test
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; CHECK: .long .L{{.*}}-test
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; CHECK-NEXT: .short 0
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; 3 locations
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; CHECK-NEXT: .short 3
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; Loc 0: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 4
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; CHECK-NEXT: .short {{[0-9]+}}
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .long 0
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; Loc 1: Register
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; CHECK-NEXT: .byte 1
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 4
|
||||
; CHECK-NEXT: .short {{[0-9]+}}
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .long 0
|
||||
; Loc 2: Constant 3
|
||||
; CHECK-NEXT: .byte 4
|
||||
; CHECK-NEXT: .byte 0
|
||||
; CHECK-NEXT: .short 8
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .long 3
|
||||
define i64 @test() nounwind ssp uwtable {
|
||||
entry:
|
||||
call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 0, i32 14, i8* null, i32 2, i32 1, i32 2, i64 3)
|
||||
ret i64 0
|
||||
}
|
||||
|
||||
; property access 1 - %obj is an anyreg call argument and should therefore be in a register
|
||||
; CHECK: .long .L{{.*}}-property_access1
|
||||
; CHECK-NEXT: .short 0
|
||||
; 2 locations
|
||||
; CHECK-NEXT: .short 2
|
||||
; Loc 0: Register <-- this is the return register
|
||||
; CHECK-NEXT: .byte 1
|
||||
; CHECK-NEXT: .byte 0
|
||||
; CHECK-NEXT: .short 8
|
||||
; CHECK-NEXT: .short {{[0-9]+}}
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .long 0
|
||||
; Loc 1: Register
|
||||
; CHECK-NEXT: .byte 1
|
||||
; CHECK-NEXT: .byte 0
|
||||
; CHECK-NEXT: .short 8
|
||||
; CHECK-NEXT: .short {{[0-9]+}}
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .long 0
|
||||
define i64 @property_access1(i8* %obj) nounwind ssp uwtable {
|
||||
entry:
|
||||
%f = inttoptr i64 12297829382473034410 to i8*
|
||||
%ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 1, i32 14, i8* %f, i32 1, i8* %obj)
|
||||
ret i64 %ret
|
||||
}
|
||||
|
||||
; property access 2 - %obj is an anyreg call argument and should therefore be in a register
|
||||
; CHECK: .long .L{{.*}}-property_access2
|
||||
; CHECK-NEXT: .short 0
|
||||
; 2 locations
|
||||
; CHECK-NEXT: .short 2
|
||||
; Loc 0: Register <-- this is the return register
|
||||
; CHECK-NEXT: .byte 1
|
||||
; CHECK-NEXT: .byte 0
|
||||
; CHECK-NEXT: .short 8
|
||||
; CHECK-NEXT: .short {{[0-9]+}}
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .long 0
|
||||
; Loc 1: Register
|
||||
; CHECK-NEXT: .byte 1
|
||||
; CHECK-NEXT: .byte 0
|
||||
; CHECK-NEXT: .short 8
|
||||
; CHECK-NEXT: .short {{[0-9]+}}
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .long 0
|
||||
define i64 @property_access2() nounwind ssp uwtable {
|
||||
entry:
|
||||
%obj = alloca i64, align 8
|
||||
%f = inttoptr i64 12297829382473034410 to i8*
|
||||
%ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 14, i8* %f, i32 1, i64* %obj)
|
||||
ret i64 %ret
|
||||
}
|
||||
|
||||
; property access 3 - %obj is a frame index
|
||||
; CHECK: .long .L{{.*}}-property_access3
|
||||
; CHECK-NEXT: .short 0
|
||||
; 2 locations
|
||||
; CHECK-NEXT: .short 2
|
||||
; Loc 0: Register <-- this is the return register
|
||||
; CHECK-NEXT: .byte 1
|
||||
; CHECK-NEXT: .byte 0
|
||||
; CHECK-NEXT: .short 8
|
||||
; CHECK-NEXT: .short {{[0-9]+}}
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .long 0
|
||||
; Loc 1: Direct %r15 + 160
|
||||
; CHECK-NEXT: .byte 2
|
||||
; CHECK-NEXT: .byte 0
|
||||
; CHECK-NEXT: .short 8
|
||||
; CHECK-NEXT: .short 15
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .long 160
|
||||
define i64 @property_access3() nounwind ssp uwtable {
|
||||
entry:
|
||||
%obj = alloca i64, align 8
|
||||
%f = inttoptr i64 12297829382473034410 to i8*
|
||||
%ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 3, i32 14, i8* %f, i32 0, i64* %obj)
|
||||
ret i64 %ret
|
||||
}
|
||||
|
||||
; anyreg_test1
|
||||
; CHECK: .long .L{{.*}}-anyreg_test1
|
||||
; CHECK-NEXT: .short 0
|
||||
; 13 locations
|
||||
; CHECK-NEXT: .short 13
|
||||
; Loc 0: Register <-- this is the return register
|
||||
; CHECK-NEXT: .byte 1
|
||||
; CHECK-NEXT: .byte 0
|
||||
; CHECK-NEXT: .short 8
|
||||
; CHECK-NEXT: .short {{[0-9]+}}
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .long 0
|
||||
; Loc 1: Register
|
||||
; CHECK-NEXT: .byte 1
|
||||
; CHECK-NEXT: .byte 0
|
||||
; CHECK-NEXT: .short 8
|
||||
; CHECK-NEXT: .short {{[0-9]+}}
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .long 0
|
||||
; Loc 2: Register
|
||||
; CHECK-NEXT: .byte 1
|
||||
; CHECK-NEXT: .byte 0
|
||||
; CHECK-NEXT: .short 8
|
||||
; CHECK-NEXT: .short {{[0-9]+}}
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .long 0
|
||||
; Loc 3: Register
|
||||
; CHECK-NEXT: .byte 1
|
||||
; CHECK-NEXT: .byte 0
|
||||
; CHECK-NEXT: .short 8
|
||||
; CHECK-NEXT: .short {{[0-9]+}}
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .long 0
|
||||
; Loc 4: Register
|
||||
; CHECK-NEXT: .byte 1
|
||||
; CHECK-NEXT: .byte 0
|
||||
; CHECK-NEXT: .short 8
|
||||
; CHECK-NEXT: .short {{[0-9]+}}
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .long 0
|
||||
; Loc 5: Register
|
||||
; CHECK-NEXT: .byte 1
|
||||
; CHECK-NEXT: .byte 0
|
||||
; CHECK-NEXT: .short 8
|
||||
; CHECK-NEXT: .short {{[0-9]+}}
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .long 0
|
||||
; Loc 6: Register
|
||||
; CHECK-NEXT: .byte 1
|
||||
; CHECK-NEXT: .byte 0
|
||||
; CHECK-NEXT: .short 8
|
||||
; CHECK-NEXT: .short {{[0-9]+}}
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .long 0
|
||||
; Loc 7: Register
|
||||
; CHECK-NEXT: .byte 1
|
||||
; CHECK-NEXT: .byte 0
|
||||
; CHECK-NEXT: .short 8
|
||||
; CHECK-NEXT: .short {{[0-9]+}}
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .long 0
|
||||
; Loc 8: Register
|
||||
; CHECK-NEXT: .byte 1
|
||||
; CHECK-NEXT: .byte 0
|
||||
; CHECK-NEXT: .short 8
|
||||
; CHECK-NEXT: .short {{[0-9]+}}
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .long 0
|
||||
; Loc 9: Register
|
||||
; CHECK-NEXT: .byte 1
|
||||
; CHECK-NEXT: .byte 0
|
||||
; CHECK-NEXT: .short 8
|
||||
; CHECK-NEXT: .short {{[0-9]+}}
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .long 0
|
||||
; Loc 10: Register
|
||||
; CHECK-NEXT: .byte 1
|
||||
; CHECK-NEXT: .byte 0
|
||||
; CHECK-NEXT: .short 8
|
||||
; CHECK-NEXT: .short {{[0-9]+}}
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .long 0
|
||||
; Loc 11: Register
|
||||
; CHECK-NEXT: .byte 1
|
||||
; CHECK-NEXT: .byte 0
|
||||
; CHECK-NEXT: .short 8
|
||||
; CHECK-NEXT: .short {{[0-9]+}}
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .long 0
|
||||
; Loc 12: Register
|
||||
; CHECK-NEXT: .byte 1
|
||||
; CHECK-NEXT: .byte 0
|
||||
; CHECK-NEXT: .short 8
|
||||
; CHECK-NEXT: .short {{[0-9]+}}
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .long 0
|
||||
define i64 @anyreg_test1(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12) nounwind ssp uwtable {
|
||||
entry:
|
||||
%f = inttoptr i64 12297829382473034410 to i8*
|
||||
%ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 4, i32 14, i8* %f, i32 12, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12)
|
||||
ret i64 %ret
|
||||
}
|
||||
|
||||
; anyreg_test2
|
||||
; CHECK: .long .L{{.*}}-anyreg_test2
|
||||
; CHECK-NEXT: .short 0
|
||||
; 13 locations
|
||||
; CHECK-NEXT: .short 13
|
||||
; Loc 0: Register <-- this is the return register
|
||||
; CHECK-NEXT: .byte 1
|
||||
; CHECK-NEXT: .byte 0
|
||||
; CHECK-NEXT: .short 8
|
||||
; CHECK-NEXT: .short {{[0-9]+}}
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .long 0
|
||||
; Loc 1: Register
|
||||
; CHECK-NEXT: .byte 1
|
||||
; CHECK-NEXT: .byte 0
|
||||
; CHECK-NEXT: .short 8
|
||||
; CHECK-NEXT: .short {{[0-9]+}}
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .long 0
|
||||
; Loc 2: Register
|
||||
; CHECK-NEXT: .byte 1
|
||||
; CHECK-NEXT: .byte 0
|
||||
; CHECK-NEXT: .short 8
|
||||
; CHECK-NEXT: .short {{[0-9]+}}
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .long 0
|
||||
; Loc 3: Register
|
||||
; CHECK-NEXT: .byte 1
|
||||
; CHECK-NEXT: .byte 0
|
||||
; CHECK-NEXT: .short 8
|
||||
; CHECK-NEXT: .short {{[0-9]+}}
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .long 0
|
||||
; Loc 4: Register
|
||||
; CHECK-NEXT: .byte 1
|
||||
; CHECK-NEXT: .byte 0
|
||||
; CHECK-NEXT: .short 8
|
||||
; CHECK-NEXT: .short {{[0-9]+}}
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .long 0
|
||||
; Loc 5: Register
|
||||
; CHECK-NEXT: .byte 1
|
||||
; CHECK-NEXT: .byte 0
|
||||
; CHECK-NEXT: .short 8
|
||||
; CHECK-NEXT: .short {{[0-9]+}}
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .long 0
|
||||
; Loc 6: Register
|
||||
; CHECK-NEXT: .byte 1
|
||||
; CHECK-NEXT: .byte 0
|
||||
; CHECK-NEXT: .short 8
|
||||
; CHECK-NEXT: .short {{[0-9]+}}
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .long 0
|
||||
; Loc 7: Register
|
||||
; CHECK-NEXT: .byte 1
|
||||
; CHECK-NEXT: .byte 0
|
||||
; CHECK-NEXT: .short 8
|
||||
; CHECK-NEXT: .short {{[0-9]+}}
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .long 0
|
||||
; Loc 8: Register
|
||||
; CHECK-NEXT: .byte 1
|
||||
; CHECK-NEXT: .byte 0
|
||||
; CHECK-NEXT: .short 8
|
||||
; CHECK-NEXT: .short {{[0-9]+}}
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .long 0
|
||||
; Loc 9: Register
|
||||
; CHECK-NEXT: .byte 1
|
||||
; CHECK-NEXT: .byte 0
|
||||
; CHECK-NEXT: .short 8
|
||||
; CHECK-NEXT: .short {{[0-9]+}}
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .long 0
|
||||
; Loc 10: Register
|
||||
; CHECK-NEXT: .byte 1
|
||||
; CHECK-NEXT: .byte 0
|
||||
; CHECK-NEXT: .short 8
|
||||
; CHECK-NEXT: .short {{[0-9]+}}
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .long 0
|
||||
; Loc 11: Register
|
||||
; CHECK-NEXT: .byte 1
|
||||
; CHECK-NEXT: .byte 0
|
||||
; CHECK-NEXT: .short 8
|
||||
; CHECK-NEXT: .short {{[0-9]+}}
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .long 0
|
||||
; Loc 12: Register
|
||||
; CHECK-NEXT: .byte 1
|
||||
; CHECK-NEXT: .byte 0
|
||||
; CHECK-NEXT: .short 8
|
||||
; CHECK-NEXT: .short {{[0-9]+}}
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .long 0
|
||||
define i64 @anyreg_test2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12) nounwind ssp uwtable {
|
||||
entry:
|
||||
%f = inttoptr i64 12297829382473034410 to i8*
|
||||
%ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 14, i8* %f, i32 8, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12)
|
||||
ret i64 %ret
|
||||
}
|
||||
|
||||
; Test spilling the return value of an anyregcc call.
|
||||
;
|
||||
; <rdar://problem/15432754> [JS] Assertion: "Folded a def to a non-store!"
|
||||
;
|
||||
; CHECK: .long .L{{.*}}-patchpoint_spilldef
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .short 3
|
||||
; Loc 0: Register (some register that will be spilled to the stack)
|
||||
; CHECK-NEXT: .byte 1
|
||||
; CHECK-NEXT: .byte 0
|
||||
; CHECK-NEXT: .short 8
|
||||
; CHECK-NEXT: .short {{[0-9]+}}
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .long 0
|
||||
; Loc 1: Register %r2
|
||||
; CHECK-NEXT: .byte 1
|
||||
; CHECK-NEXT: .byte 0
|
||||
; CHECK-NEXT: .short 8
|
||||
; CHECK-NEXT: .short 2
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .long 0
|
||||
; Loc 1: Register %r3
|
||||
; CHECK-NEXT: .byte 1
|
||||
; CHECK-NEXT: .byte 0
|
||||
; CHECK-NEXT: .short 8
|
||||
; CHECK-NEXT: .short 3
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .long 0
|
||||
define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
|
||||
entry:
|
||||
%result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 14, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2)
|
||||
tail call void asm sideeffect "nopr %r0", "~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14}"() nounwind
|
||||
ret i64 %result
|
||||
}
|
||||
|
||||
; Test spilling the arguments of an anyregcc call.
|
||||
;
|
||||
; <rdar://problem/15487687> [JS] AnyRegCC argument ends up being spilled
|
||||
;
|
||||
; CHECK: .long .L{{.*}}-patchpoint_spillargs
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .short 5
|
||||
; Loc 0: Return a register
|
||||
; CHECK-NEXT: .byte 1
|
||||
; CHECK-NEXT: .byte 0
|
||||
; CHECK-NEXT: .short 8
|
||||
; CHECK-NEXT: .short {{[0-9]+}}
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .long 0
|
||||
; Loc 1: Arg0 in a Register
|
||||
; CHECK-NEXT: .byte 1
|
||||
; CHECK-NEXT: .byte 0
|
||||
; CHECK-NEXT: .short 8
|
||||
; CHECK-NEXT: .short {{[0-9]+}}
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .long 0
|
||||
; Loc 2: Arg1 in a Register
|
||||
; CHECK-NEXT: .byte 1
|
||||
; CHECK-NEXT: .byte 0
|
||||
; CHECK-NEXT: .short 8
|
||||
; CHECK-NEXT: .short {{[0-9]+}}
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .long 0
|
||||
; Loc 3: Arg2 spilled to %r15 +
|
||||
; CHECK-NEXT: .byte 3
|
||||
; CHECK-NEXT: .byte 0
|
||||
; CHECK-NEXT: .short 8
|
||||
; CHECK-NEXT: .short 15
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .long
|
||||
; Loc 4: Arg3 spilled to %r15 +
|
||||
; CHECK-NEXT: .byte 3
|
||||
; CHECK-NEXT: .byte 0
|
||||
; CHECK-NEXT: .short 8
|
||||
; CHECK-NEXT: .short 15
|
||||
; CHECK-NEXT: .short 0
|
||||
; CHECK-NEXT: .long
|
||||
define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
|
||||
entry:
|
||||
tail call void asm sideeffect "nopr %r0", "~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14}"() nounwind
|
||||
%result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 13, i32 14, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
|
||||
ret i64 %result
|
||||
}
|
||||
|
||||
declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
|
||||
declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
|
||||
Loading…
Reference in New Issue