[clang][BFloat] Add create/set/get/dup intrinsics
Summary: This patch is part of a series that adds support for the Bfloat16 extension of the Armv8.6-a architecture, as detailed here: https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-architecture-developments-armv8-6-a The bfloat type and its properties are specified in the Arm Architecture Reference Manual: https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile The following people contributed to this patch: - Luke Cheeseman - Momchil Velikov - Luke Geeson - Ties Stuij - Mikhail Maltsev Reviewers: t.p.northover, sdesmalen, fpetrogalli, LukeGeeson, stuij, labrinea Reviewed By: labrinea Subscribers: miyuki, dmgreen, labrinea, kristof.beyls, ilya-biryukov, MaskRay, jkorous, arphaman, usaxena95, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D79710
This commit is contained in:
Ties Stuij
parent
80845db6a5
commit
8b137a4306
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@ -190,20 +190,28 @@ def OP_SCALAR_QRDMLAH_LN : Op<(call "vqadd", $p0, (call "vqrdmulh", $p1,
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def OP_SCALAR_QRDMLSH_LN : Op<(call "vqsub", $p0, (call "vqrdmulh", $p1,
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(call "vget_lane", $p2, $p3)))>;
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def OP_SCALAR_HALF_GET_LN : Op<(bitcast "float16_t",
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(call "vget_lane",
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(bitcast "int16x4_t", $p0), $p1))>;
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def OP_SCALAR_HALF_GET_LNQ : Op<(bitcast "float16_t",
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(call "vget_lane",
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(bitcast "int16x8_t", $p0), $p1))>;
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def OP_SCALAR_HALF_SET_LN : Op<(bitcast "float16x4_t",
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(call "vset_lane",
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(bitcast "int16_t", $p0),
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(bitcast "int16x4_t", $p1), $p2))>;
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def OP_SCALAR_HALF_SET_LNQ : Op<(bitcast "float16x8_t",
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(call "vset_lane",
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(bitcast "int16_t", $p0),
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(bitcast "int16x8_t", $p1), $p2))>;
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multiclass ScalarGetSetLaneOpsF16<string scalarTy,
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string vectorTy4, string vectorTy8> {
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def _GET_LN : Op<(bitcast scalarTy,
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(call "vget_lane",
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(bitcast "int16x4_t", $p0), $p1))>;
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def _GET_LNQ : Op<(bitcast scalarTy,
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(call "vget_lane",
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(bitcast "int16x8_t", $p0), $p1))>;
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def _SET_LN : Op<(bitcast vectorTy4,
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(call "vset_lane",
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(bitcast "int16_t", $p0),
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(bitcast "int16x4_t", $p1), $p2))>;
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def _SET_LNQ : Op<(bitcast vectorTy8,
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(call "vset_lane",
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(bitcast "int16_t", $p0),
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(bitcast "int16x8_t", $p1), $p2))>;
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}
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defm OP_SCALAR_HALF: ScalarGetSetLaneOpsF16<"float16_t",
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"float16x4_t", "float16x8_t">;
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defm OP_SCALAR_BF16: ScalarGetSetLaneOpsF16<"bfloat16_t",
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"bfloat16x4_t", "bfloat16x8_t">;
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def OP_DOT_LN
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: Op<(call "vdot", $p0, $p1,
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@ -247,6 +255,12 @@ def SPLATQ : WInst<"splat_laneq", ".(!Q)I",
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"UcUsUicsilPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUlhdQhQdPlQPl"> {
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let isLaneQ = 1;
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}
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let ArchGuard = "defined(__ARM_FEATURE_BF16_VECTOR_ARITHMETIC)" in {
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def SPLAT_BF : WInst<"splat_lane", ".(!q)I", "bQb">;
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def SPLATQ_BF : WInst<"splat_laneq", ".(!Q)I", "bQb"> {
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let isLaneQ = 1;
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}
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}
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//===----------------------------------------------------------------------===//
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// Intrinsics
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@ -1841,3 +1855,39 @@ let ArchGuard = "defined(__ARM_FEATURE_COMPLEX) && defined(__aarch64__)" in {
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def VCADDQ_ROT90_FP64 : SInst<"vcaddq_rot90", "QQQ", "d">;
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def VCADDQ_ROT270_FP64 : SInst<"vcaddq_rot270", "QQQ", "d">;
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}
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// V8.2-A BFloat intrinsics
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let ArchGuard = "defined(__ARM_FEATURE_BF16_VECTOR_ARITHMETIC)" in {
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def VCREATE_BF : NoTestOpInst<"vcreate", ".(IU>)", "b", OP_CAST> {
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let BigEndianSafe = 1;
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}
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def VDUP_N_BF : WOpInst<"vdup_n", ".1", "bQb", OP_DUP>;
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def VDUP_LANE_BF : WOpInst<"vdup_lane", ".qI", "bQb", OP_DUP_LN>;
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def VDUP_LANEQ_BF: WOpInst<"vdup_laneq", ".QI", "bQb", OP_DUP_LN> {
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let isLaneQ = 1;
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}
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def VCOMBINE_BF : NoTestOpInst<"vcombine", "Q..", "b", OP_CONC>;
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def VGET_HIGH_BF : NoTestOpInst<"vget_high", ".Q", "b", OP_HI>;
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def VGET_LOW_BF : NoTestOpInst<"vget_low", ".Q", "b", OP_LO>;
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def VGET_LANE_BF : IOpInst<"vget_lane", "1.I", "b", OP_SCALAR_BF16_GET_LN>;
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def VSET_LANE_BF : IOpInst<"vset_lane", ".1.I", "b", OP_SCALAR_BF16_SET_LN>;
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def VGET_LANEQ_BF : IOpInst<"vget_lane", "1.I", "Qb", OP_SCALAR_BF16_GET_LNQ>;
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def VSET_LANEQ_BF : IOpInst<"vset_lane", ".1.I", "Qb", OP_SCALAR_BF16_SET_LNQ>;
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}
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let ArchGuard = "defined(__ARM_FEATURE_BF16_VECTOR_ARITHMETIC) && !defined(__aarch64__)" in {
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def SCALAR_VDUP_LANE_BF_A32 : IOpInst<"vduph_lane", "1.I", "b", OP_SCALAR_BF16_GET_LN>;
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def SCALAR_VDUP_LANEQ_BF_A32 : IOpInst<"vduph_laneq", "1.I", "Hb", OP_SCALAR_BF16_GET_LNQ>;
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}
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let ArchGuard = "defined(__ARM_FEATURE_BF16_VECTOR_ARITHMETIC) && defined(__aarch64__)" in {
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def SCALAR_VDUP_LANE_BF_A64 : IInst<"vdup_lane", "1.I", "Sb">;
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def SCALAR_VDUP_LANEQ_BF_A64 : IInst<"vdup_laneq", "1QI", "Sb"> {
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let isLaneQ = 1;
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}
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}
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@ -9368,10 +9368,12 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
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: Intrinsic::aarch64_neon_sqsub;
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return EmitNeonCall(CGM.getIntrinsic(AccInt, Int64Ty), Ops, "vqdmlXl");
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}
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case NEON::BI__builtin_neon_vduph_lane_bf16:
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case NEON::BI__builtin_neon_vduph_lane_f16: {
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return Builder.CreateExtractElement(Ops[0], EmitScalarExpr(E->getArg(1)),
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"vget_lane");
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}
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case NEON::BI__builtin_neon_vduph_laneq_bf16:
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case NEON::BI__builtin_neon_vduph_laneq_f16: {
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return Builder.CreateExtractElement(Ops[0], EmitScalarExpr(E->getArg(1)),
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"vgetq_lane");
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@ -0,0 +1,151 @@
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-feature +neon -target-feature +bf16 \
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// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg -instcombine | FileCheck %s
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#include <arm_neon.h>
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// CHECK-LABEL: @test_vcreate_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A:%.*]] to <4 x bfloat>
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// CHECK-NEXT: ret <4 x bfloat> [[TMP0]]
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//
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bfloat16x4_t test_vcreate_bf16(uint64_t a) {
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return vcreate_bf16(a);
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}
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// CHECK-LABEL: @test_vdup_n_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x bfloat> undef, bfloat [[V:%.*]], i32 0
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// CHECK-NEXT: [[VECINIT3_I:%.*]] = shufflevector <4 x bfloat> [[VECINIT_I]], <4 x bfloat> undef, <4 x i32> zeroinitializer
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// CHECK-NEXT: ret <4 x bfloat> [[VECINIT3_I]]
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//
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bfloat16x4_t test_vdup_n_bf16(bfloat16_t v) {
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return vdup_n_bf16(v);
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}
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// CHECK-LABEL: @test_vdupq_n_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x bfloat> undef, bfloat [[V:%.*]], i32 0
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// CHECK-NEXT: [[VECINIT7_I:%.*]] = shufflevector <8 x bfloat> [[VECINIT_I]], <8 x bfloat> undef, <8 x i32> zeroinitializer
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// CHECK-NEXT: ret <8 x bfloat> [[VECINIT7_I]]
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//
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bfloat16x8_t test_vdupq_n_bf16(bfloat16_t v) {
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return vdupq_n_bf16(v);
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}
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// CHECK-LABEL: @test_vdup_lane_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x bfloat> [[V:%.*]], <4 x bfloat> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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// CHECK-NEXT: ret <4 x bfloat> [[LANE]]
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//
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bfloat16x4_t test_vdup_lane_bf16(bfloat16x4_t v) {
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return vdup_lane_bf16(v, 1);
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}
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// CHECK-LABEL: @test_vdupq_lane_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x bfloat> [[V:%.*]], <4 x bfloat> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
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// CHECK-NEXT: ret <8 x bfloat> [[LANE]]
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//
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bfloat16x8_t test_vdupq_lane_bf16(bfloat16x4_t v) {
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return vdupq_lane_bf16(v, 1);
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}
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// CHECK-LABEL: @test_vdup_laneq_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[LANE:%.*]] = shufflevector <8 x bfloat> [[V:%.*]], <8 x bfloat> undef, <4 x i32> <i32 7, i32 7, i32 7, i32 7>
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// CHECK-NEXT: ret <4 x bfloat> [[LANE]]
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//
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bfloat16x4_t test_vdup_laneq_bf16(bfloat16x8_t v) {
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return vdup_laneq_bf16(v, 7);
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}
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// CHECK-LABEL: @test_vdupq_laneq_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[LANE:%.*]] = shufflevector <8 x bfloat> [[V:%.*]], <8 x bfloat> undef, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
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// CHECK-NEXT: ret <8 x bfloat> [[LANE]]
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//
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bfloat16x8_t test_vdupq_laneq_bf16(bfloat16x8_t v) {
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return vdupq_laneq_bf16(v, 7);
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}
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// CHECK-LABEL: @test_vcombine_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x bfloat> [[LOW:%.*]], <4 x bfloat> [[HIGH:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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// CHECK-NEXT: ret <8 x bfloat> [[SHUFFLE_I]]
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//
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bfloat16x8_t test_vcombine_bf16(bfloat16x4_t low, bfloat16x4_t high) {
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return vcombine_bf16(low, high);
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}
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// CHECK-LABEL: @test_vget_high_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x bfloat> [[A:%.*]], <8 x bfloat> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
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// CHECK-NEXT: ret <4 x bfloat> [[SHUFFLE_I]]
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//
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bfloat16x4_t test_vget_high_bf16(bfloat16x8_t a) {
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return vget_high_bf16(a);
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}
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// CHECK-LABEL: @test_vget_low_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x bfloat> [[A:%.*]], <8 x bfloat> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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// CHECK-NEXT: ret <4 x bfloat> [[SHUFFLE_I]]
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//
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bfloat16x4_t test_vget_low_bf16(bfloat16x8_t a) {
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return vget_low_bf16(a);
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}
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// CHECK-LABEL: @test_vget_lane_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[DOTCAST1:%.*]] = extractelement <4 x bfloat> [[V:%.*]], i32 1
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// CHECK-NEXT: ret bfloat [[DOTCAST1]]
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//
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bfloat16_t test_vget_lane_bf16(bfloat16x4_t v) {
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return vget_lane_bf16(v, 1);
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}
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// CHECK-LABEL: @test_vgetq_lane_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[DOTCAST1:%.*]] = extractelement <8 x bfloat> [[V:%.*]], i32 7
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// CHECK-NEXT: ret bfloat [[DOTCAST1]]
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//
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bfloat16_t test_vgetq_lane_bf16(bfloat16x8_t v) {
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return vgetq_lane_bf16(v, 7);
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}
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// CHECK-LABEL: @test_vset_lane_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x bfloat> [[V:%.*]], bfloat [[A:%.*]], i32 1
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// CHECK-NEXT: ret <4 x bfloat> [[TMP0]]
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//
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bfloat16x4_t test_vset_lane_bf16(bfloat16_t a, bfloat16x4_t v) {
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return vset_lane_bf16(a, v, 1);
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}
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// CHECK-LABEL: @test_vsetq_lane_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x bfloat> [[V:%.*]], bfloat [[A:%.*]], i32 7
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// CHECK-NEXT: ret <8 x bfloat> [[TMP0]]
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//
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bfloat16x8_t test_vsetq_lane_bf16(bfloat16_t a, bfloat16x8_t v) {
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return vsetq_lane_bf16(a, v, 7);
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}
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// CHECK-LABEL: @test_vduph_lane_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VGET_LANE:%.*]] = extractelement <4 x bfloat> [[V:%.*]], i32 1
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// CHECK-NEXT: ret bfloat [[VGET_LANE]]
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//
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bfloat16_t test_vduph_lane_bf16(bfloat16x4_t v) {
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return vduph_lane_bf16(v, 1);
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}
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// CHECK-LABEL: @test_vduph_laneq_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VGETQ_LANE:%.*]] = extractelement <8 x bfloat> [[V:%.*]], i32 7
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// CHECK-NEXT: ret bfloat [[VGETQ_LANE]]
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//
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bfloat16_t test_vduph_laneq_bf16(bfloat16x8_t v) {
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return vduph_laneq_bf16(v, 7);
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}
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@ -0,0 +1,151 @@
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// RUN: %clang_cc1 -triple armv8.6a-arm-none-eabi -target-feature +neon -target-feature +bf16 -mfloat-abi hard \
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// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg -instcombine | FileCheck %s
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#include <arm_neon.h>
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// CHECK-LABEL: @test_vcreate_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = bitcast i64 [[A:%.*]] to <4 x bfloat>
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// CHECK-NEXT: ret <4 x bfloat> [[TMP0]]
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//
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bfloat16x4_t test_vcreate_bf16(uint64_t a) {
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return vcreate_bf16(a);
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}
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// CHECK-LABEL: @test_vdup_n_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x bfloat> undef, bfloat [[V:%.*]], i32 0
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// CHECK-NEXT: [[VECINIT3_I:%.*]] = shufflevector <4 x bfloat> [[VECINIT_I]], <4 x bfloat> undef, <4 x i32> zeroinitializer
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// CHECK-NEXT: ret <4 x bfloat> [[VECINIT3_I]]
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//
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bfloat16x4_t test_vdup_n_bf16(bfloat16_t v) {
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return vdup_n_bf16(v);
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}
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// CHECK-LABEL: @test_vdupq_n_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x bfloat> undef, bfloat [[V:%.*]], i32 0
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// CHECK-NEXT: [[VECINIT7_I:%.*]] = shufflevector <8 x bfloat> [[VECINIT_I]], <8 x bfloat> undef, <8 x i32> zeroinitializer
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// CHECK-NEXT: ret <8 x bfloat> [[VECINIT7_I]]
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//
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bfloat16x8_t test_vdupq_n_bf16(bfloat16_t v) {
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return vdupq_n_bf16(v);
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}
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// CHECK-LABEL: @test_vdup_lane_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x bfloat> [[V:%.*]], <4 x bfloat> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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// CHECK-NEXT: ret <4 x bfloat> [[LANE]]
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//
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bfloat16x4_t test_vdup_lane_bf16(bfloat16x4_t v) {
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return vdup_lane_bf16(v, 1);
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}
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// CHECK-LABEL: @test_vdupq_lane_bf16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x bfloat> [[V:%.*]], <4 x bfloat> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
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// CHECK-NEXT: ret <8 x bfloat> [[LANE]]
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//
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bfloat16x8_t test_vdupq_lane_bf16(bfloat16x4_t v) {
|
||||
return vdupq_lane_bf16(v, 1);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: @test_vdup_laneq_bf16(
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[LANE:%.*]] = shufflevector <8 x bfloat> [[V:%.*]], <8 x bfloat> undef, <4 x i32> <i32 7, i32 7, i32 7, i32 7>
|
||||
// CHECK-NEXT: ret <4 x bfloat> [[LANE]]
|
||||
//
|
||||
bfloat16x4_t test_vdup_laneq_bf16(bfloat16x8_t v) {
|
||||
return vdup_laneq_bf16(v, 7);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: @test_vdupq_laneq_bf16(
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[LANE:%.*]] = shufflevector <8 x bfloat> [[V:%.*]], <8 x bfloat> undef, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
|
||||
// CHECK-NEXT: ret <8 x bfloat> [[LANE]]
|
||||
//
|
||||
bfloat16x8_t test_vdupq_laneq_bf16(bfloat16x8_t v) {
|
||||
return vdupq_laneq_bf16(v, 7);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: @test_vcombine_bf16(
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x bfloat> [[LOW:%.*]], <4 x bfloat> [[HIGH:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
// CHECK-NEXT: ret <8 x bfloat> [[SHUFFLE_I]]
|
||||
//
|
||||
bfloat16x8_t test_vcombine_bf16(bfloat16x4_t low, bfloat16x4_t high) {
|
||||
return vcombine_bf16(low, high);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: @test_vget_high_bf16(
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x bfloat> [[A:%.*]], <8 x bfloat> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
|
||||
// CHECK-NEXT: ret <4 x bfloat> [[SHUFFLE_I]]
|
||||
//
|
||||
bfloat16x4_t test_vget_high_bf16(bfloat16x8_t a) {
|
||||
return vget_high_bf16(a);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: @test_vget_low_bf16(
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x bfloat> [[A:%.*]], <8 x bfloat> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
// CHECK-NEXT: ret <4 x bfloat> [[SHUFFLE_I]]
|
||||
//
|
||||
bfloat16x4_t test_vget_low_bf16(bfloat16x8_t a) {
|
||||
return vget_low_bf16(a);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: @test_vget_lane_bf16(
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[DOTCAST1:%.*]] = extractelement <4 x bfloat> [[V:%.*]], i32 1
|
||||
// CHECK-NEXT: ret bfloat [[DOTCAST1]]
|
||||
//
|
||||
bfloat16_t test_vget_lane_bf16(bfloat16x4_t v) {
|
||||
return vget_lane_bf16(v, 1);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: @test_vgetq_lane_bf16(
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[DOTCAST1:%.*]] = extractelement <8 x bfloat> [[V:%.*]], i32 7
|
||||
// CHECK-NEXT: ret bfloat [[DOTCAST1]]
|
||||
//
|
||||
bfloat16_t test_vgetq_lane_bf16(bfloat16x8_t v) {
|
||||
return vgetq_lane_bf16(v, 7);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: @test_vset_lane_bf16(
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x bfloat> [[V:%.*]], bfloat [[A:%.*]], i32 1
|
||||
// CHECK-NEXT: ret <4 x bfloat> [[TMP0]]
|
||||
//
|
||||
bfloat16x4_t test_vset_lane_bf16(bfloat16_t a, bfloat16x4_t v) {
|
||||
return vset_lane_bf16(a, v, 1);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: @test_vsetq_lane_bf16(
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x bfloat> [[V:%.*]], bfloat [[A:%.*]], i32 7
|
||||
// CHECK-NEXT: ret <8 x bfloat> [[TMP0]]
|
||||
//
|
||||
bfloat16x8_t test_vsetq_lane_bf16(bfloat16_t a, bfloat16x8_t v) {
|
||||
return vsetq_lane_bf16(a, v, 7);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: @test_vduph_lane_bf16(
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[VGET_LANE:%.*]] = extractelement <4 x bfloat> [[V:%.*]], i32 1
|
||||
// CHECK-NEXT: ret bfloat [[VGET_LANE]]
|
||||
//
|
||||
bfloat16_t test_vduph_lane_bf16(bfloat16x4_t v) {
|
||||
return vduph_lane_bf16(v, 1);
|
||||
}
|
||||
|
||||
// CHECK-LABEL: @test_vduph_laneq_bf16(
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[VGETQ_LANE:%.*]] = extractelement <8 x bfloat> [[V:%.*]], i32 7
|
||||
// CHECK-NEXT: ret bfloat [[VGETQ_LANE]]
|
||||
//
|
||||
bfloat16_t test_vduph_laneq_bf16(bfloat16x8_t v) {
|
||||
return vduph_laneq_bf16(v, 7);
|
||||
}
|
||||
Loading…
Reference in New Issue